JPH0343847A - Data transfer system to cache memory - Google Patents

Abstract

PURPOSE:To shorten the access suppressing time caused by the transfer of data to a cache memory by writing the data read out of a main storage into the cache memory with a single clock after the cache mishit produced to a read request to be given to the main storage. CONSTITUTION:A signal 30 showing the timing where the read data is outputted to a system data bus 9 from a main storage is added to the 2 lower rank bits 31 of a flip-flop 25 which stores a CPU address at cache mishit. These added bits and signal are stored in a flip-flop 29. Then the selectors 11-14 select the output data of the flip-flops 5-8 in a cycle where the 4th main storage read data 10 is stored in one of flip-flops 5-8. The selected output data 17-20 are stored in the addresses of cache memories 1-4 pointed by a cache memory address 23 of the flip-flop 25 selected by a selector 26. Thus the data can be written into a cache memory with a single clock.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data transfer method to a cache memory, in particular,
This invention relates to a data transfer method from main memory to cache memory after a cache miss.

[Conventional technology]

Traditionally, this type of data transfer method transfers data from main memory to system memory.
There was one cache miss because the data sent over 4T via the data bus was sequentially written to the cache memory.

It takes 4T to write data read from the main memory into the cache memory.

[Problem to be solved by the invention]

The conventional data transfer method to the cache memory described above requires four clocks to write data to the cache memory, and therefore has the disadvantage that the cache memory cannot be accessed during those four clocks.

[Means to solve the problem]

The data transfer method to the cache memory of the present invention includes a cache memory address selector, a shift flip-flop that indicates data transfer timing, a flip-flop that counts the number of data transfers, and a CPU at the time of data transfer.
It has a flip-flop that stores an address, a flip-flop that stores main memory read data, and a circuit that generates a set condition for the flip-flop.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which the amount of data transferred at one time is 4 bytes, and the capacity of one block of cache memory is 1.
FIG. 2 is a block diagram around a 6-byte 1-way p-cache memory.

l is 4 indicated by the youngest CPU address in one block
Cache memory that stores byte data, 2 is cache memory that stores 4 bytes of data indicated by the second youngest CPU address in one block, and 3 is 4 indicated by the third youngest CPU address in one block. 4 is a cache memory that stores 4 bytes of data indicated by the largest CPU address in one block; 5 is a flip-flop that stores main memory read data stored in cache memory 1; 6 is a flip-flop that stores the main memory read data stored in the cache memory 2; 7 is a flip-flop that stores the main memory read data stored in the cache memory 3; 8 is a flip-flop that stores the main memory read data stored in the cache memory 4; Flip-flop for storing memory read data,
9 is a system data bus, 10 is main memory read data,
11 is a selector for switching write data to cache memory 1, 12 is a selector for switching write data to cache memory 2, 13 is a selector for switching write data to cache memory 3, and 14 is a selector for switching write data to cache memory 4. Selector 15 is a selector 1 for read data from cache memories 1 to 4.
6 is a selector for read data to the central processing unit, 17 is write data to cache memory 1, 18 is write data to cache memory 2, 19 is write data to cache memory 3, and 20 is write data to cache memory 4. data, 21 is a set enable signal for flip-flops 5 to 8, 22 is cache memory write data,
23 is the cache memory address, 24.25 is the CPU
A flip-flop that stores an address, 26 a selector that switches the cache memory address, 27 a shift flip-flop that indicates the read data transfer timing from the main memory, 28 a circuit that generates a select signal for the selector 26, and 29 a set enable signal 21 is a flip-flop that stores 30 is a data transfer timing signal from the main memory, 31 is the lower 2 bits of the CPU address
t, 32 is a select signal of the selector 26, 33 is a select signal of the selector 15, 34 is a select signal of the selector 16, and 35 is a CPU.

Next, the present invention will be explained in detail.

When a cache miss occurs in a read request to the main memory, the main memory read data 10 outputted to the system data bus 9 for 4T is distributed and stored among the flip-flops 5, 6, 7, and 8.

Which flip-flop to store data in is determined by the value of the flip-flop's set enable signal 2102 bits.

For example, when the set enable signal 21 is 00", the flip-flop 5 is set. When the set enable signal 21 is "01", the flip-flop 6 is set.
, the main memory read data 10 is stored in the flip-flop 7 when it is "10", and in the flip-flop 8 when it is "11".

The set enable signal 21 is generated as follows.

A signal 30 indicating the timing at which read data from the main memory is output to the system data bus 9 is added to the lower two bits 31 of the flip-flop bus 25 that stores the CPU address at the time of a cache miss. 29.

For example, the lower 2 bits 31 of the flip-flop 25 are “1”
0”, the main memory read data timing signal 30 is “0”
At this time, the flip-flop 29 stores "10", but
In the cycle in which the first main memory read data is output to the system data bus 9, the main memory read data timing signal 30 becomes "1", and in the next cycle, the first main memory read data lO is stored in the flip-flop 7. , and the flip-flop 29 indicates "11".

Therefore, the second main memory read data is transferred to the flip-flop 8, and similarly, the third main memory read data lO is transferred to the flip-flop 5 since the flip-flop 29 indicates "oo". Data 10 is stored in flip-flop 6 since flip-flop 29 indicates "01".

In the cycle in which the fourth main memory read data 10 is stored in any of the flip-flops 5, 6, and 7.8 as described above, the selectors 11, 12, and 13.14 are stored in the flip-flops 5, 6, and 7.8. The output data 17, 18, 19, 20 are stored in the cache memory 1, 2, 3, 4 indicated by the cache memory address 23 of the flip-flop 25 selected by the selector 26.
is stored at the address.

〔Effect of the invention〕

As explained above, the present invention reduces access inhibition time due to data transfer to the cache memory by writing the data read from the main memory to the cache memory in one clock when a read request to the main memory causes a cache miss. It has the effect of reducing

In addition, by placing cache memories in parallel, cache daygrade can be operated even in a one-way system, making it possible to adjust the performance of the central processing unit and prevent failure of part of the RAM used as cache memory. This has the effect that it is not necessary to completely disconnect the cache memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1-4... Cache memory, 5-8...
...Flip-flop, 9...System data bus, 10...Main memory read data, 11-1
6...Selector, 24.25...Furi, Puflo, Pu, 26...Selector, 27...
...Shift flip-flop, 28...Select signal generation circuit, 29...Flip-flop, 35...CPU.

Claims (1)

[Claims] In a main memory read data transfer method after a cache miss/hit to the cache memory in an electronic computer having a cache memory, an input address selector to the cache memory, a shift flip-flop indicating data transfer timing, and a data transfer number are provided. A flip-flop that counts , a flip-flop that stores the CPU address, a flip-flop that stores the CPU address during data transfer, a flip-flop that stores main memory read data, and a flip-flop that stores the main memory read data. A data transfer method to a cache memory having a circuit that generates a set condition.