JPH0343785B2 - - Google Patents

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Publication number
JPH0343785B2
JPH0343785B2 JP58044419A JP4441983A JPH0343785B2 JP H0343785 B2 JPH0343785 B2 JP H0343785B2 JP 58044419 A JP58044419 A JP 58044419A JP 4441983 A JP4441983 A JP 4441983A JP H0343785 B2 JPH0343785 B2 JP H0343785B2
Authority
JP
Japan
Prior art keywords
film
insulating film
bonding pad
semiconductor device
phosphorus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58044419A
Other languages
Japanese (ja)
Other versions
JPS59172258A (en
Inventor
Shigeo Ishii
Kazuhiro Tsurumaru
Shunichiro Shigematsu
Izumi Tezuka
Eiji Minamimura
Isao Sakamoto
Kazuo Shimizu
Shizuo Kondo
Keisuke Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Microcomputer System Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Microcomputer System Ltd, Hitachi Ltd filed Critical Hitachi Microcomputer System Ltd
Priority to JP58044419A priority Critical patent/JPS59172258A/en
Publication of JPS59172258A publication Critical patent/JPS59172258A/en
Publication of JPH0343785B2 publication Critical patent/JPH0343785B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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    • H01L2224/45144—Gold (Au) as principal constituent
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To remove a clearance and the crack of an insulating film, and to improve a wetproof level by coating the surface and side surface of a section surrounding a bonding pad section of the insulating film with the laminated films of silicon dioxide group glass containing phosphorus or silicon nitride and a polyimide group resin. CONSTITUTION:A silicon oxide film 4 used for diffusion masks for base-emitter, etc. is formed on the surface of an element 3, and the surface section of the film 4 is coated with a phosphorus glass film 4a. An Al wiring on the SiO2 film 4 is etched according to predetermined patterns, and a bonding pad 5 is formed to one part of the Al wiring. A silicon oxide group glass film 6 containing phosphorus is shaped, and a film consisting of a polyimide group resin 9 is formed on the film 6 as a final protective film. The phosphorus glass film 4a and the PSG film 6 constrain Na<+> ions etc. contained in the SiO2 film 4 by the action of phosphorus, and prevent a change into instability of the characteristics of the semiconductor element 3.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は高信頼性を有する樹脂モールド型の半
導体装置に関し、特に半田デイツプ実装用の小型
（又は薄型）パツケージ半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a highly reliable resin molded semiconductor device, and particularly to a small (or thin) package semiconductor device for solder dip mounting.

〔背景技術〕[Background technology]

半導体素子をエポキシ樹脂等でモールド封止
（パツケージ）した樹脂モールド型半導体装置は
封止構造が簡単であると共に低コストに製作でき
るという利点を有する。反面、封止体としてセラ
ミツクを用いたセラミツク型パツケージに比較し
て耐湿性が劣るという不利がある。すなわち、樹
脂には水分を透過させ得る性質があるためパツケ
ージ外部の水分が樹脂体を通してパツケージ内部
まで浸入し、これが半導体素子の表面に形成した
アルミニウムからなるボンデイングパツドに付着
してこのパツドを腐食し、電気的な接続を不良又
は不能にして半導体装置の寿命を短縮し、かつ信
頼性を低下させているのである。 A resin-molded semiconductor device in which a semiconductor element is molded and sealed (packaged) with an epoxy resin or the like has the advantage of having a simple sealing structure and being manufactured at low cost. On the other hand, it has the disadvantage of being inferior in moisture resistance compared to a ceramic type package that uses ceramic as the sealing body. In other words, since resin has the property of allowing moisture to pass through, moisture from outside the package penetrates into the package through the resin body, and this adheres to the bonding pad made of aluminum formed on the surface of the semiconductor element and corrodes this pad. However, the electrical connection becomes defective or impossible, shortening the life of the semiconductor device and reducing its reliability.

このため本願発明者等によつて、この種の樹脂
モールド型パツケージにおいて、樹脂体内部に浸
入した水分が半導体素子表面に付着しないよう
に、半導体素子の表面にパツシベーシヨン膜とし
て、ナイトライド（Si3N4）やPSG（リンシリケ
ートガラス）のごとき無機物質膜を形成すること
が考えられた。例えば第１図はその一例であり、
金属タブ１上に銀ペースト２等により接続された
Si（シリコン）を主体とする半導体素子（ペレツ
ト）３の表面の酸化膜４の上にAl（アルミニウ
ム）からなるボンデイングパツド５を有する半導
体装置において、Au（金）ワイヤ８のボンデイン
グされるボンデイングパツド５の一部を露出し、
その周辺及び酸化膜４を覆うようにナイトライド
やPSGによるパツシベーシヨン膜６を形成した
上でエポキシ樹脂７等でモールドするものであ
る。このようなパツシベーシヨン膜を設けること
により樹脂体を通して侵入してきた水分はは上記
ナイトライド膜等により内部への浸入が防止され
半導体素子３表面へ水分が直接に付着するのを相
当程度防止することができるのである。 For this reason, the inventors of the present invention applied nitride (Si 3 Formation of an inorganic material film such as N 4 ) or PSG (phosphosilicate glass) was considered. For example, Figure 1 is an example of this.
Connected on metal tab 1 with silver paste 2 etc.
In a semiconductor device having a bonding pad 5 made of Al (aluminum) on an oxide film 4 on the surface of a semiconductor element (pellet) 3 mainly made of Si (silicon), a bonding process in which an Au (gold) wire 8 is bonded. Exposing a part of pad 5,
A passivation film 6 made of nitride or PSG is formed to cover the periphery and the oxide film 4, and then molded with an epoxy resin 7 or the like. By providing such a passivation film, moisture that has entered through the resin body is prevented from entering the interior by the nitride film, etc., and direct adhesion of moisture to the surface of the semiconductor element 3 can be prevented to a considerable extent. It can be done.

ところが、このようにして半導体装置を構成し
ても、未だ充分満足のゆく耐湿性が得られなかつ
た。特に小型で薄型のパツケージ製品であつて半
田デイツプ（浸漬）により配線基板へ実装するも
のの場合、半田デイツプ後の耐湿度が大きく低下
することが耐湿性試験の結果から明らかとなつ
た。このような耐湿性低下の原因として、半田デ
イツプ後の耐湿性試験でタブ吊りリードから浸入
した水が第１図に矢印Ｈで示すようにSiペレツト
側面より上昇してペレツト上面周辺部表面に集中
し、又、半田デイツプ時の熱応力で熱的に弱い小
型パツケージ製品ではペレツト樹脂体との間に隙
間が生じ、又、パツシベーシヨン膜自体にクラツ
ク等が発生してそこから水が内部に浸入し、リン
ガラスやAlが反応して耐湿性レベルを低下させ
ることがわかつた。 However, even with the semiconductor device configured in this manner, it has not yet been possible to obtain sufficiently satisfactory moisture resistance. In particular, in the case of small and thin packaged products that are mounted on wiring boards by solder dipping (immersion), it has become clear from the results of moisture resistance tests that the moisture resistance after solder dipping is significantly reduced. The reason for this decrease in moisture resistance is that water that entered from the tab suspension lead during the moisture resistance test after solder dipping rises from the side of the Si pellet as shown by arrow H in Figure 1 and concentrates on the peripheral surface of the upper surface of the pellet. Furthermore, in small package products that are thermally weak due to thermal stress during solder dipping, gaps may occur between the package and the pellet resin body, and cracks may occur in the package film itself, allowing water to enter the product. It was found that phosphorus glass and Al react with each other and reduce the moisture resistance level.

〔発明の目的〕[Purpose of the invention]

本発明の目的は半田デイツプ時の熱応力を緩和
し、ペレツトと樹脂体との隙間及びペレツトパツ
シベーシヨンのクラツクを低減して、耐湿性レベ
ルを向上させ、半田デイツプ基板実装方法を可能
とした樹脂パツケージ半導体製品の提供にある。 The purpose of the present invention is to alleviate the thermal stress during solder dip, reduce the gap between the pellet and the resin body and cracks in the pellet packaging, improve the moisture resistance level, and enable the solder dip board mounting method. Our goal is to provide resin packaged semiconductor products.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なも
のの概要を簡単に説明すれば、半導体基板の一主
面にAl等よりなる配線が形成され、この配線の
一部がボンデイングパツド部として露出され他部
が絶縁膜で覆われ、上記ボンデイングパツド部と
外部リードとがワイヤーにより接続された状態で
全体が樹脂モールド体で封止されてなる半導体装
置において、少なくとも上記絶縁膜のボンデイン
グパツド部を包囲する部分の表面及び側面をリン
を含む二酸化シリコン系ガラスもしくは窒化シリ
コンと、ポリイミド系樹脂との積層被覆で覆い、
隙間や絶縁膜のクラツクをなくし、耐湿性レベル
を向上するものである。 To briefly explain the outline of a representative invention among the inventions disclosed in this application, a wiring made of Al or the like is formed on one main surface of a semiconductor substrate, and a part of this wiring is exposed as a bonding pad portion. In a semiconductor device in which the bonding pad portion is covered with an insulating film, the bonding pad portion and the external lead are connected by a wire, and the entire body is sealed with a resin molded body, at least the bonding pad portion of the insulating film is covered with an insulating film. Covering the surface and side surfaces of the surrounding part with a laminated coating of silicon dioxide glass or silicon nitride containing phosphorus and polyimide resin,
This eliminates gaps and cracks in the insulating film and improves the level of moisture resistance.

〔実施例〕〔Example〕

第２図は本発明による小型樹脂封止形半導体装
置の一実施例を断面図で示すものである。 FIG. 2 is a sectional view showing an embodiment of a small resin-sealed semiconductor device according to the present invention.

同図において、３はSiを主体とする集積回路が
構成された半導体素子で銅、コバール等の金属に
て形成したリードフレームのタブ１上にAu−Si
（金・シリコン）共晶合金又はAg（銀）ペースト
２を用いてダイボンデイングされている。この半
導体素子の表面に形成された複数のボンデイング
パツド５と前記リードフレームのリード９とが
Auワイヤ８でボンデイングされ、電気的接続さ
れた上で封止用エポキシ樹脂７によりこれらはモ
ールド封止されている。 In the same figure, reference numeral 3 denotes a semiconductor element composed of an integrated circuit mainly composed of Si.
Die bonding is performed using a (gold/silicon) eutectic alloy or Ag (silver) paste 2. A plurality of bonding pads 5 formed on the surface of this semiconductor element and leads 9 of the lead frame are connected to each other.
After bonding and electrical connection with Au wires 8, these are mold-sealed with a sealing epoxy resin 7.

第３図は前記半導体素子３の表面部を詳細に示
すための要部拡大断面図である。同図において、
素子３の表面上にはベース・エミツタ等の拡散マ
スクに使用した酸化シリコン（SiO2）膜４が形
成され、その表面部分はエミツタ拡散時の酸化リ
ンを含むガラス、いわゆるリンガラス膜４ａで覆
われている。このSiO4膜４の上にAi配線を所定
のパターンにエツチングしてその一部にボンデイ
ングパツド５が形成されている。このように形成
した素子上面にはさらにリンを含む酸化シリコン
系ガラス（PSG）膜６が形成され、この上に最
終用保護膜（パツシベーシヨン）としてポリイミ
ド系樹脂（例えばポリイミドイソインドロキナゾ
リンジオン）の被膜が形成されている。上記リン
ガラス膜４ａ及びPSG膜６はSiO2膜４中に含ま
れるNa+イオン等をリンの作用で拘束し、SiO2
膜内におけるNa+イオン等の遊動に伴つて生ずる
半導体素子３の特性の不安定化を防止する。又、
上記ポリイミド系樹脂９はスピン塗布等の手段に
よつて形成することにより半導体素子表面の隙間
を埋めて表面を平坦化するとともにその外側を覆
つて封止するエポキシ系樹脂封止体７との間の接
着性を良好ならしめ、外部より水分等の浸入を防
止する。これらPSG膜６とポリイミド系樹脂膜
９は素子の上面部分に存在する酸化シリコン膜４
の表面及び側面を完全に覆うように形成されてい
る。特に、第３図に見られるように、PSG膜６
の終端部側面（半導体基板外周に近接した部分）
はその上に形成されたポリイミド系樹脂膜９によ
つて覆われている。 FIG. 3 is an enlarged sectional view of a main part showing the surface part of the semiconductor element 3 in detail. In the same figure,
A silicon oxide (SiO 2 ) film 4 used as a diffusion mask for the base and emitter is formed on the surface of the element 3, and the surface portion is covered with a so-called phosphorus glass film 4a, which is glass containing phosphorus oxide during emitter diffusion. It is being said. On this SiO 4 film 4, an Ai wiring is etched in a predetermined pattern, and a bonding pad 5 is formed in a part thereof. A silicon oxide glass (PSG) film 6 containing phosphorus is further formed on the top surface of the element formed in this way, and a polyimide resin (for example, polyimide isoindoquinazolinedione) is coated on top of this as a final protective film (passivation). A film is formed. The phosphorus glass film 4a and the PSG film 6 restrain Na + ions, etc. contained in the SiO 2 film 4 by the action of phosphorus, and the SiO 2
This prevents the characteristics of the semiconductor element 3 from becoming unstable due to the movement of Na + ions, etc. within the film. or,
The polyimide resin 9 is formed by spin coating or other means to fill gaps on the surface of the semiconductor element and flatten the surface, and also to cover and seal the outside of the semiconductor element between the polyimide resin 9 and the epoxy resin encapsulant 7. This ensures good adhesion and prevents moisture from entering from the outside. These PSG film 6 and polyimide resin film 9 are silicon oxide film 4 present on the upper surface of the element.
It is formed to completely cover the surface and sides of the In particular, as seen in Figure 3, the PSG film 6
Side surface of the terminal end (portion close to the outer periphery of the semiconductor substrate)
is covered with a polyimide resin film 9 formed thereon.

〔効果〕〔effect〕

本発明による半導体装置は以上の構成を有し、
半導体素子の表面及び側面をPSG膜で覆つて素
子の特性安定化に寄与し、その上にポリイミド系
樹脂膜を介して樹脂モールドしてあるため、この
半導体装置を配線基板に対して半田デイツプによ
り実装する際に生じる熱ストレスを緩和でき、
PSG膜の表面にそつて隙間を生じたり、PSG膜
等の絶縁膜自体におけるクラツクの発生を緩和で
きる。したがつて樹脂封止体内部よりの水分が半
導体素子表面及び側面へ第３図の矢印Ｈに示すよ
うに入つてきた場合もPSGとポリイミド系樹脂
とによつて有効に阻止することができる。 A semiconductor device according to the present invention has the above configuration,
The surface and side surfaces of the semiconductor element are covered with a PSG film, which contributes to stabilizing the characteristics of the element, and the semiconductor element is resin-molded with a polyimide resin film interposed thereon. Thermal stress that occurs during mounting can be alleviated,
It is possible to alleviate the occurrence of gaps along the surface of the PSG film and cracks in the insulating film itself such as the PSG film. Therefore, even if moisture from inside the resin sealing body enters the surface and side surfaces of the semiconductor element as shown by arrow H in FIG. 3, it can be effectively prevented by the PSG and polyimide resin.

上記した本発明の実施例では半導体素子の表面
を直接に覆う下地パツシベーシヨン膜として
PSGを使用したが、このPSGに代えて他の無機
性絶縁膜、たとえばプラズマ放電を利用して気相
より生成するシリコン窒化物（例えばSi3N4、ナ
イトライドと称する）を使用することもできる。
ナイトライドは高いち密性をもち機械的強度、化
学安定性を有し、これとポリイミド系樹脂と組合
せることによつてPSGを使用した場合と同様又
はそれ以上の効果を有する。 In the above-described embodiments of the present invention, as a base passivation film that directly covers the surface of a semiconductor element,
Although PSG was used, other inorganic insulating films such as silicon nitride (e.g. Si 3 N 4 , called nitride), which is generated from the gas phase using plasma discharge, may be used in place of PSG. can.
Nitride has high densities, mechanical strength, and chemical stability, and by combining it with polyimide resin, it has the same or better effect than when PSG is used.

前記第２図及び第３図に示した半導体装置を製
造する際のプロセスの例を第４図乃至第８図を用
いて説明する。 An example of a process for manufacturing the semiconductor device shown in FIGS. 2 and 3 will be described with reference to FIGS. 4 to 8.

第４図はｐ型Si基板１１の上に一部でn+型埋込
層１２を介してｎ型エピタキシヤルSi層１３を有
する半導体素子を縦断面図で示すものであり、本
例ではバイポーラ型のトランジスタを構成してい
る。ウエハ状態で半導体素子の表面に形成した酸
化膜（SiO2）１４の一部を窓開してそれぞれ別
個の拡散工程により、ｐ型アイソレーシヨン部１
５、p+型ベース１６、n+型コレクタ１７、n+型
エミツタ１８を順次形成した後、エミツタ拡散の
際のデボジツト・リンガラス膜１９で覆つた状態
でコンタクトホトエツチを行い、その上にAl（ア
ルミニウム）を蒸着し、パターニングエツチする
ことにより配線２０及びその端子としてボンデイ
ングパツド２１を形成する。 FIG. 4 shows a vertical cross-sectional view of a semiconductor device having an n-type epitaxial Si layer 13 on a p-type Si substrate 11 with a part of the n + type buried layer 12 interposed therebetween. It constitutes a type of transistor. A part of the oxide film (SiO 2 ) 14 formed on the surface of the semiconductor element in a wafer state is opened and a p-type isolation region 1 is formed by a separate diffusion process.
5. After sequentially forming the p + type base 16, the n + type collector 17, and the n + type emitter 18, contact photoetching is performed while covering with the deposit phosphorus glass film 19 used for emitter diffusion. By vapor depositing Al (aluminum) and patterning and etching, wiring 20 and bonding pads 21 as its terminals are formed.

このあと第５図（以下ボンデイングパツド部分
近傍を含む部分図であらわす）に示すように、全
面にCVD（気相化学堆積法）によるリン酸化物を
含むSiO2系ガラス、いわゆるPSG膜２２をデポ
ジシヨンする。次いでPSGのボンデイングパツ
ド部分２１をホトエツチ技術により窓開する。 After this, as shown in FIG. 5 (hereinafter shown as a partial view including the vicinity of the bonding pad), a so-called PSG film 22, which is SiO 2 -based glass containing phosphorous oxide, is deposited on the entire surface by CVD (vapor phase chemical deposition). Deposit. Next, the bonding pad portion 21 of the PSG is opened using a photoetch technique.

このあとポリイミド系樹脂をスピン塗布法によ
り基板全表面を覆うように十分な厚さに形成し、
ベーク処理して第６図に示すようにポリイミド樹
脂膜２３を形成し、ボンデイングパツド部分のみ
を窓開する。このボンデイングパツド部分の窓開
は、前記PSG膜２２とその上のポリイミド系樹
脂膜２３とを全面に重ね合せた状態で共通のホト
エツチマスクにより同時に行うようにしてもよ
い。 After this, polyimide resin is formed to a sufficient thickness to cover the entire surface of the substrate by spin coating.
A baking process is performed to form a polyimide resin film 23 as shown in FIG. 6, and only the bonding pad portion is opened. The bonding pad portion may be opened simultaneously using a common photo-etch mask while the PSG film 22 and the polyimide resin film 23 thereon are superimposed on the entire surface.

然るのち、ウエハをスクライブ（又はダイシン
グ）して半導体素子を含むペレツトに分割し、第
７図（全体組立図）で示すようにペレツト基板１
１をリードフレームのタブ２４上に銀ペースト等
を介してペレツトボンデイングした後、ボンデイ
ングパツド部２１とリードフレームの外部リード
群２５との間をAuワイヤ２６によるワイヤボン
デイングを行う。第８図は第７図の点線の円Ａで
囲む部分の拡大断面図である。 Thereafter, the wafer is scribed (or diced) and divided into pellets containing semiconductor elements, and a pellet substrate 1 is formed as shown in FIG. 7 (overall assembly diagram).
1 is pellet-bonded onto the tab 24 of the lead frame using silver paste or the like, and then wire bonding is performed using an Au wire 26 between the bonding pad portion 21 and the external lead group 25 of the lead frame. FIG. 8 is an enlarged sectional view of a portion surrounded by a dotted circle A in FIG.

さいごに公知のトランスフアモールド法を用い
て上記構体をエポキシ樹脂等によりモールド封止
することにより前記第２図で示した半導体装置を
得ることができる。 Finally, the above-mentioned structure is mold-sealed with epoxy resin or the like using a known transfer molding method to obtain the semiconductor device shown in FIG. 2.

〔他の実施例及びその結果〕[Other Examples and Results]

さらに本発明の他の実施例を第９図及び第１０
図を参照し説明する。 Furthermore, other embodiments of the present invention are shown in FIGS. 9 and 10.
This will be explained with reference to the drawings.

第９図はボンデイングパツドの金属層を２層構
造とした場合の例を示す。なお、同図で前記第８
図と共通する構成部分はそれと同一指示記号を使
用している。 FIG. 9 shows an example in which the metal layer of the bonding pad has a two-layer structure. In addition, in the same figure, the eighth
Components common to the figures have the same reference symbols.

すなわち、最終パツシベーシヨンのためのポリ
イミド系樹脂２３を形成しボンデイングパツド部
を窓開してAl層を露出した後、その上に再度Al
等の金属を蒸着（又はスパツタ）し、パターニン
グエツチしてボンデイングパツド部に２層目の金
属膜２７が周辺のポリイミド系樹脂膜の上方に突
出するように形成する。この状態でエポキシ樹脂
２９モールドすることにより、ボンデイングパツ
ド部が肉厚に形成された分だけ腐食に対する寿命
がさらに増大し、かつ配線部分への水の浸入も阻
止され、半導体製品の信頼性の向上を図り得る。 That is, after forming the polyimide resin 23 for the final bonding and opening the bonding pad part to expose the Al layer, the Al layer is again deposited on top of it.
A second metal film 27 is formed on the bonding pad portion by vapor deposition (or sputtering) and patterning so as to protrude above the surrounding polyimide resin film. By molding the bonding pad with epoxy resin 29 in this state, the lifespan against corrosion is further increased by making the bonding pad part thicker, and water infiltration into the wiring part is also prevented, improving the reliability of semiconductor products. Improvements can be made.

第１０図はボンデイングパツドに対してワイヤ
ボンデイング後にポリ部分のみに少量のポリイミ
ド系樹脂等をポツテイング（滴下）してAl表面
部を含み、その周辺のポリイミド系樹脂膜２３に
重なるように樹脂コーテイング２８を形成し、こ
の上でエポキシ樹脂等をモールドして封止した場
合の例である。同図において前記第８図と共通の
構成部分はそれと同一の指示記号を使用してい
る。 Figure 10 shows that after wire bonding to the bonding pad, a small amount of polyimide resin, etc. is potted (dropped) only on the poly portion to coat the bonding pad so as to include the Al surface portion and overlap the polyimide resin film 23 around it. 28 is formed, and epoxy resin or the like is molded thereon to seal it. In this figure, the same designating symbols are used for components common to those in FIG. 8.

このような構成にすればポツテイングした樹脂
コーテイング２８によつてボンデイングパツド部
が完全に覆われるためにパツド表面及びその周辺
への水分の浸入が一層有効に阻止でき、半導体装
置の寿命、耐湿信頼性を向上できる。 With this configuration, the bonding pad portion is completely covered by the potted resin coating 28, which makes it possible to more effectively prevent moisture from entering the pad surface and its surroundings, thereby extending the lifespan of the semiconductor device and its moisture resistance reliability. You can improve your sexuality.

〔利用分野〕[Application field]

以上の説明では主として本発明者によつてなさ
れた発明をその背景となつた利用分野であるバイ
ポーラ形半導体装置について説明したが、それに
限定されるものではなく、たとえばMOS形素子
を含む半導体装置についても本発明を同様に適用
できる。 In the above explanation, the invention made by the present inventor has mainly been explained with respect to bipolar type semiconductor devices, which is the field of application that forms the background of the invention, but is not limited thereto, and includes, for example, semiconductor devices including MOS type elements. The present invention can also be applied in the same way.

本発明は少なくともボンデイングパツド部を有
し、ポリイミド系樹脂を最終保護膜に使用する樹
脂封止形半導体装置に適用することができるもの
であり、特に半田デイツプにより外部リードを配
線基板等に実装する小型・薄型パツケージの半導
体装置に適用して有効である。例えば、その半導
体装置との外観構造としては、第１１図に示すよ
うなミニスクウエアパツケージ（Mini−square
Package）構造あるいは第１２図に示すようなス
モールアウトラインパツケージ（Small−
Outline Package）構造が最も好ましい例であ
る。これらの半導体装置を半田ジヤプ付け方式で
電子部品ボードに実現する場合を第１１図に示す
半導体装置を例に以下に簡単に述べておく。 The present invention can be applied to a resin-sealed semiconductor device that has at least a bonding pad portion and uses polyimide resin as a final protective film, and is particularly applicable to a resin-sealed semiconductor device that uses a solder dip to mount external leads to a wiring board, etc. It is effective when applied to semiconductor devices in small and thin packages. For example, the external structure of the semiconductor device is a mini-square package as shown in FIG.
Package structure or small outline package structure as shown in Figure 12.
Outline Package) structure is the most preferred example. A case in which these semiconductor devices are implemented on an electronic component board using the solder jump method will be briefly described below using the semiconductor device shown in FIG. 11 as an example.

第１３図に示すように半導体装置１００を接着
剤１０１によつて電子部品ボード１０２に仮固定
しておき、そして半田１０３が流動している半田
浴槽１０４内に通す。この結果、所望の電子装置
が得られる。なお、１０５は電子部品ボードに印
刷または選択エツチングによつて形成された配線
層である。 As shown in FIG. 13, a semiconductor device 100 is temporarily fixed to an electronic component board 102 with an adhesive 101, and then passed through a solder bath 104 in which solder 103 is flowing. As a result, a desired electronic device is obtained. Note that 105 is a wiring layer formed on the electronic component board by printing or selective etching.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明者により提案された本発明の前
提となる半導体装置の素子表面部の拡大断面図で
ある。第２図は本発明の一実施例による半導体装
置の全体断面図である。第３図は第２図に示した
半導体装置の素子表面部の拡大断面図である。第
４図乃至第８図は第２図に示した半導体装置の製
造プロセスの要部を示す工程断面図であつて、こ
のうち第４図は配線の完成した一つの半導体素子
の構造を示す断面図、第５図、第６図は工程の一
部における拡大断面図、第７図はボンデイングの
形態を示す正面図、第８図は第７図における一部
拡大断面図である。第９図及び第１０図は夫々異
なる本発明の他の実施例の拡大断面図である。第
１１図及び第１２図は本発明が適用される半導体
装置の外観構造をそれぞれ示す斜視図である。第
１３図は半導体装置の実装方法を示す断面図であ
る。 １……金属タブ、２……銀ペースト、３……半
導体素子（ペレツト）、４……酸化Si膜、５……
ボンデイングパツド、６……パツシベーシヨン膜
（PSG膜）、７……エポキシ樹脂封止体、８……
ワイヤ、９……ポリイミド系樹脂膜、１１……ｐ
型Si基板、１２……n+型埋込層、１３……ｎ型エ
ピタキシヤルSi層、１４……酸化膜、１５……ｐ
型アイソレーシヨン部、１６……p+型ベース、
１７……n+型コレクタ、１８……n+型エミツタ、
１９……リンガラス膜、２０……配線、２１……
ボンデイングパツド、２２……PSG膜、２３…
…ポリイミド系樹脂膜、２４……タブ、２５……
リード、２６……金ワイヤ、２７……金属膜、２
８……樹脂コーテイング、半導体装置……１０
０、接着剤……１０１、電子部品ボード……１０
２、半田……１０３、半田槽……１０４、配線層
……１０５。 FIG. 1 is an enlarged sectional view of an element surface portion of a semiconductor device, which is the premise of the present invention proposed by the present inventor. FIG. 2 is an overall sectional view of a semiconductor device according to an embodiment of the present invention. 3 is an enlarged cross-sectional view of the element surface portion of the semiconductor device shown in FIG. 2. FIG. 4 to 8 are process cross-sectional views showing the main parts of the manufacturing process of the semiconductor device shown in FIG. 2, of which FIG. 4 is a cross-sectional view showing the structure of one semiconductor element with completed wiring. 5 and 6 are enlarged sectional views of a part of the process, FIG. 7 is a front view showing the form of bonding, and FIG. 8 is a partially enlarged sectional view of FIG. 7. FIGS. 9 and 10 are enlarged sectional views of other different embodiments of the present invention. FIGS. 11 and 12 are perspective views respectively showing the external structure of a semiconductor device to which the present invention is applied. FIG. 13 is a cross-sectional view showing a method of mounting a semiconductor device. 1...Metal tab, 2...Silver paste, 3...Semiconductor element (pellet), 4...Si oxide film, 5...
Bonding pad, 6... Passivation film (PSG film), 7... Epoxy resin sealing body, 8...
Wire, 9...polyimide resin film, 11...p
type Si substrate, 12...n + type buried layer, 13...n type epitaxial Si layer, 14...oxide film, 15...p
Mold isolation part, 16...p + type base,
17...n + type collector, 18...n + type emitter,
19...phosphorus glass film, 20... wiring, 21...
Bonding pad, 22...PSG film, 23...
...Polyimide resin film, 24...Tab, 25...
Lead, 26... Gold wire, 27... Metal film, 2
8...Resin coating, semiconductor device...10
0, Adhesive...101, Electronic component board...10
2. Solder...103, Solder tank...104, Wiring layer...105.

Claims (1)

【特許請求の範囲】[Claims] １ 半導体基板の一主面上にAlよりなる配線が
形成され、この配線の一部が半導体基板の外周に
近接した位置においてボンデイングパツド部とし
て現れ、他部が絶縁膜によつて覆われてなり、端
部がその半導体基板外周から所定間隔を保つて位
置する外部リードを有し、上記ボンデイングパツ
ド部と外部リードとがワイヤにより電気的接続さ
れ、その外部リードの一部を露出するようにして
半導体基板全体が樹脂封止体により封止され、該
外部リードの露出部分を半田付けするために装置
全体が熱応力が加わるような環境に曝される半導
体装置であつて、上記絶縁膜はリンを含む二酸化
シリコン系ガラスもしくは窒化シリコンからなる
無機性絶縁膜と、この無機性絶縁膜に重ねて形成
されたポリイミド系樹脂からなる有機性絶縁膜と
によつて構成され、半導体基板の外周に近接して
終端するその無機性絶縁膜の側面はその上に形成
された有機性絶縁膜によつて覆われてなることを
特徴とする半導体装置。1 A wiring made of Al is formed on one main surface of a semiconductor substrate, a part of this wiring appears as a bonding pad near the outer periphery of the semiconductor substrate, and the other part is covered with an insulating film. The bonding pad portion and the external lead are electrically connected to each other by a wire, and a portion of the external lead is exposed. The semiconductor device is a semiconductor device in which the entire semiconductor substrate is sealed with a resin sealant, and the entire device is exposed to an environment where thermal stress is applied in order to solder the exposed portions of the external leads, and the insulating film is consists of an inorganic insulating film made of silicon dioxide-based glass or silicon nitride containing phosphorus, and an organic insulating film made of polyimide-based resin formed on top of this inorganic insulating film. A semiconductor device characterized in that a side surface of the inorganic insulating film that terminates in proximity to the inorganic insulating film is covered with an organic insulating film formed thereon.
JP58044419A 1983-03-18 1983-03-18 Semiconductor device Granted JPS59172258A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58044419A JPS59172258A (en) 1983-03-18 1983-03-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58044419A JPS59172258A (en) 1983-03-18 1983-03-18 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59172258A JPS59172258A (en) 1984-09-28
JPH0343785B2 true JPH0343785B2 (en) 1991-07-03

Family

ID=12690968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58044419A Granted JPS59172258A (en) 1983-03-18 1983-03-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS59172258A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4832996A (en) * 1988-02-24 1989-05-23 Motorola, Inc. Semiconductor die for plastic encapsulation having an adhesion promoter

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150830A (en) * 1980-04-25 1981-11-21 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150830A (en) * 1980-04-25 1981-11-21 Hitachi Ltd Semiconductor device

Also Published As

Publication number Publication date
JPS59172258A (en) 1984-09-28

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