JPH034324A - Shift processor - Google Patents

Abstract

PURPOSE:To execute a shift processing to contain a digit shift for one word with a small number of steps at a high speed by inputting the output data of a register directly to a register file at the time of executing the digit shift for one word. CONSTITUTION:At the time of executing a left shift processing, first, a register 13 and a counter 12 are both cleared, and whether or not a shift digit number stored in a register 16 is at M-digit or above is discriminated. Here, when the number is below M-digit, the left shift processing for a shift digit number indicated by the register 16 is executed by a shifter 15, and the processing is completed. When the shift digit number is at M-digit or above, by inputting the data of the register 13 to a register file 11, the shift processing for M-digit is executed. Further, the portion of M-digit is subtracted from the register 16, and the remaining shift digit number is checked. When the remaining shift digit number is at M-digit or above, the data of the register 13 are inputted to the file 11 again, the shift processing for M-digit is executed, and the processing is repeated until the remaining shift digit number goes below M-digit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a shift processing device that processes data in a register file of an arithmetic processing unit by an arbitrary number of digits or shifts it to the right.

(Prior Art) The configuration of a conventional shift processing device of this type is shown in FIG. 3, and the shift processing flow thereof is shown in FIG.

In Figure 3, the old register file (RU) stores the data to be shifted and the data resulting from the shift.
, 02 is a counter (UCT) that specifies the word position of the register file O1. 03 is a register (RS) that temporarily stores data read out from the register file O1 in units of 1 word (M digits), and 04 receives the data read out from the register file O1 and the data read out from register 03; This is a selector that connects and outputs each data in a combination order according to the shift direction (left or right). 05 shifts the output data of selector 04 as the input data (DS) and shifts the digits in units of 1 digit (zero digit shift to M - 1 digit shift), and outputs a 1 word (M digit) width shift by shifting the digit. A 1-word shifter 06 that supplies data (DSO) to the register file 01
is a register (RS N
). A specific example of the shift function of the shifter 05 is shown in FIG. Here, each shift state (zero digit shift to M-1 digit shift) is illustrated using a left shift as an example of M-8 digits.

In FIG. 4, SOI is an initial setting step in which counter 02 and registers 03+ and :rOJ are set.

SO2 is a step in which the data in the register file O1 is shifted from the word on the LSB side to all words, and when the number of shifts indicated by register 06 is less than the number of digits of one word, that is, indicated by register OG. When the number of shifts is within the maximum number of shift digits (M - 1 digit) of shifter 05 (RSN<M), shift processing is performed for the number of shifts indicated by register 06, and the number of shifts indicated by register OB is The number of digits in one word or more (RSN≧M
), the shift process of the maximum number of shift digits (M-1 digits) of shifter 05 is executed. SO3 is a step to prepare for re-shift processing, in which the maximum number of shift digits (M-1 digits) of shifter 05 is subtracted from register 00, and counter 02 and register 03 are initialized to "0". S04 is a step for determining the end of the shift process, and if the remaining shift number in the register OG is one or more digits (if RSN>0), the shift process of step SO2 is performed again, and if it is "0", the process ends.

However, in the conventional shift processing device as described above, when one word (M digits) is to be shifted to the left, the maximum number of digits shifted at one time by the shifter 05 is M-.
Since it is a single digit, first shift processing with [;
After shifting by one digit to the left, it is necessary to shift by one digit to the left in a second shift process, which requires twice as many processing steps as in the shift process of M-1 digits or less, which reduces the processing speed. There was a problem with the surface.

(Problems to be Solved by the Invention) As described above, in a shift processing device with a conventional configuration using a shifter with a 1-word (M digit) configuration, for example, 1
When performing a left or right shift of a word (M digits), M-
This method requires twice as many processing steps as the shift processing of one digit or less, and there is a problem that the processing speed decreases.

The present invention has been made in view of the above-mentioned circumstances.
In a shift processing device using a shifter with a configuration of 1
A digit shift of a word (M digits) can be performed in just one shift process in the same way as a digit shift of less than 1 word (M - 1 digit or less), and the processing steps for a 1 word shift can be halved and the shift processing operation can be performed. The purpose of the present invention is to provide a shift processing device that can speed up the processing.

[Structure of the Invention] (Means and Effects for Solving the Problems) The present invention provides a register that temporarily stores one word of data read from a register file, and a register that temporarily stores data read from the register file and data read from the register. In response to this,
A first selector that connects and outputs each of these data in a combination order according to the shift direction, and a 1-word configuration that shifts the output data of the selector in units of digits and outputs shifted data with the number of digits equivalent to one word. shifter, and a second selector that receives the output data of the same chic and the output data of the register, selects one of them, and inputs it to the register file, and performs a digit shift of one word. When this is done, the output data of the register is directly input into the register file, which allows one word's worth of digit shifts to be executed at high speed in a small number of steps.

That is, the present invention provides a shift processing device using a shifter having a one-word (M digit) configuration, as shown in FIG. The input terminal receives the output data (DSO) of the shifter 15 and the data of the register (R5) 13 that temporarily stores the shift input data, and selects one of the data and inputs it to the register file 11. As shown in the processing flow (from step 83) of FIG. 2, when shifting one word (M digits), the register 1 is
By directly inputting the output of 3 to the register file 11 via the selector 14, a shift of M digits can be realized at high speed with just one shift process, similar to the shift within M-1 digits.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In Figure 1, ll is a register file (RU) that stores the data to be shifted and the data resulting from the shift.
It is. 12 is a counter (UCT) that specifies the word position of the register file O1.

Reference numeral 13 denotes a register (
R5). A selector 14 receives the data read from the register file 11 and the data stored in the register 13, and connects and outputs the data in a combination order according to the shift direction (left or right). 15 uses the output data of the selector 14 as shift input data (DSI) and shifts the digits in units of digits (zero digit shift to M-1 digit shift), and shifts the output data of 1 word (M digits) width by shifting the digit ( This is a one-word shifter that inputs DSO) to the register file 11. te is a register (RSN) that specifies the number of digits to be shifted by the shifter 15.

17 receives the output data (DSO) of the shifter 15 and the data stored in the register (R8) 13, and shifts either one of the data according to the shift digit number of the register 1B (
This is a selector that selects (depending on whether RSN≧M or not) and inputs it to the register file 11.

FIG. 2 is a flowchart showing the processing flow of the above embodiment.

In FIG. 2, St is a step for initial setting and determining the number of shifts, and the counter 12 and register 13 are
0", and it is determined whether the number of shift digits set in the register 1G is greater than or equal to the number of digits constituting one word (M digits). S2 shifts input data to the left or right by the number of shift digits indicated by register IB when the number of shift digits is less than the number of digits (M digits) constituting one word (within M-1 digits). This is a processing step in which the data in the register file 11 is shifted from the LSB side word to all the words. Sa is a step to shift M digits when the number of shift digits set in register 1B is greater than or equal to the number of digits constituting one word (M digits), and the data in register file 11 is shifted from all words on the LSB side. Shift to word.

S4 is a step to prepare for re-shift processing, in which register l (number of digits composing one word CM) is subtracted from i, and counter 12 and register 13 are initialized to "0".

S5 is a step for determining the number of shifts, and register 1
It is determined whether the remaining shift number of G is "M" or more (RSN≧M), and if it is "M" or more, the process of step S3 is performed again. Sa is a step for determining the end of the shift process, and if the remaining shift number in the register 1B is "1" or more (RSN>0), the shift process in step S2 is performed again, and the result is "0" (RSN-0). ), the process ends.

The operation of an embodiment of the present invention will now be described with reference to FIGS. 1 and 2. Here, taking a left shift as an example, it is assumed that zero (0) is input as the shift input data from the LSB side in the case of left shift.

When performing left shift processing, first clear both the register 13 and the counter 12, and determine whether the number of shift digits stored in the register 1B is M digits or more (R3N1M) (step in Fig. 2). S2).

Here, if the number of shift digits is less than M digits, shifter 1
5, the left shift process is performed by the number of shift digits indicated by the register 1B, and the process ends (step S2 in FIG. 2).

Also, when the number of shift digits is M digits or more, register 13
By inputting the data into the register file 11, shift processing for M digits is performed. That is, when the number of shift digits is M or more (RSN≧M), the selector I7 selects the data in the register 3 and inputs it to the register file 11. Furthermore, M digits are subtracted from the register 16 to check the remaining number of shift digits (step S3 in FIG. 2).

Here, when the number of remaining shift digits is M digits or more, the data in the register 13 is inputted to the register file 11 again to perform shift processing for M digits, and this process is repeated until the number of remaining shift digits is less than M digits. This is repeated until (steps S5 and 33 in FIG. 2).

If the remaining number of shift digits is less than M digits, the left shift is performed by the number of shift digits indicated by the register 1G, and the process ends (steps S3 and S2 in FIG. 2).

By such a shift processing operation, shift processing including a digit shift of one word (M digits) or more can be performed at high speed in a small number of steps.

[Effects of the Invention] As detailed above, according to the shift processing device of the present invention,
A register that temporarily stores 1-word data read from the register file, and a register that receives the data read from the register file and the data read from the register, connects these data in a combination order according to the shift direction, and outputs it. a first selector that shifts the output data of the selector in units of digits and outputs shifted data having the number of digits equivalent to one word;
A second selector receives the output data of the shifter and the output data of the register, selects one of the data, and inputs the selected data to the register file. By manually inputting the output data of the register directly to the register file, shift processing including digit shift for one word can be executed at high speed in a small number of steps.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing the processing flow of the same embodiment, FIG. 3 is a block diagram showing the configuration of a conventional shift processing device, and FIG. FIG. 5 is a flowchart showing the processing flow of the conventional device shown in FIG. 5, and FIG. 11...Register file (RU), 12...Counter (UCT), 13...Register (R8), 1
4... Selector (first selector), 15... Shifter, 16... Register (R3N), 17... Selector (second selector).

Claims (1)

[Claims] A register file that stores shift target data and shift result data, means for reading data in units of one word from the register file, a register that temporarily stores data in units of one word read from the register file, and the register file. A first selector receives the data read from the register and the data read from the register, and connects and outputs the data in a combination order according to the shift direction, and the output data of the selector is shifted digit by digit to form one word. A 1-word shifter that outputs shifted data with a number of digits, receives the output data of the shifter and the output data of the above register, selects one of the data, and inputs it to the above register file. A shift processing device comprising: a second selector that selects a second selector;