JPH0342831A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0342831A JPH0342831A JP17850289A JP17850289A JPH0342831A JP H0342831 A JPH0342831 A JP H0342831A JP 17850289 A JP17850289 A JP 17850289A JP 17850289 A JP17850289 A JP 17850289A JP H0342831 A JPH0342831 A JP H0342831A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- oxide film
- silicon oxide
- polycrystalline silicon
- onto
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims abstract description 11
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 7
- 239000011574 phosphorus Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 abstract description 9
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 9
- 239000010410 layer Substances 0.000 abstract description 8
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- 239000011229 interlayer Substances 0.000 abstract description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052786 argon Inorganic materials 0.000 abstract description 3
- -1 argon ions Chemical class 0.000 abstract description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体装置の保護膜の構造に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to the structure of a protective film for a semiconductor device.
〔従来の技術］
従来の半導体装置の保護膜の構造は、シリコン酸化膜、
燐を含んだシリコン酸化膜、プラズマシリコン窒化膜、
あるいは、それ等の積層膜を有する構造であった。特に
、半導体装置の１ｌｉ４湿性向上のため、プラズマシリ
コン窒化膜が用いられていた。[Prior art] The structure of the protective film of a conventional semiconductor device is a silicon oxide film,
Silicon oxide film containing phosphorus, plasma silicon nitride film,
Alternatively, it was a structure having such laminated films. In particular, plasma silicon nitride films have been used to improve the 1li4 humidity of semiconductor devices.
［発明が解決しようとする課題］
しかし、前述の従来技術では、ＩＥＤＭ ８６の”
１ 、０ ａ ｍ ＣｕＯ２ＰＲＯＣ：ＥＳＳ ＦＯ
ＲＨＩＧＨＬＹ ＳＴＡＢＬＥＴＥＲＡ−ＯＨＭ ＰＯ
ＬＹＳＩＬＩＣＯＮ ＬＯＡＤ ＩＭｂ ＳＲＡＭ ”
に記載されているように、より高抵抗を得るために薄い
多結晶シリコンを用いると、プラズマシリコン窒化膜中
の水素が多結晶シリコンに入り、わずかな外部印加電圧
により、抵抗値が大きく変動するという問題点を有する
。[Problem to be solved by the invention] However, in the above-mentioned prior art, the “IEDM 86”
1,0 am CuO2PROC:ESS FO
RHIGHLY STABLETERA-OHM PO
LYSILICON LOAD IMb SRAM”
As described in , when thin polycrystalline silicon is used to obtain higher resistance, hydrogen in the plasma silicon nitride film enters the polycrystalline silicon, causing the resistance value to fluctuate greatly with a small externally applied voltage. There is a problem.
そこで本発明はこのような問題点を解決するちので、そ
の目的とするところは、半導体装置の到湿性向上のため
プラズマシリコン窒化膜を用いても、高抵抗多結晶シリ
コンの抵抗値が外部印加電圧により、変動しない半導体
装置を提供するところにある。Therefore, the present invention aims to solve these problems, and its purpose is that even if a plasma silicon nitride film is used to improve the wettability of semiconductor devices, the resistance value of high-resistance polycrystalline silicon will not change when applied externally. The purpose is to provide a semiconductor device that does not vary depending on voltage.
〔課題を解決するための手段１
本発明の半導体装置は、半導体基板上に形成された高抵
抗多結晶シリコン上に、イオン打ち込みにより生成され
た不対電子をちつシリコン絶縁膜層があり、その上にプ
ラズマシリコン窒化膜層があることを特徴とする。[Means for Solving the Problems 1] The semiconductor device of the present invention has a silicon insulating film layer on high-resistance polycrystalline silicon formed on a semiconductor substrate, which removes unpaired electrons generated by ion implantation. It is characterized by having a plasma silicon nitride film layer thereon.
［作 用１
本発明の上記の構成によれば、不活性元素をシリコン酸
化膜にイオン打ち込みを行うことにより、５ｉ−３ｉ、
５ｉ−０、及び５ｉ−０−Ｈの結合を切り、前記シリコ
ン酸化膜中の不対電子密度を増加させることによって、
プラズマシリコン窒化膜生成時の水素、及びプラズマシ
リコン窒化膜中より拡散する水素を前記シリコン酸化膜
中に捕獲することができる。従って、プラズマシリコン
窒化膜を半導体装置の保護膜として用いても、外部印加
電圧による高抵抗多結晶シリコンの抵抗値の変動は生じ
ない。[Function 1] According to the above configuration of the present invention, by ion implanting an inert element into the silicon oxide film, 5i-3i,
By cutting the bonds of 5i-0 and 5i-0-H and increasing the unpaired electron density in the silicon oxide film,
Hydrogen during the formation of the plasma silicon nitride film and hydrogen diffused from within the plasma silicon nitride film can be captured in the silicon oxide film. Therefore, even if a plasma silicon nitride film is used as a protective film of a semiconductor device, the resistance value of high-resistance polycrystalline silicon does not vary due to externally applied voltage.
［実 施 例］
第１図は、本発明の実施例における半導体装置の断面図
を示す、１０１は、シリコン基板、１０２はシリコン酸
化膜、１０３は高抵抗多結晶シリコン、１０４はＮ型多
結晶シリコン、１０５は層間絶縁膜、１０６はアルミニ
ウム配線層、】０７はシリコン酸化膜、１０８は不対電
子を６つシリコン酸化膜、１０９はプラズマシリコン窒
化膜である０本実施例のように、高抵抗多結晶シリコン
を覆うように不対電子をもつシリコン酸化膜１０８があ
る為に、プラズマシリコン窒化膜１０９がらの水素は、
捕獲され、高抵抗多結晶シリコン１０３まで拡散しない
。[Embodiment] FIG. 1 shows a cross-sectional view of a semiconductor device according to an embodiment of the present invention. 101 is a silicon substrate, 102 is a silicon oxide film, 103 is a high-resistance polycrystalline silicon, and 104 is an N-type polycrystalline silicon. 07 is a silicon oxide film, 108 is a silicon oxide film with six unpaired electrons, and 109 is a plasma silicon nitride film. Since there is a silicon oxide film 108 with unpaired electrons covering the resistor polycrystalline silicon, hydrogen from the plasma silicon nitride film 109 is
It is captured and does not diffuse to the high resistance polycrystalline silicon 103.
次に、本発明の製造方法について説明する。まず、シリ
コン基板ｌ○】に、シリコン酸化膜１０２を形成した後
に、ＣＶＤ法により多結晶シリコンを１０００＾蒸着し
、所望の箇所にイオン打ち込みにより、燐を４ Ｘ １
０ ”ｃｍ−”打ち込み、高抵抗多結晶シリコン１０３
、Ｎ型多結晶シリコン１０４をそれぞれ作り、所望の形
状に加工したのち、その上に、ＣＶＤ法により燐を含む
シリコン酸化膜を堆積し、層間絶縁膜１０５を形成した
後、拡散炉を用いてアニールを行い、不純物を活性化す
る０次に、所望の箇所に、コンタクトホールを形成した
後に、スパッター法によりアルミニウムを堆積し、所望
の形状に加工し、アルミニウム配線層１０６を作り、水
素雰囲気中で、シンターを行う０以上で半導体素子およ
び相互配線が作られる。最後に、保護膜として、まず、
ＣＶＤ法によりシリコン酸化膜を４０００人堆積した後
、アルゴンイオンを１５０Ｋｅｙで、ｌＸｌ０”ｃｍ−
”打ち込み、シリコン酸化膜１０７と不対電子をもつシ
リコン酸化膜１０８を作り、次に、プラズマＣＶＤ法を
用いて、プラズマシリコン窒化膜１０９を、５ｏｏｏ＾
形成する０以上の工程を経て、本発明の半導体装置が完
成する。上記実流例の方法によれば、イオン打ち込みに
よりシリコン酸化膜の上部の約０．２μｍに、約５Ｘ１
０”ｃｍ−”の不活性ガスが存在し、不対電子も、同等
存在する。一般に、装置やガス流量などにもよるが、４
００℃前後で堆積されるプラズマシリコン窒化膜から、
通常約１０ ”ｃ ｍ’−”の水素が拡散する。しかし
、イオン打ち込みにより生成された不対電子濃度が高い
ために、その水素の多くは捕獲される。Next, the manufacturing method of the present invention will be explained. First, a silicon oxide film 102 is formed on a silicon substrate l○], then 1000^ of polycrystalline silicon is deposited by CVD method, and 4×1 phosphorus is deposited at desired locations by ion implantation.
0 "cm-" implant, high resistance polycrystalline silicon 103
, N-type polycrystalline silicon 104 is made and processed into a desired shape, and then a silicon oxide film containing phosphorus is deposited thereon by the CVD method, an interlayer insulating film 105 is formed, and then a diffusion furnace is used to form an interlayer insulating film 105. Annealing is performed to activate the impurities. Next, after forming contact holes at desired locations, aluminum is deposited by sputtering and processed into the desired shape to form an aluminum wiring layer 106, which is placed in a hydrogen atmosphere. Semiconductor elements and interconnections are created by sintering. Finally, as a protective film,
After depositing 4,000 silicon oxide films using the CVD method, argon ions were deposited with a key of 150 to lXl0"cm-
``By implantation, a silicon oxide film 107 and a silicon oxide film 108 having unpaired electrons are formed, and then a plasma silicon nitride film 109 is formed using a plasma CVD method.
The semiconductor device of the present invention is completed through zero or more forming steps. According to the method of the above-mentioned actual flow example, approximately 5×1
There is 0"cm-" of inert gas and an equal amount of unpaired electrons. In general, it depends on the equipment, gas flow rate, etc., but
From plasma silicon nitride film deposited at around 00℃,
Typically about 10 "cm'-" of hydrogen diffuses. However, due to the high concentration of unpaired electrons generated by ion implantation, much of the hydrogen is captured.
上記実施例では、アルミニウム配線上に、シリコン酸化
膜を用いたが、可動イオンによる汚染を防止するために
、燐を含んだシリコン酸化膜を用いても、同等の効果が
得られる。さらには、アルゴンイオンを打ち込んだが、
他の不活性元素、あるいは、耐湿性に影響を与えない砒
素や硼素を用いても同等の効果が得られる１本発明の趣
旨を逸脱しない範囲において、種々変更可能な事は言う
までもない。In the above embodiment, a silicon oxide film is used on the aluminum wiring, but the same effect can be obtained by using a silicon oxide film containing phosphorus to prevent contamination by mobile ions. Furthermore, although argon ions were implanted,
The same effect can be obtained by using other inert elements or arsenic or boron which do not affect the moisture resistance.It goes without saying that various changes can be made without departing from the spirit of the present invention.
［発明の効果１
以上述べたように本発明によれば、保護膜としてイオン
打ち込みにより生成された不対電子をもつシリコン酸化
膜を用いることにより、プラズマシリコン窒化膜を積層
しても、水素による外部印加電圧による高抵抗多結晶シ
リコンの抵抗値の変動が生じないという効果を有する。[Effect of the invention 1 As described above, according to the present invention, by using a silicon oxide film with unpaired electrons generated by ion implantation as a protective film, even if a plasma silicon nitride film is stacked, hydrogen-induced This has the effect that the resistance value of high-resistance polycrystalline silicon does not vary due to externally applied voltage.
第１図は、本発明の半導体装置の一実施例を示す主要断
面図。
１０１ ・
０２
１０３ ・
ｌ ○ ４ ・
１０５ ・
１０６ ・
０７
０８
１０９ ・
シリコン基板
シリコン酸化膜
高抵抗多結晶シリコン
Ｎ型多結晶シリコン
層間絶縁膜
アルミニウム配線層
シリコン酸化膜
不対電子をもつシリコン酸化膜
プラズマシリコン窒化膜
／Ｄ／
俤
田FIG. 1 is a main sectional view showing an embodiment of a semiconductor device of the present invention. 101 ・ 02 103 ・ l ○ 4 ・ 105 ・ 106 ・ 07 08 109 ・ Silicon substrate Silicon oxide film High resistance polycrystalline silicon N-type polycrystalline silicon Interlayer insulation film Aluminum wiring layer Silicon oxide film Silicon oxide film with unpaired electrons Plasma Silicon nitride film/D/ Toda
Claims (3)
上に、イオン打ち込みにより生成された不対電子をもつ
シリコン絶縁膜層があり、その上にプラズマシリコン窒
化膜層があることを特徴とする半導体装置。(1) A silicon insulating film layer with unpaired electrons generated by ion implantation is provided on high-resistance polycrystalline silicon formed on a semiconductor substrate, and a plasma silicon nitride film layer is provided on top of the silicon insulating film layer. semiconductor devices.
いは燐を含んだシリコン酸化膜層からなることを特徴と
する請求項１記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the silicon insulating film layer is a silicon oxide film layer or a silicon oxide film layer containing phosphorus.
不活性元素、硼素、あるいは、砒素であることを特徴と
する請求項１記載の半導体装置。(3) The impurity implanted by the ion implantation is
2. The semiconductor device according to claim 1, wherein the semiconductor element is an inert element, boron, or arsenic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17850289A JPH0342831A (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17850289A JPH0342831A (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0342831A true JPH0342831A (en) | 1991-02-25 |
Family
ID=16049587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17850289A Pending JPH0342831A (en) | 1989-07-11 | 1989-07-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0342831A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5500553A (en) * | 1992-08-12 | 1996-03-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes |
-
1989
- 1989-07-11 JP JP17850289A patent/JPH0342831A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5500553A (en) * | 1992-08-12 | 1996-03-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes |
| US5956592A (en) * | 1992-08-12 | 1999-09-21 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes |
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