JPH0342823A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0342823A JPH0342823A JP17881289A JP17881289A JPH0342823A JP H0342823 A JPH0342823 A JP H0342823A JP 17881289 A JP17881289 A JP 17881289A JP 17881289 A JP17881289 A JP 17881289A JP H0342823 A JPH0342823 A JP H0342823A
- Authority
- JP
- Japan
- Prior art keywords
- film resistor
- thin film
- contact hole
- thin
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000010409 thin film Substances 0.000 claims abstract description 45
- 239000010408 film Substances 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000009413 insulation Methods 0.000 claims abstract 4
- 238000005530 etching Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 6
- 238000005553 drilling Methods 0.000 claims 1
- 239000011229 interlayer Substances 0.000 abstract description 8
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 2
- 238000003379 elimination reaction Methods 0.000 abstract 3
- 230000008021 deposition Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は１ｌＷ１４抵抗を有する半導体装置とその製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a 11W14 resistor and a method for manufacturing the same.
本発明は基板あるいはゲート電極等のコンタクトホール
上に薄膜抵抗を残すことによって、薄膜抵抗と金属配線
の眉間絶縁膜形成を容易にするものである。The present invention facilitates the formation of an insulating film between the thin film resistor and metal wiring by leaving the thin film resistor on the substrate or the contact hole of the gate electrode or the like.
第２図は、従来の薄膜抵抗を有する半導体装置の断面構
造図である。半導体基板２１の表面にＭＯＳトランジス
タを構成するゲート電極２２．ソースドレイン領域２３
がある。ソースドレイン領域２３゜ゲート電極２２には
眉間絶縁膜２４をデポした後、コンタクトホール２５が
あけられ、配線金属２９によって外部と接続している。FIG. 2 is a cross-sectional structural diagram of a semiconductor device having a conventional thin film resistor. A gate electrode 22 constituting a MOS transistor is formed on the surface of the semiconductor substrate 21. Source drain region 23
There is. After a glabellar insulating film 24 is deposited on the source/drain region 23° gate electrode 22, a contact hole 25 is opened and connected to the outside via a wiring metal 29.
また、薄膜抵抗２６の上に抵抗層間絶縁膜２７があり、
薄Ｗ４抵抗コンタクトホール２８により、薄膜抵抗２６
は配線金属２９と接続されている。Further, there is a resistor interlayer insulating film 27 on the thin film resistor 26,
The thin W4 resistor contact hole 28 allows the thin film resistor 26
is connected to the wiring metal 29.
従来の薄膜抵抗を有する半導体装置では、薄膜抵抗２６
の層間絶縁膜２７がコンタクトホール２５を被い、これ
をエツチング除去する時に、コンタクトホールをエツチ
ングしてしまい、コンタクトホール２５の変形（コンタ
クトホール２５の径が大きくなる）をそのバラツキの増
大を生じていた。In a semiconductor device having a conventional thin film resistor, the thin film resistor 26
The interlayer insulating film 27 covers the contact hole 25, and when it is removed by etching, the contact hole is etched, causing deformation of the contact hole 25 (the diameter of the contact hole 25 increases) and an increase in its dispersion. was.
このため、薄膜抵抗を有する半導体装置では、コンタク
トホール２５の周辺の設計に大きなマージンを見込まね
ばならず、微細化の障害になるばかりか、１１膜抵抗を
含まない半導体装置で設計されたパターンをそのまま使
用できず、設計負荷の増大を生じていた。For this reason, in a semiconductor device having a thin film resistor, a large margin must be allowed in the design around the contact hole 25, which not only becomes an obstacle to miniaturization, but also prevents a pattern designed for a semiconductor device that does not include an 11-film resistor. It could not be used as is and the design load increased.
本発明は、前記従来の欠点を解決するために、コンタク
トホールに￥ｉｌ膜抵抗を残すことで、薄膜抵抗を眉間
絶縁膜のエツチングの終点として利用するものである。In order to solve the above-mentioned conventional drawbacks, the present invention leaves a \il film resistor in the contact hole and utilizes the thin film resistor as the end point of the etching of the glabella insulating film.
これによりコンタクトホールの変形とバラツキの増大を
防ぎ、コンタクトホール周辺の設計マージンを小さくで
き、微細化を達成できるようにしたものである。これに
より、薄膜抵抗を有無に関わりなく、コンタクトホール
回りの設計が可能になり、設計負荷が減少できる。This prevents contact hole deformation and increase in variation, reduces the design margin around the contact hole, and enables miniaturization. This makes it possible to design the area around the contact hole regardless of the presence or absence of a thin film resistor, reducing the design load.
以下、本発明の実施例を図面を用いて詳細に説明する。 Embodiments of the present invention will be described in detail below with reference to the drawings.
第１図は、本発明の実施例の半導体装置の断面構造図で
ある。FIG. 1 is a cross-sectional structural diagram of a semiconductor device according to an embodiment of the present invention.
半導体基板ｌの表面に、ＭＯＳトランジスタを構成する
ゲート電極２．ソースドレイン領域３がある。ソースド
レイン領域３．ゲート電極２には眉間絶縁膜４ （ＢＰ
ＳＧ膜等）デポジションした後にコンタクトホール５が
あけられている。さらに、コンタクトホール５には、コ
ンタクトホールを被う薄膜抵抗１０があり、この薄膜抵
抗１０の上に配線金属９がある。また抵抗素子を構成す
る薄膜抵抗６の上に、抵抗層間絶縁膜７があり、薄膜抵
抗コンタクトホール８により、薄膜抵抗６は配線金属９
に接続されている。A gate electrode 2 constituting a MOS transistor is formed on the surface of the semiconductor substrate l. There is a source drain region 3. Source drain region 3. The gate electrode 2 is provided with a glabella insulating film 4 (BP
A contact hole 5 is formed after the SG film (SG film, etc.) is deposited. Further, in the contact hole 5, there is a thin film resistor 10 covering the contact hole, and on this thin film resistor 10 there is a wiring metal 9. Further, there is a resistor interlayer insulating film 7 on the thin film resistor 6 constituting the resistor element, and the thin film resistor 6 is connected to the wiring metal 9 by the thin film resistor contact hole 8.
It is connected to the.
本発明では、ゲート電極２、ソースドレイン領域３等と
配線金属９とは薄膜抵抗１０を介して接続されている。In the present invention, the gate electrode 2, source/drain region 3, etc. and the wiring metal 9 are connected via the thin film resistor 10.
この薄膜抵抗の抵抗率は高いが、厚さは１０００Å以下
と極めて薄く、コンタクト抵抗の増加は発生しない、ま
た薄膜抵抗１０がコンタクトホール５を被うことで、薄
膜抵抗コンタクトホール８をあける時のエンチングで、
コンタクトホール５の径が大きくなることを防止するエ
ツチングストンパーになっている。Although the resistivity of this thin film resistor is high, the thickness is extremely thin at 1000 Å or less, so no increase in contact resistance occurs. With enching,
It serves as an etching stopper that prevents the diameter of the contact hole 5 from increasing.
第３図（ａ）〜（ｄ＋は本発明の半導体装置の製造工程
順の断面図である。第３図（Ａ）は、半導体基板１の表
面に、ゲート電極２．ソースドレイン領域３を形成後、
眉間絶縁膜（ＢＰＳＧ膜）４をデポジションし、コンタ
クトホール５をあけ、コンタクトホールのエツジを滑ら
かにするりフロー熱処理した工程の断面図である。3(a) to 3(d+) are cross-sectional views of the semiconductor device of the present invention in the order of manufacturing steps. FIG. rear,
It is a cross-sectional view showing the process of depositing a glabellar insulating film (BPSG film) 4, opening a contact hole 5, smoothing the edge of the contact hole, and carrying out flow heat treatment.
第３図中）は、薄膜抵抗体をデポジションした後、少な
くともコンタクトホールを被う薄膜抵抗１０と、抵抗素
子となる薄膜抵抗６以外の薄膜抵抗体をエンチング除去
した工程の断面図である。3) is a cross-sectional view of a step in which, after depositing a thin film resistor, the thin film resistors other than at least the thin film resistor 10 covering the contact hole and the thin film resistor 6 serving as a resistance element are removed by etching.
第３図（Ｃ１は薄膜抵抗６の層間絶縁膜７をデポジショ
ンした後、′ＦＩＩＷＡ抵抗６のコンタクトホール８を
あけるとともに、不用な眉間絶縁膜７をエツチング除去
した工程の断面図である。コンタクトホール５は、′ｒ
ｉＩｌｌ！抵抗１０で被われているため、コンタクトホ
ールを被う眉間絶縁膜をエンチング除去しても、薄膜抵
抗１０でエンチングは終了し、層間絶縁膜４をエツチン
グするおそれはなく、コンタクトホール５の変形は起こ
さない。FIG. 3 (C1 is a cross-sectional view of the process in which, after depositing the interlayer insulating film 7 of the thin film resistor 6, the contact hole 8 of the FIIWA resistor 6 is opened and the unnecessary glabellar insulating film 7 is removed by etching. Contact Hall 5 is 'r
iIll! Since it is covered with the resistor 10, even if the glabellar insulating film covering the contact hole is removed by etching, the etching will be completed by the thin film resistor 10, and there is no risk of etching the interlayer insulating film 4, and the contact hole 5 will not be deformed. I won't wake you up.
第３図１ｄｌは、配線金ＩＥ９をデポジションした後、
不用な配線金属をエツチング除去して、半導体装置を完
成させた工程を示す断面図である。この配線金属９のエ
ツチング工程で、配線金属９のパターンをはみ出たコン
タクトホールを被う薄膜抵抗ｌＯもエツチング除去され
る。FIG. 3 1dl shows that after depositing the wiring gold IE9,
FIG. 3 is a cross-sectional view showing a process of completing a semiconductor device by etching away unnecessary wiring metal. In this process of etching the wiring metal 9, the thin film resistor lO covering the contact hole protruding from the pattern of the wiring metal 9 is also etched away.
以上の説明で明らかなように、本発明はコンタクトホー
ルに薄膜抵抗を残すことによって、コンタクトホールの
変形を生じずに、薄膜抵抗にコンタクトホールが開けら
れ、半導体装置の微細化と設計負荷が減少でき、実用性
の高い薄膜抵抗を有する半導体装置を提供するものであ
る。As is clear from the above description, the present invention allows the contact hole to be opened in the thin film resistor without deforming the contact hole by leaving the thin film resistor in the contact hole, thereby reducing the miniaturization of semiconductor devices and the design load. The present invention provides a semiconductor device having a highly practical thin film resistor.
第１図は本発明の実施例の半導体装置の断面図であり、
第２図は従来の薄膜抵抗を有する半導体装置の断面構造
図、第３図（ａｌ〜（ｄｌは本発明の半導体装置の製造
工程順の断面構造図である。
ｌ、２１・・・半導体基板
２．２２・ ・ ・ゲート電極
３．２３・・・ノースドレイン領域
５．２５・・・コンタクトホール
６．２６・・・薄膜抵抗
９．２９・・・配線金属
１０・・・・・コンタクトホールを被う薄膜抵抗以上FIG. 1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention,
FIG. 2 is a cross-sectional structural diagram of a conventional semiconductor device having a thin film resistor, and FIG. 3 is a cross-sectional structural diagram of a semiconductor device according to the present invention in the order of manufacturing steps. 2.22... Gate electrode 3.23... North drain region 5.25... Contact hole 6.26... Thin film resistor 9.29... Wiring metal 10... Contact hole overlying thin film resistance
Claims (2)
導体装置において、少なくとも基板あるいはゲート電極
と金属配線とが薄膜抵抗を介して接続されていることを
特徴とする半導体装置。(1) A semiconductor device having a thin film resistor on an insulating film on the surface of a semiconductor substrate, characterized in that at least a substrate or a gate electrode and a metal wiring are connected via the thin film resistor.
工程と、 半導体基板表面に抵抗薄膜をデポジションし、少なくと
もコンタクトホール部分と薄膜抵抗素子部分の抵抗薄膜
を残し、抵抗薄膜をエッチングする工程と、 絶縁膜をデポジションし、薄膜抵抗にコンタクトホール
をあける工程と、 金属配線を形成する工程からなる半導体装置の製造方法
。(2) a step of forming a MOS transistor on the surface of the semiconductor substrate, a step of depositing a resistive thin film on the surface of the semiconductor substrate, leaving at least the resistive thin film in the contact hole portion and the thin film resistor element portion, and etching the resistive thin film; and insulation. A method for manufacturing semiconductor devices that consists of the steps of depositing a film, drilling contact holes in the thin film resistor, and forming metal wiring.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17881289A JPH0342823A (en) | 1989-07-10 | 1989-07-10 | Semiconductor device and its manufacture |
| US07/547,785 US5128745A (en) | 1989-07-05 | 1990-07-03 | Semiconductor device with thin film resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17881289A JPH0342823A (en) | 1989-07-10 | 1989-07-10 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0342823A true JPH0342823A (en) | 1991-02-25 |
Family
ID=16055091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17881289A Pending JPH0342823A (en) | 1989-07-05 | 1989-07-10 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0342823A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993009599A2 (en) * | 1991-10-30 | 1993-05-13 | Harris Corporation | Analog-to-digital converter and method of fabrication |
| KR100602864B1 (en) * | 2003-06-11 | 2006-07-20 | 가부시키가이샤 리코 | Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same |
-
1989
- 1989-07-10 JP JP17881289A patent/JPH0342823A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993009599A2 (en) * | 1991-10-30 | 1993-05-13 | Harris Corporation | Analog-to-digital converter and method of fabrication |
| KR100602864B1 (en) * | 2003-06-11 | 2006-07-20 | 가부시키가이샤 리코 | Semiconductor apparatus including a thin-metal-film resistor element and a method of manufacturing the same |
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