JPH0342817B2 - - Google Patents

Description

Detailed Description of the Invention [Industrial Application Field] The present invention counts a count value to be increased or decreased according to the value of a binary signal, and the count value is set to a predetermined lower limit or upper limit. The present invention relates to a counter device having the function of generating an output signal when a value is reached.

For example, a receiving device used for digital communication is equipped with a digital phase locked loop (DPLL) in order to match the phase of an internal clock with the phase of a received signal. A phase comparator detects the delay or lead in the rise time of the clock signal relative to the rise time of the received signal, and controls the internal clock to advance if it is late, and delays the internal clock if it is ahead. Such control is performed.

However, the phase of the received signal may change temporarily due to fluctuations in the receiving system, and in such cases it is not desirable to control the internal clock each time.
The number of phase delay detections in the phase comparator and the phase lead detection circuit are integrated by an up-down counter, and a control signal is sent to the internal clock only when the integrated value reaches a predetermined lower limit value or upper limit value. There is.

Furthermore, in order to be able to adapt to the type of receiving device or the state of the receiving system, the upper and lower limits of the up-down counter when transmitting the control signal are generally made variable.

By the way, these devices are constructed from various standardized digital elements including microprocessors, so reducing the number of signal bits used is an effective way to reduce the number of digital elements used. This is very important.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional example of a counter device. Binary signal C
This is an n-bit up-down counter configured to read the binary signal C, decrease the count value when it is "1", and increase the count value when it is "0".

2 is the output of up-down counter 1, that is, the lower limit value D1 of which the count value D is stored externally.
3 is a first comparator circuit that outputs a control signal E1 when the count value D of the up-down counter 1 reaches an externally stored upper limit value D2. A comparison circuit 4 outputs an initial value setting signal A to the up-down counter 1 when the first comparison circuit 2 outputs the control signal E1 or when the second comparison circuit 3 outputs the control signal. This is an OR circuit that outputs.

For example, if the number of bits n of the up-down counter 1 is 4, the initial value B is "1000", the lower limit value D1 is "1111", and the upper limit value D2 is "0000", after the initial value B is set, the up-down counter When the number of times the counter 1 reads "0" in the binary signal C reaches 9 times more than the number of times it reads "1", the count value reaches "1111".
The first comparator circuit 2 outputs a control signal E1.

Similarly, after the initial value B is set, when the number of times the up-down counter 1 reads "1" in the binary signal C reaches 8 times more than the number of times it reads "0", the count value changes. Reached "0000",
The second comparison circuit 3 outputs a control signal E2.

[Problem that the invention seeks to solve]

In the counter device having the above configuration, the first comparison circuit 2 and the second comparison circuit 3 each have n
Since it is necessary to compare the bit signals, there is a problem that the scale of the hardware increases, and in addition to the initial value set in the up-down counter 1, the On the other hand,
together as the upper and lower limits, respectively.
There is a problem in that a 2n-bit signal must be set.

[Means for solving problems]

The counter device according to the present invention includes a multi-bit up-down counter having an initial value setting function, and a combination of the input of the up-down counter and the value of each bit of a multi-bit binary number obtained as the output of the up-down counter. Performs a logical product and outputs the lower limit signal of the up-down counter.
an AND circuit, a multi-bit binary number whose least significant bit is the inverted output of the input of the up-down counter, and whose upper bits are binary numbers other than the most significant bit of an initial value to be set in the up-down counter; and the up-down counter. a matching circuit that detects a match with a multi-bit binary number obtained as an output of the up-down counter, performs a logical product of each output of the match detection, and outputs an upper limit value signal of the up-down counter; The above-mentioned problem is solved by setting the initial value in which the most significant bit is 0 in the up-down counter using a value signal.

[Effect]

That is, in the present invention, an AND circuit and a matching circuit are used as a lower limit value detection circuit or an upper limit value detection circuit. By using an AND circuit, the circuit configuration can be simplified, and the initial value can be input to the up-down counter. Other than setting the lower limit value and upper limit value, there is no need to set the upper limit value.

〔Example〕

The gist of the present invention will be specifically explained below using an embodiment shown in FIG.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, in which the same symbols as those in FIG. 2 refer to the same objects, and 1' indicates the most significant bit when the initial value setting signal A is input. After setting as the initial value an n-bit binary number B' whose lower bits are an externally stored (n-1)-bit binary number with "0", the binary signal C to be counted is set. This is a binary n-digit up-down counter configured to read and decrease the count value when the binary signal C is "1" and increase the count value when it is "0".

2' is an AND circuit that obtains the logical product of the input C of the up-down counter 1' and the value of each bit of its output D, and 5 is a NOT circuit that obtains the inverted output of the input C of the up-down counter 1'.

3' is an n-bit binary number in which the output of the NOT circuit 5 is the least significant bit and the upper bit is a binary number excluding the most significant bit of the initial value set in the up-down counter 1'; This is a matching circuit that detects a match with the n-bit binary number obtained as the output of .

Note that 31, 32, and 33 are an EOR circuit/NOT circuit and an AND circuit, respectively, which constitute the matching circuit 3'.

For example, if the number of bits n of the up-down counter 1' is 4, the up-down counter 1'
If the initial value B' to be set is "0000", when the count value of the up-down counter 1' reaches the lower limit value "1111", the AND circuit 2' outputs the control signal E1, and the up-down counter 1' When the count value of ' reaches the upper limit value "0001", the matching circuit 3' outputs the control signal E2, and therefore a ±1 stage counter device is constructed.

Similarly, if you set the initial values for the up-down counter 1' as shown in the following table, when the count value of the up-down counter 1' reaches the lower limit value or upper limit value as shown, respectively,
AND circuit 2' outputs control signal E1, and coincidence circuit 3' outputs control signal E2.

Note that the most significant bit of the initial value B' set in the up-down counter 1' is constant and always remains at "0", so only the lower 3 bits of the initial value B' are stored externally and selected according to the number of stages. do it.

Table Initial value Lower limit Upper limit Number of stages 0000 1111 0001 ±1 0001 1111 0011 ±2 0010 1111 0101 ±3 0011 1111 0111 ±4 0100 1111 1001 ±5 0101 1111 1011 ±6 0110 11 11 1101 ±7 [Effect of the invention] Above explanation As described above, according to the present invention, either the comparison circuit that detects that the count value of the up-down counter reaches the upper limit value or the lower limit value can be configured by an AND circuit.

In addition, there is no need to set the lower and upper limits separately other than setting a binary number that is 1 bit less than the number of bits of the up-down counter as the initial value, so you can reduce the number of bits of the signal used and The number can be reduced.

Therefore, not only can the scale of the hardware be reduced, but also the effects of easier handling can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional example. In the figure, 1' is an up-down counter, and 2' is an up-down counter.
AND circuit, 3' is matching circuit, 4 is OR circuit, 5 is
It is a NOT circuit.

Claims (1)

[Scope of Claims] 1. A multi-bit up-down counter having an initial value setting function, and logic between the input of the up-down counter and the value of each bit of a multi-bit binary number obtained as the output of the up-down counter. Take the product and output the lower limit signal of the up-down counter.
an AND circuit, a multi-bit binary number whose least significant bit is the inverted output of the input of the up-down counter, and whose upper bits are binary numbers other than the most significant bit of an initial value to be set in the up-down counter; and the up-down counter. a matching circuit that detects a match with a multi-bit binary number obtained as an output of the up-down counter, performs a logical product of each output of the match detection, and outputs an upper limit value signal of the up-down counter; A counter device characterized in that the initial value whose most significant bit is 0 is set in the up-down counter by a value signal.