JPH0342702B2 - - Google Patents
Info
- Publication number
- JPH0342702B2 JPH0342702B2 JP60120439A JP12043985A JPH0342702B2 JP H0342702 B2 JPH0342702 B2 JP H0342702B2 JP 60120439 A JP60120439 A JP 60120439A JP 12043985 A JP12043985 A JP 12043985A JP H0342702 B2 JPH0342702 B2 JP H0342702B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- heat transfer
- integrated circuit
- transfer body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 28
- 239000000919 ceramic Substances 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 14
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 238000009835 boiling Methods 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 4
- 239000003566 sealing material Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 239000012809 cooling fluid Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000009719 polyimide resin Substances 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 239000008393 encapsulating agent Substances 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 230000001737 promoting effect Effects 0.000 claims 1
- 238000001816 cooling Methods 0.000 description 14
- 239000004519 grease Substances 0.000 description 6
- 239000007788 liquid Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 239000003507 refrigerant Substances 0.000 description 4
- 238000012360 testing method Methods 0.000 description 3
- 239000002826 coolant Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 239000000498 cooling water Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005187 foaming Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、複数の集積回路チツプが搭載された
配線基板を単位モジユールとし、一個のモジユー
ルあるいは複数個のモジユールを含んで構成され
るマルチチツプモジユールに係り、特に電子計算
機に用いるのに適したマルチチツプモジユールに
関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention uses a wiring board on which a plurality of integrated circuit chips are mounted as a unit module, and a multi-chip device comprising one module or a plurality of modules. The present invention relates to modules, and particularly to multichip modules suitable for use in electronic computers.
従来のマルチチツプモジユールにおけるチツプ
封じ法としては、実公昭57−44700号公報に記載
されたようなチツプをセラミツク基板に設けた凹
みの底に装着し、これに凸状部を有するヒートシ
ンクを押し当てる方法と、特公昭57−48860号報
に記載の如くセラミツク基板全体を一体のキヤツ
プで覆い基板の周辺部で封じをする方法とがあ
る。
Conventional chip sealing methods for multi-chip modules include mounting a chip as described in Japanese Utility Model Publication No. 57-44700 on the bottom of a recess provided in a ceramic substrate, and pressing a heat sink having a convex portion onto the chip. There are two methods: a method in which the entire ceramic substrate is covered with an integral cap and the periphery of the substrate is sealed, as described in Japanese Patent Publication No. 57-48860.
前者における凹みは熱伝導グリースを保持する
ためのもので、チツプの封じを目的としたもので
はなく、封じは後者と同様、モジユール全体の封
じを考えている。
The recesses in the former are for holding thermally conductive grease and are not intended to seal the chip, and the seal is intended to seal the entire module, similar to the latter.
モジユール全体を封じする場合、次のような問
題点がある。 When sealing the entire module, there are the following problems.
まず、セラミツク等の基板は、焼結時に与えら
れる熱覆歴のため、反つている。この基板の反り
のため、集積回路チツプとキヤツプの内壁面との
距離がチツプごとに不均一になる。このため、熱
伝導グリースなどを用いチツプとキヤツプ内壁面
との熱的結合を図る場合、熱伝導グリースの層を
厚くしなければならないチツプがでてくる。熱伝
導グリース層を厚くするとチツプとキヤツプ間の
熱コンダクタンスは非常に小さなものとなる。例
えば、市販の熱伝導グリース（熱伝導率７×
10-4W／Ｋmm）を１mm厚で使用した場合、熱コン
ダクタンスは７×10-4W／Ｋmm2と非常に小さい。
そのため、キヤツプ外面を例えば強制液冷（熱伝
導率〜２×10-2W／Ｋmm2）、沸騰冷却（〜１×
10-2W／Ｋmm2）など高性能な冷却方法をもつてし
ても十分な冷却効果が得られない。ピストン等の
熱伝導部材を用いてチツプとキヤツプとを熱的に
接続する方法もあるが、熱コンダクタンスは
0.5W／Ｋmm2程度が限界であり、キヤツプ自体の
熱伝導率を比べると小さい。 First, substrates such as ceramics warp due to the thermal history given during sintering. Because of this substrate warpage, the distance between the integrated circuit chip and the inner wall surface of the cap becomes non-uniform from chip to chip. For this reason, when thermally bonding the chip and the inner wall surface of the cap using thermally conductive grease or the like, some chips require a thick layer of thermally conductive grease. When the thermal conductive grease layer is thickened, the thermal conductance between the chip and the cap becomes very small. For example, commercially available thermal conductive grease (thermal conductivity 7×
10 -4 W/Kmm) with a thickness of 1 mm, the thermal conductance is extremely small at 7×10 -4 W/Kmm 2 .
Therefore, the outer surface of the cap can be cooled by, for example, forced liquid cooling (thermal conductivity ~2×10 -2 W/Kmm 2 ), boiling cooling (~1×
Even with high-performance cooling methods such as 10 -2 W/Kmm 2 ), a sufficient cooling effect cannot be obtained. There is also a method of thermally connecting the chip and cap using a heat conductive member such as a piston, but thermal conductance
The limit is about 0.5W/Kmm2, which is small compared to the thermal conductivity of the cap itself.
また、従来のものは、検査パツドや論理変更パ
ツド等の目的で用いられる技術パツドがセラミツ
ク基板上に設けられており、回路の検査や論理変
更は、封じを除去しないと行なうことができな
い。 Furthermore, in the conventional circuit, technology pads used for purposes such as test pads and logic change pads are provided on the ceramic substrate, and circuit inspection and logic change cannot be performed without removing the seal.
前記特公昭57−48860号公報には、半田パツド
及び技術変更パツドがセラミツク基板上に設けら
れた例が示されているが、半田パツドや冷却液中
に浸ることは、該パツドと集積回路チツプとの接
続部分が腐食される恐れがある。本発明は、集積
回路チツプの各チツプと、チツプ上に搭載される
伝熱体の距離を小さくして熱抵抗を減少させると
共に、チツプの封じを除去しなくても技術変更パ
ツドを使用できるようにすることにある。 The above-mentioned Japanese Patent Publication No. 57-48860 shows an example in which solder pads and technology change pads are provided on a ceramic substrate. There is a risk that the connecting parts may be corroded. The present invention reduces the distance between each chip of an integrated circuit chip and a heat transfer body mounted on the chip to reduce thermal resistance and allows the use of technology-modified pads without removing the chip encapsulation. The goal is to
上記目的を達成するために、基板に凹部を形成
し、該部分に集積回路チツプを配置し、技術変更
パツドを基板表面に移し、チツプ上に搭載される
伝熱体の外周と前記凹部側面との間に封じ材料を
充填した。
In order to achieve the above objective, a recess is formed in the substrate, an integrated circuit chip is placed in the recess, a technology change pad is transferred to the surface of the substrate, and the outer periphery of the heat transfer body mounted on the chip and the side surface of the recess are formed. A sealing material was filled in between.
半田パツドと異なり、技術変更パツドはモジユ
ールの組み立て初期にのみ使用するものであるの
で、腐食による不具合はない。 Unlike solder pads, technologically modified pads are used only during the early stages of module assembly, so there are no problems caused by corrosion.
上記のように、基板に凹部を形成し、集積回路
チツプ個別あるいは少数のチツプグループ別に伝
熱体を設置し、封じを行なうので、基板に反りが
あつても、集積回路チツプとチツプ上に搭載され
る伝熱体の距離を小さくでき、熱抵抗が小さくな
る。
As mentioned above, since a recess is formed in the substrate and a heat transfer body is installed and sealed for each integrated circuit chip or a small group of chips, even if the substrate is warped, the integrated circuit chips and chips mounted on the chips are still intact. The distance between the heat transfer elements can be reduced, and the thermal resistance can be reduced.
さらに、技術変更パツドを封じの外側に設けて
いるので、集積回路の機能検査や論理変更に際
し、封じ構造を設けたままで行なえる。 Further, since the technology change pad is provided outside the seal, functional testing or logic changes of the integrated circuit can be performed without leaving the seal structure in place.
以下本発明の実施例を図により説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図において、セラミツク製の基板１には、
多数の集積回路チツプ２とその背面に取り付けら
れた伝熱体３とが搭載されている。基板１はバツ
クボード４に取り付けられた状態で密閉容器５に
組み込まれている。バツクボード４に取り付けら
れた基板１は、不電導性液１０に浸漬されてい
る。集積回路チツプ２の発熱により不電導性液１
０は、沸騰、発泡９する。沸騰した不電導性液１
０の蒸気は、容器５の上部に設けられた凝縮器６
で凝縮、液化１１し、再び容器下部の液部へ戻
る。凝縮器６には、冷却ユニツト８および循環ポ
ンプ７により冷却水が送り込まれており、容器５
内の蒸気を冷却する。 In FIG. 1, a ceramic substrate 1 includes:
A large number of integrated circuit chips 2 and a heat transfer body 3 attached to the back side thereof are mounted. The substrate 1 is assembled into a closed container 5 while being attached to a backboard 4. A substrate 1 attached to a backboard 4 is immersed in a non-conductive liquid 10. Due to the heat generated by the integrated circuit chip 2, the non-conductive liquid 1
0 means boiling and foaming 9. boiling nonconductive liquid 1
0 steam is passed through a condenser 6 installed at the top of the container 5.
It condenses and liquefies (11) and returns to the liquid part at the bottom of the container. Cooling water is fed into the condenser 6 by a cooling unit 8 and a circulation pump 7, and the container 5
Cool the steam inside.
第２図、第３図に、本発明の要部詳細を示す。
配線ピン１２を有するセラミツク基板１の、チツ
プ２を搭載する側に、現状の凹部を多数設け、該
凹部１００の底にハンダパツド１４を介してチツ
プ２を搭載し、基板の表面１１０に検査用又は、
論理変更用の技術変更パツド２１が設けられ、基
板内部の配線２０によりチツプとの電気的接続が
図られている。チツプの封じは、伝熱体３を凹部
１００に挿入し、該凹部の側壁１０２との間をハ
ンダなどの封じ材料２３により封じる。伝熱体３
の先端とチツプ２の間の〓間２４にはハンダある
いは、熱伝導グリースなどをつめて熱抵抗を極力
少なくする。これらの材料はあらかじめチツプの
面に取り付けておいてもよいが、伝熱体３に孔２
５を設け、充てん材２６を封入するようにしても
よい。伝熱体３は、例えば、沸騰冷却用のフイン
を兼ねるようにすることもでき、冷媒１０に浸漬
して気泡９を発生させ、チツプの発熱を効率よく
除去する。 FIGS. 2 and 3 show details of the main parts of the present invention.
A large number of current recesses are provided on the side of the ceramic substrate 1 having the wiring pins 12 on which the chip 2 is mounted, the chip 2 is mounted on the bottom of the recess 100 via the solder pad 14, and the surface 110 of the board is used for inspection or the like. ,
A technology change pad 21 for changing logic is provided, and electrical connection to the chip is achieved by wiring 20 inside the board. To seal the chip, the heat transfer body 3 is inserted into the recess 100, and the space between it and the side wall 102 of the recess is sealed with a sealing material 23 such as solder. Heat transfer body 3
The gap 24 between the tip of the chip 2 and the chip 2 is filled with solder or thermally conductive grease to reduce thermal resistance as much as possible. These materials may be attached to the surface of the chip in advance, but the holes 2 in the heat transfer body 3
5 may be provided and the filler 26 may be enclosed. For example, the heat transfer body 3 can also serve as a boiling cooling fin, and is immersed in the refrigerant 10 to generate bubbles 9 and efficiently remove heat generated from the chip.
沸騰冷却は、空気の強制対流による冷却法に比
べて、10倍以上の高い熱伝熱率をもたらす。 Boiling cooling provides a heat transfer rate more than 10 times higher than cooling methods using forced air convection.
本実施例では伝熱体３が拡大伝熱面としても働
くので更に大きな有効熱伝達率が得られる。この
ような高性能冷却法を用いるとき、チツプから冷
媒までの間に大きな熱抵抗を呈する部分がある
と、折角の高性能冷却法の効果が相殺されてしま
うが、個別にチツプを封じする本構造では、チツ
プの伝熱体３側の面と伝熱体３のチツプ側の面と
をできる限り近づけることができるので、該〓間
２４にハンダなど適当な充てん物を入れれば接触
熱抵抗を非常に小さくできる。本構造によれば、
封じ接合面にかかる応力は従来のこの種の封じ接
合面にかかる応力よりもきわめて小さく、熱履歴
に対し高い信頼性を持つことができる。また沸謄
冷却においては冷媒がチツプの回路面に接触する
と回路素子を腐食したり回路の誤動作をひき起す
危険性が増す。本構造においてチツプがある凹み
部を不活性ガス１８で満たしておけば、冷媒とチ
ツプが直接接触しないので上記の危険性が除かれ
る。なお、〓間充てん用材料２６を注入する構造
においては、注入材をハンダとし、注入後固化す
れば、凹部１００のガス圧は外部の圧力より若干
高くできるので、たとえ微細なクラツクが封じ接
合部２３に入つても、冷媒が凹部１００の内部に
侵入する可能性を小さくすることができる。 In this embodiment, since the heat transfer body 3 also functions as an enlarged heat transfer surface, an even larger effective heat transfer coefficient can be obtained. When using such a high-performance cooling method, if there is a part that exhibits large thermal resistance between the chip and the coolant, the effect of the high-performance cooling method will be canceled out. In terms of structure, the surface of the chip on the heat transfer body 3 side and the surface of the heat transfer body 3 on the chip side can be brought as close as possible, so if a suitable filler such as solder is placed in the gap 24, the contact thermal resistance can be reduced. Can be made very small. According to this structure,
The stress applied to the sealing joint surface is much smaller than that applied to conventional sealing joint surfaces of this type, and it can have high reliability against thermal history. Furthermore, in boiling cooling, if the refrigerant comes into contact with the circuit surface of the chip, there is an increased risk of corrosion of the circuit elements or malfunction of the circuit. In this structure, if the recess where the chip is located is filled with inert gas 18, the above-mentioned danger is eliminated because the refrigerant and the chip do not come into direct contact. In addition, in the structure in which the interfilling material 26 is injected, if the injected material is solder and solidifies after injection, the gas pressure in the recess 100 can be made slightly higher than the external pressure. 23, it is possible to reduce the possibility that the refrigerant will enter the inside of the recess 100.
一方、本発明では、技術変更パツド２１を基板
表面１１０の頂面に設けており、封止２３の外側
に位置する。したがつて、封止を外さず、冷却構
造体が動作した通常の動作状態で回路の機能検査
を行うことができる。これは、チツプジヤンクシ
ヨン温度が変わると論理動作の遅延時間が変わ
り、誤動作を起こす恐れがある論理LSIを、正確
に機能検査するために重要な機能である。論理変
更についても同様である。 In contrast, in the present invention, a technology change pad 21 is provided on the top of the substrate surface 110 and is located outside of the seal 23. Therefore, the functionality of the circuit can be tested in the normal operating state in which the cooling structure is operated without removing the seal. This is an important function for accurately testing the functionality of logic LSIs, which can cause malfunctions due to the delay time of logic operations changing as the chip juncture temperature changes. The same applies to logic changes.
第４図は数個のチツプ２をグループとして封止
したもので、技術変更パツド２１は基板の表面１
１０に設けられている。伝熱体３はフインを兼ね
ており、これに空気または液体の流れ３０を流し
チツプの発熱を除去する。 FIG. 4 shows several chips 2 encapsulated as a group, and the technology change pad 21 is on the surface 1 of the substrate.
10. The heat transfer body 3 also serves as a fin, and a flow of air or liquid 30 is passed through it to remove heat generated by the chip.
上記の実施例において、パツドが設けられる基
板凸部１１０を製作するには、従来からセラミツ
ク積層基板を製作するのを同じ方法によればよ
い。即ち第５図に示すように、配線パターンを有
する複数のセラミツクシート３１に角形あるいは
円形（図示せず）の孔を有し、かつパツドと基板
とを電気的に接続するための貫通導線あるいは配
線となるべき必要なスルーホール、メタンパター
ンを有するセラミツクシート３２を重ね焼結す
る。 In the above embodiment, the substrate protrusion 110 on which the pad is provided can be manufactured by the same method as conventionally used for manufacturing a ceramic laminated substrate. That is, as shown in FIG. 5, a plurality of ceramic sheets 31 having wiring patterns have square or circular (not shown) holes, and through conductive wires or wiring for electrically connecting the pads and the board. Ceramic sheets 32 having the necessary through holes and methane pattern are stacked and sintered.
セラミツクシートの代りに、ポリイミド樹脂な
どの他の有機薄膜を積層、接合して用いてもよ
い。基板表面の技術変更パツドと基板内の配線と
を電気的に接続するために、該積層シートに、貫
通導体や導体配線パターンを内蔵させる。 Instead of the ceramic sheet, other organic thin films such as polyimide resin may be laminated and bonded. In order to electrically connect the technology change pad on the surface of the board to the wiring within the board, the laminated sheet incorporates through conductors and conductor wiring patterns.
伝熱体としては、多孔質構造体、例えば、焼結
体や多数の微細溝を有する板を積層したものを採
用してもよい。 As the heat transfer body, a porous structure such as a sintered body or a stack of plates having a large number of fine grooves may be used.
本発明は、集積回路チツプを個別に、あるいは
少数のチツプのグループ別に、外周の冷却流体あ
るいは雰囲気を隔離するための封じを行ない、封
じの外側に技術変更パツドを設けたので各チツプ
を封じ伝熱体の間に距離をきわめて小さくするこ
とができるので、沸騰冷却液冷却など高性能冷却
法の効果を十分に活かすことができる。
The present invention seals integrated circuit chips individually or in small groups of chips to isolate cooling fluid or atmosphere around the periphery, and provides a technology change pad on the outside of the seal to seal each chip. Since the distance between the hot bodies can be made extremely small, the effects of high performance cooling methods such as boiling coolant cooling can be fully utilized.
さらに、技術変更パツドが封じの外側に露出し
ているので、封じ構造を設けたままで集積回路の
機能検査や論理変更ができる。この技術変更パツ
ドは、半田パツドと異なり、使用時期が初期に限
られるため、冷却流体に触れても問題はない。 Additionally, because the technology change pad is exposed outside the enclosure, the functionality of the integrated circuit can be tested and the logic changed while the enclosure structure remains in place. Unlike solder pads, this technologically modified pad can only be used in the early stages, so there is no problem even if it comes into contact with cooling fluid.
第１図は、本発明の一実施例の一部断面斜視
図、第２図は、本発明の要部拡大平面図、第３図
は、本発明の封じ部を示す要部縦断面図、第４図
は、本発明の他の実施例の斜視図、第５図は、本
発明の製法の一例を示す図である。
１……セラミツク製の基板、２……集積回路チ
ツプ、３……伝熱体、２１……パツド、２３……
封じ材料。
FIG. 1 is a partial cross-sectional perspective view of an embodiment of the present invention, FIG. 2 is an enlarged plan view of the main part of the present invention, and FIG. 3 is a longitudinal cross-sectional view of the main part showing the sealing part of the present invention. FIG. 4 is a perspective view of another embodiment of the present invention, and FIG. 5 is a diagram showing an example of the manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1... Ceramic substrate, 2... Integrated circuit chip, 3... Heat transfer body, 21... Pad, 23...
Sealing material.
Claims (1)
の集積回路チツプと、基板上で各集積回路チツプ
の付近に設けられた各チツプに接続される半田パ
ツド及び技術変更パツドと、１〜複数の集積回路
チツプ毎に設けられた伝熱体と、伝熱体の周囲に
設けられ冷却用流体を収容する室とを備えたマル
チチツプモジユールにおいて、前記基板は、各々
１〜複数の集積回路チツプを収容する凹部を複数
個備え、該凹部の底部分に前記半田パツドが設け
られ、一方凹部の側面と伝熱体の外周の間〓に封
じ材料が充填され、封じ材料の外側の基板表面に
前記技術変更パツドが設けられていることを特徴
とするマルチチツプモジユール。 ２ 特許請求の範囲第１項記載のマルチチツプモ
ジユールにおいて、前記基板は、該チツプに相当
する部分がくり貫かれたセラミツクシートあるい
はポリイミド樹脂などの有機薄膜、および、スル
ーホール部以外はむくのセラミツクシートあるい
はポリイミド樹脂などの有機薄膜を積層、接合す
ることにより該基板を形成し、技術変更パツドと
該基板内の配線とを電気的に接続するために、該
積層シートに導体配線パターンを内蔵する基板で
あることを特徴とするマルチチツプモジユール。 ３ 特許請求の範囲第１項記載のマルチチツプモ
ジユールにおいて、該チツプ封じ用伝熱体構造材
に沸騰熱伝達を促進するための多孔質構造を設け
たことを特徴とするマルチチツプモジユール。[Claims] 1. An insulating substrate, a plurality of integrated circuit chips mounted on the substrate, and solder pads and technology connected to each chip provided near each integrated circuit chip on the substrate. In a multi-chip module comprising a change pad, a heat transfer body provided for each one or more integrated circuit chips, and a chamber provided around the heat transfer body and containing a cooling fluid, the substrate includes: a plurality of recesses each accommodating one to a plurality of integrated circuit chips, the solder pads are provided at the bottoms of the recesses, and a sealing material is filled between the side surfaces of the recesses and the outer periphery of the heat transfer body; A multichip module characterized in that the technology change pad is provided on the surface of the substrate outside the encapsulant. 2. In the multi-chip module according to claim 1, the substrate is made of a ceramic sheet or an organic thin film such as polyimide resin, which is hollowed out in the portion corresponding to the chip, and is exposed except for the through-hole portion. The substrate is formed by laminating and bonding ceramic sheets or organic thin films such as polyimide resin, and a conductor wiring pattern is built into the laminated sheet in order to electrically connect the technology change pad and the wiring within the substrate. A multi-chip module characterized by being a board that 3. The multi-chip module according to claim 1, wherein the heat transfer body structural material for sealing the chips is provided with a porous structure for promoting boiling heat transfer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60120439A JPS61279156A (en) | 1985-06-05 | 1985-06-05 | Multiple chip module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60120439A JPS61279156A (en) | 1985-06-05 | 1985-06-05 | Multiple chip module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61279156A JPS61279156A (en) | 1986-12-09 |
| JPH0342702B2 true JPH0342702B2 (en) | 1991-06-28 |
Family
ID=14786230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60120439A Granted JPS61279156A (en) | 1985-06-05 | 1985-06-05 | Multiple chip module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61279156A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2019043835A1 (en) * | 2017-08-30 | 2020-09-24 | 日本電気株式会社 | Electronic device |
-
1985
- 1985-06-05 JP JP60120439A patent/JPS61279156A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61279156A (en) | 1986-12-09 |
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