JPH034145B2 - - Google Patents
Info
- Publication number
- JPH034145B2 JPH034145B2 JP58117367A JP11736783A JPH034145B2 JP H034145 B2 JPH034145 B2 JP H034145B2 JP 58117367 A JP58117367 A JP 58117367A JP 11736783 A JP11736783 A JP 11736783A JP H034145 B2 JPH034145 B2 JP H034145B2
- Authority
- JP
- Japan
- Prior art keywords
- line
- control
- signal
- control unit
- section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005540 biological transmission Effects 0.000 claims description 23
- 230000008054 signal transmission Effects 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 3
- 102100031699 Choline transporter-like protein 1 Human genes 0.000 description 9
- 101000940912 Homo sapiens Choline transporter-like protein 1 Proteins 0.000 description 9
- 230000001360 synchronised effect Effects 0.000 description 7
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- IORPOFJLSIHJOG-UHFFFAOYSA-N 3,7-dimethyl-1-prop-2-ynylpurine-2,6-dione Chemical compound CN1C(=O)N(CC#C)C(=O)C2=C1N=CN2C IORPOFJLSIHJOG-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000004308 accommodation Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 101150071238 tut1 gene Proteins 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は複数のデータ回線を交換制御する回線
制御装置に係り、特に二重化された回線制御部の
構成および制御を単純化・経済化する系切替方式
に関す。[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a line control device for switching and controlling a plurality of data lines, and in particular to a system for simplifying and economicalizing the configuration and control of a duplex line control unit. Regarding the switching method.
(b) 従来技術と問題点
第１図はこの種回線制御装置における従来ある
系切替方式の一例を示す図である。第１図におい
て、回線制御装置は主制御部CCと、二重化され
た回線制御部CCU０およみびCCU１と、回線終
端部CTUとを具備している。各回線制御部CCU
０およびCCU１は、同一周期のクロツク信号を
発生するクロツク信号発生回路CK０およびCK１
と、各クロツク信号発生回路CK０およびCK１の
発生するクロツク信号を同期化するクロツク同期
化回路SC０およびSC１と、主制御部CCから伝達
される収容回線Ｌ相互の交換制御情報を保持し、
回線終端部CTUから伝達される各回線Ｌの受信
データrdを蓄積し、該受信データrdを前記交換制
御情報に基づき各回線Ｌの送信データsdとして回
線終端部CTUに伝達する回線制御回路CTL０お
よびCTL１とを具備している。なお回線制御回
路CTL０およびCTL１は、クロツク信号発生回
路CK０またはCK１から供給されるクロツク信号
に同期して、受信データrdおよび送信データsdを
送受信する回線Ｌの各回線番号を示す回線アドレ
ス信号ad０およびad１と、送信データsdの該当
回線Ｌへの送出時期を指定する回線信号送出制御
パルスws０およびws１とを回線終端部CTUに伝
達する。回線終端部CTUは、何れの回線制御部
CCU０またはCCU１を選択するかの選択指示を
主制御部CCから設定されるレジスタRAと、レジ
スタRAに設定される選択指示により導通状態を
制御されるゲートCA０乃至CC１と、収容各回線
Ｌから到着する受信データrdを時分割多重化して
回線制御部CCU０およびCCU１に伝達するマル
チプレクサMPXと、選択された回線制御部CCU
０またはCCU１から伝達される時分割多重化さ
れた送信データsdを各回線Ｌに分配送出するデマ
ルチプレクサDMPXとを具備している。今主制
御部CCから回線終端部CTUのレジスタRAに回
線制御CCU０を選択する選択指示が設定される
と、ゲートGA０、GB０およびGC０が導通状態
となり、ゲートGA１，GB１およびGC１が阻止
状態となる。その結果マルチプレクサMPXは回
線制御部CCU０からゲートGB０を介して伝達さ
れる回線アドレス信号ad０により受信データrd
の時分割多重化を行い、またデマルチプレクサ
DMPXは回線制御部CCU０からゲートGB０を介
して伝達される回線アドレス信号ad０およびゲ
ートGA０を介して伝達される回線信号送出制御
パルスws０により送信データsdの分配送出を行
う。かかる状態で主制御部CCからレジスタRAに
設定される選択指示が回線制御部CCU０から
CCU１に切替えられると、ゲートGA１、CB１
およびGC１が導通状態となり、ゲートGA０、
GB０およびGC０が阻止状態となる。その結果マ
ルチプレクサMPXは回線制御部CCU１からゲー
トGB１を介して伝達される回線アドレス信号ad
１により受信データrdの時分割多重化を行い、ま
たデマルチプレクサDMPXは回線制御部CCU１
からゲートGB１を介して伝達される回線アドレ
ス信号ad１およびゲートGA１を介して伝達され
る回線信号送出制御パルスws１により送信デー
タsdの分配送出を行う。この時回線制御部CCU
０から伝達される回線アドレス信号ad０と、回
線制御部CCU１から伝達される回線アドレス信
号ad１とが同期化されていないと、切替以前に
回線アドレス信号ad０により時分割多重化した
受信データrdが回線制御部CCU１内においては
回線アドレス信号ad１に対応して回線制御回路
CTL１に蓄積される為、切替以後各回線Ｌに誤
つた送信データsdが送出されることとなる。また
回線制御部CCU０から伝達される回線信号送出
制御パルスws０と、回線制御部CCU１から伝達
される回線信号送出制御パルスws１とが同期化
されていないと、各回線Ｌに対する送信データsd
の送出時期が変動し、歪を発生する原因となる。
然し回線アドレス信号ad０およびad１、並びに
回線信号送出制御パルスws０およびws１は、ク
ロツク同期化回路SC０およびSC１により同期化
されたクロツク信号により動作する回線制御回路
CTL０およびCTL１により生成される為、何れ
も完全に同期化されており、回線終端部CTUが
回線制御部CCU０からCCU１へ選択を切替えた
場合にも、前述の如き送信データsdの誤りが発生
することは無い。(b) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional system switching system in this type of line control device. In FIG. 1, the line control device includes a main control unit CC, duplicated line control units CCU0 and CCU1, and a line termination unit CTU. Each line control unit CCU
0 and CCU1 are clock signal generation circuits CK0 and CK1 that generate clock signals with the same period.
, clock synchronization circuits SC0 and SC1 that synchronize the clock signals generated by the clock signal generation circuits CK0 and CK1, and the accommodation line L transmitted from the main control section CC,
A line control circuit CTL0 that accumulates received data rd of each line L transmitted from the line termination unit CTU and transmits the received data rd to the line termination unit CTU as transmission data sd of each line L based on the exchange control information; It is equipped with CTL1. The line control circuits CTL0 and CTL1, in synchronization with the clock signal supplied from the clock signal generation circuit CK0 or CK1, generate line address signals ad0 and line address signals indicating the respective line numbers of the lines L that transmit and receive receive data rd and send data sd. ad1 and line signal sending control pulses ws0 and ws1 that specify the timing of sending the transmission data sd to the corresponding line L are transmitted to the line termination unit CTU. The line termination unit CTU is either line control unit.
A selection instruction to select CCU0 or CCU1 is received from the register RA set by the main control unit CC, the gates CA0 to CC1 whose conduction states are controlled by the selection instruction set in the register RA, and each accommodated line L. A multiplexer MPX time-division multiplexes the received data rd to be transmitted to the line control units CCU0 and CCU1, and a selected line control unit CCU.
0 or CCU1, and a demultiplexer DMPX that distributes the time-division multiplexed transmission data sd transmitted from CCU1 to each line L. Now, when a selection instruction to select line control CCU0 is set from the main control unit CC to the register RA of the line termination unit CTU, gates GA0, GB0, and GC0 become conductive, and gates GA1, GB1, and GC1 become blocked. . As a result, the multiplexer MPX receives the received data rd by the line address signal ad0 transmitted from the line control unit CCU0 via the gate GB0.
Performs time division multiplexing and demultiplexing
DMPX delivers the transmission data sd in accordance with the line address signal ad0 transmitted from the line control unit CCU0 via the gate GB0 and the line signal transmission control pulse ws0 transmitted via the gate GA0. In this state, the selection instruction set in the register RA from the main control unit CC is sent from the line control unit CCU0.
When switched to CCU1, gates GA1 and CB1
and GC1 become conductive, gates GA0,
GB0 and GC0 become blocked. As a result, the multiplexer MPX receives the line address signal ad transmitted from the line control unit CCU1 via the gate GB1.
1 performs time division multiplexing of the received data rd, and the demultiplexer DMPX is connected to the line control unit CCU1.
The transmission data sd is distributed in accordance with the line address signal ad1 transmitted from the terminal via the gate GB1 and the line signal transmission control pulse ws1 transmitted via the gate GA1. At this time, the line control unit CCU
If the line address signal ad0 transmitted from CCU1 and the line address signal ad1 transmitted from the line control unit CCU1 are not synchronized, the received data rd time-division multiplexed by the line address signal ad0 before switching will be sent to the line. In the control unit CCU1, a line control circuit is activated in response to the line address signal ad1.
Since the data is accumulated in CTL1, erroneous transmission data sd will be sent to each line L after switching. Furthermore, if the line signal transmission control pulse ws0 transmitted from the line control unit CCU0 and the line signal transmission control pulse ws1 transmitted from the line control unit CCU1 are not synchronized, the transmission data sd for each line L
The sending timing of the signal changes, causing distortion.
However, line address signals ad0 and ad1 and line signal sending control pulses ws0 and ws1 are generated by a line control circuit operated by clock signals synchronized by clock synchronization circuits SC0 and SC1.
Since they are generated by CTL0 and CTL1, they are completely synchronized, and even if the line termination unit CTU switches the selection from line control unit CCU0 to CCU1, errors in the transmission data sd as described above will occur. There's nothing wrong with that.
以上の説明から明らかな如く、従来ある系切替
方式においては、回線終端部CTUが主制御部CC
からの選択指示に基づき回線制御部CCU０およ
びCCU１を切替えた場合に、収容各回線Ｌに対
する送信データsdおよび受信データrdの送受信動
作に支障を来さぬ為に、両回線制御部CCU０お
よびCCU１が使用するクロツク信号を完全に同
期化し、更に回線アドレス信号ad０およびad１、
並びに回線信号送出制御パルスws０およびws１
の同期化を図らねばならず、その為にクロツク同
期化回路SC０およびSC１を設ける等、構成およ
び制御が複雑化する欠点があつた。 As is clear from the above explanation, in conventional system switching systems, the line termination section CTU is the main control section CC
When the line control units CCU0 and CCU1 are switched based on the selection instruction from The clock signals used are completely synchronized, and the line address signals ad0 and ad1,
and line signal transmission control pulses ws0 and ws1
For this purpose, clock synchronization circuits SC0 and SC1 must be provided, which has the disadvantage of complicating the configuration and control.
(c) 発明の目的
本発明の目的は、前述の如き従来ある系切替方
式の欠点を除去し、二重化された各回線制御部の
クロツク信号を同期せなくとも、回線制御部の切
替えに際して支障を来さぬ手段を実現することに
在る。(c) Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional system switching system as described above, and to eliminate any hindrance when switching line control units without synchronizing the clock signals of each duplexed line control unit. It lies in realizing the means that will not come.
(d) 発明の構成
この目的は本発明により主制御部、２個の回線
制御部及び回線終端部より構成され、回線制御部
は主制御部から伝達される収容回線相互の交換制
御情報を保持し、回線終端部よりの時分割多重化
された受信データ信号を蓄積、再生し送信データ
信号とし、該データ信号と回線を指定する回線ア
ドレス信号及び回線への送出時期を指定する回線
信号送出制御パルスとを含む信号を回線終端部に
送出し、回線終端部は２個の回線制御部よりの信
号のいづれかを主制御部よりの選択指示により選
択し、回線アドレス信号と回線信号送出制御パル
スによつて送信データを回線に分配送出する如き
回線制御装置において、各回線制御部には回線信
号送出制御パルスの送出と停止を制御する制御手
段が設けられ、該制御手段は回線制御部の切替え
の際、主制御部より制御されて回線終端部への回
線信号送出制御パルスの送出を停止し、回線終端
部が主制御部よりの選択指示によつて回線制御部
よりの信号の切替後、主制御部より制御されて、
送出を再開することを特徴とする系切替方式によ
つて達成される。(d) Structure of the Invention The object of the present invention is to provide a main control unit, two line control units, and a line termination unit, and the line control unit holds mutual exchange control information of accommodated lines transmitted from the main control unit. The time-division multiplexed received data signal from the line termination section is stored and reproduced as a transmission data signal, and the data signal, a line address signal that specifies the line, and line signal transmission control that specifies the transmission timing to the line. The line terminal selects one of the signals from the two line control units according to a selection instruction from the main control unit, and sends a signal containing a line address signal and a line signal sending control pulse to the line termination unit. Therefore, in a line control device that distributes transmission data to lines, each line control section is provided with a control means for controlling sending and stopping of line signal sending control pulses, and the control means controls the switching of the line control section. At this time, the main control section stops sending the line signal sending control pulse to the line termination section, and the line termination section switches the signal from the line control section according to the selection instruction from the main control section, and then Controlled by the control unit,
This is achieved by a system switching method characterized by restarting transmission.
(e) 発明の実施例
以下、本発明の一実施例を図面により説明す
る。第２図は本発明の一実施例による系切替方式
を示す図である。なお、全図を通じて同一符号は
同一対象物を示す。第２図においては、回線信号
送出制御パルスws０およびws１の回線終端部
CTUへの伝達を主制御部CCからの送出指示およ
び停止指示により制御する手段として、レジスタ
RB０およびゲートGD０と、レジスタRB１およ
びゲートGD１とがそれぞれ各回線制御部CCU０
およびCCU１に設けられている。また各回線制
御部CCU０およびCCU１の使用するクロツク信
号はクロツク信号発生回路CK０およびCK１から
それぞれ独立に供給され、両クロツク信号を同期
化する手段（第１図におけるクロツク同期化回路
SC０およびSC１）は設けられていない。その結
果回線制御部CCU０の回線制御回路CTL０から
送出される回線アドレス信号ad０および回線信
号送出制御パルスws０と、回線制御部CCU１の
回線制御回路CTL１から送出される回線アドレ
ス信号ad１および回線信号送出制御パルスws１
とは互いに同期化されていない。今主制御部CC
から各回線制御部CCU０およびCCU１のレジス
タRB０およびRB１に回線信号送出制御パルス
ws０およびws１の送出指示が設定されると、ゲ
ートGD０およびGD１は導通状態となり、各回
線制御回路CTL０およびCTL１の発生する回線
信号送出制御パルスws０およびws１は回線終端
部CTUに伝達される。かかる状態で主制御部CC
が回線終端部CTUのレジスタRAに回線制御
CCU０の選択指示を設定すると、ゲートGA０、
GB０およびGC０が導通状態となり、ゲートGA
１，GB１およびGC１が阻止状態となる。その結
果マルチプレクサMPXは回線制御部CCU０から
ゲートGB０を介して伝達される回線アドレス信
号ad０により受信データrdの時分割多重化を行
い、またデマルチプレクサDMPXは回線制御部
CCU０からゲートGB０を介して伝達される回線
アドレス信号ad０およびゲートGA０を介して伝
達される回線信号送出制御パルスws０により送
信データsdの分配送出を行う。なお回線制御部
CCU１内の回線制御回路CTLにおいては、受信
データrdは回線アドレス信号ad０とad１とが同
期化されぬことにより、正しく回線Ｌに対応して
蓄積されていない。かかる状態で主制御部CCが
回線終端部CTUに回線制御部CCU０からCCU１
に選択切替を試みる場合には、最初に回線制御部
CCU０およびCCU１のレジスタRB０およびRB
１に回線信号送出制御パルスws０およびws１の
停止指示を設定する。その結果ゲートGD０およ
びGD１は共に阻止状態となり、各回線制御回路
CTL０およびCTL１から回線終端部CTUに回線
信号送出制御パルスws０およびws１が伝達され
なくなる。回線終端部CTUにおいては、デマル
チプレクサDMPXがゲートGA０を介して供給さ
れていた回線信号送出制御パルスws０が停止す
る為、各回線Ｌに対する送信データsdの送出を停
止する。次に主制御部CCは、回線終端部CTUの
レジスタRAに設定されている回線制御部CCU０
の選択指示を回線制御部CCU１の選択指示に切
替える。その結果回線終端部CTUのゲートGA
１，GB１およびGC１が導通状態となり、ゲート
GA０、GB０およびGC０が阻止状態となり、マ
ルチプレクサMPXは回線制御部CCU１からゲー
トGB１を介して伝達される回線アドレス信号ad
１により受信データrdの時分割多重化を行う。従
つて回線制御部CCU１内の回線制御回路CTLに
は、回線アドレス信号ad１が全回線Ｌを一巡す
る間、即ちマルチプレクサで全部の回線の時分割
サンプリングを１回行なつている間に、受信デー
タrdが正しく回線Ｌに対応して蓄積される。主制
御部CCが回線アドレス信号ad１が一巡した後に、
回線制御部CCU０およびCCU１のレジスタRB０
およびRB１に回線信号送出制御パルスws０およ
びws１の送出指示を設定すると、ゲートGD０お
よびGD１は再び導通状態となり、各回線制御回
路CTL０およびCTL１の発生する回線信号送出
制御パルスws０およびws１は回線終端部CTUに
伝達される。その結果デマルチプレクサDMPX
は回線制御部CCU１からゲートGB１を介して伝
達される回線アドレス信号ad１およびゲートGA
１を介して伝達される回線信号送出制御パルス
ws１により送信データsdの分配送出を行い、回
線制御部CCU０とCCU１との切替えは完了する。
なお回線信号送出制御パルスws０およびws１の
停止期間は、回線アドレス信号ad１の一巡する
期間に略等しいが、該期間は送信データsdの単位
時間長に比し無視可能な短時間である為、回線信
号送出制御パルスws０およびws１の停止により
送信データsdに与える歪は無視可能である。(e) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a system switching system according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In Fig. 2, the line signal transmission control pulses ws0 and ws1 are shown at the line terminals.
Register
RB0 and gate GD0 and register RB1 and gate GD1 are respectively connected to each line control unit CCU0.
and is provided in CCU1. In addition, the clock signals used by each line control unit CCU0 and CCU1 are independently supplied from the clock signal generation circuits CK0 and CK1, respectively, and the means for synchronizing both clock signals (the clock synchronization circuit in FIG.
SC0 and SC1) are not provided. As a result, the line address signal ad0 and line signal sending control pulse ws0 sent from the line control circuit CTL0 of the line control unit CCU0, and the line address signal ad1 and line signal sending control pulse sent from the line control circuit CTL1 of the line control unit CCU1. pulse ws1
are not synchronized with each other. Now main control part CC
Line signal transmission control pulses are sent from registers RB0 and RB1 of each line control unit CCU0 and CCU1.
When the transmission instructions for ws0 and ws1 are set, gates GD0 and GD1 become conductive, and line signal transmission control pulses ws0 and ws1 generated by each line control circuit CTL0 and CTL1 are transmitted to the line termination unit CTU. In this state, the main control unit CC
is the line control register in the line termination section CTU's register RA.
When the selection instruction for CCU0 is set, gate GA0,
GB0 and GC0 become conductive, and gate GA
1, GB1 and GC1 are in a blocking state. As a result, the multiplexer MPX time-division multiplexes the received data rd using the line address signal ad0 transmitted from the line control unit CCU0 via the gate GB0, and the demultiplexer DMPX performs time division multiplexing on the received data rd.
The transmission data sd is delivered by a line address signal ad0 transmitted from CCU0 via gate GB0 and a line signal transmission control pulse ws0 transmitted via gate GA0. Note that the line control section
In the line control circuit CTL in the CCU 1, the received data rd is not stored correctly corresponding to the line L because the line address signals ad0 and ad1 are not synchronized. In this state, the main control unit CC switches the line terminal unit CTU from line control unit CCU0 to CCU1.
When attempting to switch selection to
Registers RB0 and RB of CCU0 and CCU1
1 to instruct to stop the line signal transmission control pulses ws0 and ws1. As a result, gates GD0 and GD1 are both blocked, and each line control circuit
The line signal transmission control pulses ws0 and ws1 are no longer transmitted from CTL0 and CTL1 to the line termination unit CTU. In the line termination unit CTU, the demultiplexer DMPX stops sending out the transmission data sd to each line L because the line signal sending control pulse ws0 that was being supplied via the gate GA0 is stopped. Next, the main control unit CC executes the line control unit CCU0 set in the register RA of the line termination unit CTU.
The selection instruction is switched to the selection instruction of the line control unit CCU1. As a result, the gate GA of the line termination CTU
1, GB1 and GC1 become conductive, gate
GA0, GB0 and GC0 are in the blocking state, and the multiplexer MPX receives the line address signal ad transmitted from the line control unit CCU1 via the gate GB1.
1, the received data rd is time-division multiplexed. Therefore, the line control circuit CTL in the line control unit CCU1 receives the received data while the line address signal ad1 goes around all the lines L, that is, while the multiplexer performs time-division sampling of all the lines once. rd is stored correctly corresponding to line L. After the main control unit CC has completed one cycle of the line address signal ad1,
Register RB0 of line control units CCU0 and CCU1
When an instruction to send line signal sending control pulses ws0 and ws1 is set to RB1 and RB1, gates GD0 and GD1 become conductive again, and line signal sending control pulses ws0 and ws1 generated by each line control circuit CTL0 and CTL1 are transmitted to the line terminal. Communicated to CTU. The resulting demultiplexer DMPX
are line address signal ad1 and gate GA transmitted from line control unit CCU1 via gate GB1.
Line signaling control pulse transmitted via 1
The transmission data sd is delivered by ws1, and the switching between the line control units CCU0 and CCU1 is completed.
Note that the stop period of the line signal transmission control pulses ws0 and ws1 is approximately equal to the period of one cycle of the line address signal ad1, but since this period is a negligible short time compared to the unit time length of the transmission data sd, Distortion caused to the transmission data sd by stopping the signal transmission control pulses ws0 and ws1 is negligible.
以上の説明から明らかな如く、本実施例によれ
ば、回線制御部CCU０およびCCU１を切替える
場合に、送信データsdに影響を与えぬ程度回線信
号送出制御パルスws０およびws１を停止させる
ことにより、回線制御部CCU０およびCCU１の
クロツク信号を同期化させる必要がなくなる。 As is clear from the above description, according to the present embodiment, when switching the line control units CCU0 and CCU1, the line signal transmission control pulses ws0 and ws1 are stopped to an extent that does not affect the transmission data sd. There is no need to synchronize the clock signals of the control units CCU0 and CCU1.
なお、第２図はあく迄本発明の一実施例に過ぎ
ず、例えば回線制御部CCU０およびCCU１、或
いは回線終端部CTUの構成は図示されるものに
限定されることは無く、他に幾多の変形が考慮さ
れるが、何れの場合にも本発明の効果は変らな
い。 Note that FIG. 2 is only one embodiment of the present invention, and the configuration of the line control units CCU0 and CCU1 or the line termination unit CTU is not limited to what is shown in the figure, and there may be many other configurations. Although variations are considered, the effects of the present invention do not change in any case.
(f) 発明の効果
以上、本発明によれば、前記回線制御装置にお
いて、二重化された各回線制御部のクロツク信号
を同期させなくとも、支障無く回線制御部の切替
えが実施可能となり、当該回線制御装置の構成お
よび制御の単純化、並びに経済化が向上する。(f) Effects of the Invention As described above, according to the present invention, in the line control device, it is possible to switch the line control units without any trouble without synchronizing the clock signals of each duplexed line control unit, and the line control unit can be switched without any trouble. The structure and control of the control device can be simplified and made more economical.
第１図は従来ある系切替方式の一例を示す図、
第２図は本発明の一実施例による系切替方式を示
す図である。
図において、ad０およびad１は回線アドレス
信号、CCは主制御部、CCU０およびCCU１は回
線制御部、CK０およびCK１はクロツク信号発生
回路、CTL０およびCTL１は回線制御回路、
CTUは回線終端部、DMPXはデマルチプレク
サ、GA０乃至GD１はゲート、Ｌは回線、MPX
はマルチプレクサ、RA、RB０およびRB１はレ
ジスタ、rdは受信データ、SC０およびSC１はク
ロツク同期化回路、sdは送信データ、ws０およ
びws１は回線信号送出制御パルス、を示す。
Figure 1 is a diagram showing an example of a conventional system switching system.
FIG. 2 is a diagram showing a system switching system according to an embodiment of the present invention. In the figure, ad0 and ad1 are line address signals, CC is a main control unit, CCU0 and CCU1 are line control units, CK0 and CK1 are clock signal generation circuits, CTL0 and CTL1 are line control circuits,
CTU is line termination, DMPX is demultiplexer, GA0 to GD1 are gates, L is line, MPX
is a multiplexer, RA, RB0 and RB1 are registers, rd is received data, SC0 and SC1 are clock synchronization circuits, sd is transmitted data, and ws0 and ws1 are line signal sending control pulses.
Claims (1)
より構成され、回線制御部は主制御部から伝達さ
れる収容回線相互の交換制御情報を保持し、回線
終端部よりの時分割多重化された受信データ信号
を蓄積、再生し送信データ信号とし、該データ信
号と回線を指定する回線アドレス信号及び回線へ
の送出時期を指定する回線信号送出制御パルスと
を含む信号を回線終端部に送出し、回線終端部は
２個の回線制御部よりの信号のいづれかを主制御
部よりの選択指示により選択し、回線アドレス信
号と回線信号送出制御パルスによつて送信データ
を回線に分配送出する如き回線制御装置におい
て、各回線制御部には回線信号送出制御パルスの
送出と停止を制御する制御手段が設けられ、該制
御手段は回線制御部の切替えの際、主制御部より
制御されて回線終端部への回線信号送出制御パル
スの送出を停止し、回線終端部が主制御部よりの
選択指示によつて回線制御部よりの信号の切替
後、主制御部より制御されて、送出を再開するこ
とを特徴とする系切替方式。1 Consists of a main control unit, two line control units, and a line termination unit.The line control unit holds mutual exchange control information for accommodated lines transmitted from the main control unit, and performs time division multiplexing from the line termination unit. The received data signal is stored and reproduced as a transmission data signal, and a signal containing the data signal, a line address signal that specifies the line, and a line signal transmission control pulse that specifies the timing of transmission to the line is sent to the line termination section. However, the line termination section selects one of the signals from the two line control sections according to a selection instruction from the main control section, and sends the transmission data to the line in parts according to the line address signal and the line signal transmission control pulse. In the line control device, each line control unit is provided with a control means for controlling sending and stopping of line signal sending control pulses, and when switching the line control unit, the control means is controlled by the main control unit to terminate the line. After the line terminal section switches the signal from the line control section in response to a selection instruction from the main control section, the line terminal section resumes transmission under the control of the main control section. A system switching method characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58117367A JPS6010830A (en) | 1983-06-29 | 1983-06-29 | System switching system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58117367A JPS6010830A (en) | 1983-06-29 | 1983-06-29 | System switching system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6010830A JPS6010830A (en) | 1985-01-21 |
| JPH034145B2 true JPH034145B2 (en) | 1991-01-22 |
Family
ID=14709905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58117367A Granted JPS6010830A (en) | 1983-06-29 | 1983-06-29 | System switching system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6010830A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559520A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Output switching system for processor duplication system |
| JPS57105016A (en) * | 1980-12-22 | 1982-06-30 | Nec Corp | Clock source switching system |
| JPS57111715A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Clock switching system |
-
1983
- 1983-06-29 JP JP58117367A patent/JPS6010830A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5559520A (en) * | 1978-10-27 | 1980-05-06 | Hitachi Ltd | Output switching system for processor duplication system |
| JPS57105016A (en) * | 1980-12-22 | 1982-06-30 | Nec Corp | Clock source switching system |
| JPS57111715A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Clock switching system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6010830A (en) | 1985-01-21 |
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