JPH0340533A - Demodulation circuit - Google Patents

Abstract

PURPOSE:To demodulate a reception signal with high linearity by setting up the gate width of a field effect transistor(FET) constituting the source follower circuit of the final stage so that an output impedance is set up smaller than the impedance of a load circuit connected to the source follower circuit. CONSTITUTION:The FET Q12 constituting the source follower circuit of the final stage goes to the load of a source follower circuit based upon FET Q11, and since the input impedance of the FET Q12 is high impedance, the load of the FET Q11 goes to high impedance and the voltage gain of the FET Q11 is almost '1'. Since the gate width of the FET Q12 is set up so as to be smaller than the impedance of the load circuit connected to an output terminal 12, the load impedance of the FET Q12 is also increased and the voltage gain of the FET Q12 goes to almost '1'. Thereby, signal amplitude inputted to respective source follower circuits is reduced. Thus, a reception signal can be demodulated with high linearity.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a demodulation circuit that demodulates a received signal with extremely high linearity. [Prior Art] Conventionally, as this type of demodulation circuit, for example, TRANSACTIONS ON ELECTI? published by Institute of Electrical and Electronics Engineers (IEEE) is available.
ON DEVICE, VOL, ED-28°NO,
2, FEBRUARY 1981), and this circuit is shown in FIG. The field effect transistor (FET) Ql has a drain connected to the FET Q2 as a load, and a source grounded. In addition, FETQ3° diodes D1 to D4. FET
Q4 constitutes a source follower circuit, and is formed to have an output impedance of 50 [Ω]. In addition, +5 [
A positive R voltage vDD of [V] is given, and FETQ4
A negative power supply voltage v33 of -4 [V] is applied to the source. When the optical signal is received, it is converted into an electrical signal and sent to the FETQ.
The gate voltage is applied to I as the gate voltage, and the drain current Idl is converted. This drain current 1d flows through FETQ2 as a negative (ai), and a voltage is generated at the drain of FETQI. This voltage is applied to the gate of FETQ3, FETQ3 is turned on, and drain current 1d also flows through FETQ3. This drain current 1d is applied to each diode D1 to D.
4, a predetermined voltage is generated at the drain of FETQ4, and is output. There is also a light receiving polarization circuit shown in FIG. tiv is provided to the light receiving element 1, and the optical signal received by this is converted into a voltage signal by a resistor R1. The DC component of this voltage signal is removed by the capacitor C1, and 1j is applied to the gate of the FET Q5. FETQ
A predetermined voltage is applied to the gate 5 by a resistor R2R3, and the voltage signal from which the DC component is removed is applied to the FETQ
The impedance is converted by a source follower circuit constituted by R5 and resistor R4. Then, the impedance-converted voltage signal is output from the source of FETQ5. [Three Problems to be Solved by the Invention] However, in the conventional separate path shown in FIG. 11 above, when strong light No. 15 is received, the amplitude of the signal manually input to the circuit becomes large. For this reason, there is a problem in that the distortion generated in the demodulated signal increases and the linearity of the demodulated signal deteriorates. This problem becomes an important problem in a system where it is necessary to perform 1si tuning of an analog signal, which is a received signal, with extremely high linearity. The reasons for poor linearity are considered as follows. That is, the characteristics of gate voltage V vs. drain current (4), which is the input/output characteristic of the FET, are expressed as the following equation, where drain current s2d is expressed as a quadratic function of gate voltage VgS. Here, the threshold voltage of the FET is V
Let K be the proportionality constant th', which is a measure of current drive capability. 2 ... (1>! -K (Vg, -Vth) Therefore, when the received signal S given to the FET as the gate voltage V increases, the drain current I of this FET changes nonlinearly and the demodulated signal In addition, in the conventional circuit shown in FIG. 12 above, by appropriately selecting the resistors R2 and R3,
The advantage is that the gate voltage can be freely selected. but,
On the other hand, its gate voltage fluctuates due to manufacturing variations in the threshold voltage and transfer conductance g of FETQ5, as well as fluctuations in the supplied power supply voltage (DD). Therefore, the demodulated signal is not stabilized and its linearity becomes increasingly worse. [Means for Solving the Problems] The present invention has been made to solve these three problems, and includes a plurality of source follower circuits for impedance conversion of received signals on the same semiconductor substrate, and the first stage FET is a gate A received signal is applied to the gate, a resistor having a high resistance value is connected between the gate and the source, and a resistor is connected to the source. In addition, 1. Each FET connected to the next stage has its gate connected to the source of the previous stage FET,
The source is connected to the gate of the next stage FET and is also connected to a resistor. Furthermore, each FE from the second stage onward
The product of the gate width of T and the resistance value of the resistor connected to its source is set equal to the product of the gate radiation of the first stage FET and the resistance value of the resistor connected to its source, and , the gate width of the final stage FET is set so that the output impedance is smaller than the impedance of the load circuit. [Operation] Since the resistance value of the resistor connected between the gate and source of the first stage FET is large, the gate potential and source potential of the first stage FET are almost equal, and this gate-source voltage is approximately 0 [V] become. Also, since the product of the gate width of the FET in all stages and the resistance value of the resistor connected to its source is equal, the product of the drain current of the FET in all stages and the resistance value of the resistor connected to its source is The source potentials of all stages become equal to each other. Moreover, each stage of FE
The source potential of T is equal to the gate potential of the next stage FET. Therefore, the source potential and gate potential of the FETs in each stage become equal, and the gate-source voltage of the FETs in each stage becomes approximately 0 [V]. Furthermore, a source follower circuit with high human impedance is connected as a load for each stage of FET. Furthermore, since the output impedance is smaller than the impedance of the load circuit, the load of the final stage FET also has high impedance. Therefore, the electrical gain of each stage of FET is approximately 1.
The amplitude of the signal output from the source of the FET in each stage is small and uneven, and this small amplitude signal is applied to the gate of the FET in each stage. In addition, since each element is formed on the same semiconductor substrate,
Manufacturing variations in each element are reflected in the light at the same ratio. Therefore, the product of the gate width of the FET in each stage and the resistance value of the resistor connected to its source is the same for each source follower circuit even if there are manufacturing variations. Moreover, this product is not affected by R voltage fluctuations. [Embodiment] Next, a case will be described in which the present invention is applied to an optical receiving circuit of an optical CATV system used for Hatake quality television broadcasting service. FIG. 1 is a circuit diagram showing the configuration of one embodiment of this optical receiving circuit, which is formed on the same semiconductor substrate. The cathode of the PIN photodiode 11 is 'fli [pressure V
I to B! i'+ is raised, and the anode is connected to the other end of a resistor R11 whose one end is grounded. Further, this anode is connected via a capacitor C1,1 to the gate of FETQII that constitutes the first stage source follower circuit. A resistor R12 having a high resistance value is connected between the gate and source of FETQII. Also,
The drain of FETQII is the bypass capacitor C12.
is raised to the connected power supply voltage VDD, and its source is grounded via a resistor R13. In addition, this source is a FET that constitutes the second stage source follower circuit.
Connected to the gate of Q12. Like FETQII, this FETQ12 also has its drain connected to the power supply voltage VDD.
The source is grounded through a resistor R14. This source is then connected to the output terminal 12 of the circuit. The resistance value of the resistor R11 is set to about 1 [KΩ]. This is to satisfy the "desirable performance" stipulated by the Cable Television Broadcasting Act. In other words, under this law, 40 channels of video signals are
When transmitted over a distance of ml, carrier signal power vs. fp
It is required that the C/N, which is the power ratio, be 45 dB or more. When changing the resistance value of resistor R11, transmission distance ill [Kml (I axis) and C/N [dB]
(vertical axis) is expressed in the graph of FIG. A curve 13 shows the relationship when the resistance value of the resistor R11 is 300 [Ω], and a curve 14 shows the relationship when the resistance value is 1 [KΩ]. When the resistance value is 300 [Ω], the transmission distance is 10 [Kml] and the C/N is about 45 dB. resistance value is 1
In the case of [KΩ], 10[Kml is approximately 47dB, 15
[About 45 dB in Kml. Therefore, the resistor R11 is required to have a resistance value of 1 [KΩ] or more. The capacitance value of the capacitor C1l is set to 30 [pF] or more. Capacitor C1l suppresses fluctuations in the gate voltage of FETQII when the strength of the received signal is large.
It is a LII flow cutoff capacitor, and 2! This maintains the linearity of the J signal. In addition, in optical CATV systems, upstream signals from the handset side to the base side are transmitted in the low frequency band, so the low cutoff frequency is 5 [MHz].
] Must be less than or equal to For this purpose, the above chain is required as the capacitance of the capacitor C1l. The resistance value of the resistor R12 should just be a sufficiently large value compared to the respective resistance values of the resistors R11 and R13, and is usually 100[K].
Ω] is set to the degree of kneading. Therefore, almost no current flows between the gate and source of FETQII, and the gate potential and source potential become approximately equal. Therefore, F
The gate-source voltage V of ETQII is almost 0

[v]
become. In addition, the resistance value 13 of the resistor R13 is set so that the drain-source voltage of this FETQII is approximately 1/2 of the drain breakdown voltage at the operating point of the FETQII. ” 14 is FETQ
The product of I2 and gate width 0w2 is the resistance value of resistor R13'
13 and the gate width Gvl of FETQII, that is, it is set so as to satisfy the following equation. ' ” (``!3×Gwl)/Gv2...
(2)4 Since the drain current I is proportional to the gate width, if the resistor tnr14 is set as shown in equation (2), the source potentials of FETQII and FETQI2 become equal. Also,
- The gate potential of FETQI2 is equal to the source potential of FETQII, and the source potential of this FETQll is equal to the source potential of FETQII.
I is equal to the gate potential of 1. Therefore, the gate potential and source potential of FETQI2 become equal to the gate potential and source potential of FETQII. As a result, FET
The gate-source voltage V of QI2 also becomes approximately 0 [v]s. Furthermore, FETQI2 serves as a load for the source follower circuit formed by FETQll, and the input impedance of FETQI2 is high impedance. For this reason, FE
The TQII load becomes high impedance, and the FETQ
The voltage gain A of II becomes approximately 1. In other words, FETQI
If the load impedance of I is RL, FETQll
The voltage gain A of is expressed by the following equation. A - [g (r 13/ J, > ] / section [1+ (r13/RL) (g, +g,)]... (
3) Here, g 5 gd represents the transfer conductance and drain conductance of FETQII, and the symbol "l" represents the combined resistance value when the respective resistances before and after the symbol are connected in parallel. Normally, the value of A is 1 or less (A<1), but as can be understood from the above equation, the larger the value of (r13j'RL), that is, the larger the value of the load impedance RL of F, ETQII, Voltage gain A of FETQII
approaches 1. In the case of this embodiment, since impedance RL is the human input impedance of FETQI2, this value is sufficiently large, and the voltage gain A of FETQII is approximately 1. In addition, FETQ, which constitutes the final stage source follower circuit,
The gate width Gv2 of I2 is set so as to satisfy the above equation (2) and to be smaller than the impedance of the negative voltage circuit connected to the output terminal 12. usually,
In the optical CATVA system, an amplifier having an output impedance of 50 to 75 [Ω] is used, and it is considered that such an amplifier is also connected to the load of this circuit. Therefore, the gate width of FETQI2 is set so that the output impedance is 25 [Ω] or less. Therefore, the load impedance of FET QI2 also becomes high, and the impedance R in the above equation (3) becomes large. As a result, the voltage gain A of FETQI2 is also approximately 1°.
become. Therefore, the voltage gain A of each source follower circuit is
is approximately 1, and since the load impedance of each source follower circuit is high, the amplitude of the fj signal input to each source follower circuit becomes small. As mentioned above, each gate-source voltage V of FETQIN and FETQI2 is 0

[v] becomes s, and the amplitude of the signal applied to the gate becomes small. Therefore, according to the circuit according to this implementation column,
It becomes possible to demodulate the received signal with extremely high linearity. This can be explained in two ways as follows. Generally, the gate-source voltage vg of an FET. The above-mentioned equation (1) 1/2 relationship between and drain current l is expressed by a linear equation, and (l ) changes linearly with respect to changes in 7g8, that is, 1 /2 It should be. However, in reality, (I) and vg
The relationship with s is as shown in the graph of FIG. 3, and does not change linearly over the entire range. This is due to the subthreshold current near the threshold voltage vth of the FET, so the gate-source voltage vg. Even if it reduces the drain current! This is because 6 continues to flow without disappearing. Furthermore, in the range s where the voltage V is large, the Schottky forward current due to the Schottky characteristic between the gate and source flows from the gate to the source, and most of the voltage V is spent in the gate parasitic resistance Rgs and the source parasitic resistance R. be. Therefore, even if the gate-source voltage V s is increased, the drain current I no longer increases linearly. Therefore, in order to reduce the distortion of the demodulated signal, it is necessary to use a W''C'FET in the range of voltage vg where the relationship between (1) and vg changes linearly. According to this embodiment, as described above, the FETQ
The gate-source voltage vg of each FET QI, ()12 is set to approximately 0 [V], and the amplitude of the signal applied to each gate is small. Q12 is the drain current (!) and the gate-source voltage g,
This means that it is used in a voltage range W in which the relationship between In addition, in order to reduce the distortion of the demodulated signal, each FET
Q11. Is there a manufacturing variation in each gate-source voltage V in Q12? It is also necessary that it not be affected by variations in t[voltage VI)D, etc. The repurchase according to this embodiment is not affected by these factors, and this can be explained as follows. Since each element of this circuit is formed within the same chip, even if there is variation in manufacturing, the ratio of variation for each element will be the same. Considering the relationship between the resistors R13 and R14, and the FETQII and FETQI2, even if the absolute chain of each resistance wire and the device parameters of each FET vary, the rate of change thereof is the same. Therefore, no matter how many parameters vary,
Furthermore, the following relationship also holds true for fluctuations in the ¥i source voltage vDD. '13" 14- Cw2/Gwl '
...(4) Therefore, the resistance FIL r of the above-mentioned resistor R14
The relationship expressed by equation (2) representing xi always holds true regardless of the influence of various parameters. In addition, the voltage gain A described above is shown (
Also in equation 3), the chain of input impedance RL of FET QI2 is sufficiently large, so the voltage gain A is maintained at approximately 1 without being influenced by other factors shown in the open equation. Therefore, each gate-source voltage of FETQII and Q12 may vary due to manufacturing variations or electric current. Regardless of fluctuations in the R voltage vDD, it is stably maintained at approximately O[V]. Further, the fj signal given to each gate is also maintained at a small amplitude. As described above, according to this embodiment, the optical signal received by the PIN photodiode 11 is reduced with high linearity, and the transmission and reception of Anna 0715 is performed accurately. Also, the signal band received by this circuit is wide :;)
It has been used as a castle. This can be explained as follows. When a sinusoidal voltage is applied to the gate of the FET, the relationship between the gate voltage V 1 and the source voltage V 2 is shown in the graph of FIG. Note that the vertical axis is voltage. The horizontal axis indicates time. The sinusoidal waveform represented by the solid line represents the gate voltage waveform 151, and the sinusoidal waveform represented by the dotted line represents the source voltage waveform 16, and the amplitude ratio of each waveform is A. Here, when this voltage gain A approaches 1, the source voltage waveform 1
6 becomes large, and when the voltage gain A becomes 1, each waveform overlaps. Since each source follower circuit of this circuit has a voltage gain of approximately 1, the gate potential and source potential of each of FETQIl and Q12 are exclusive. Therefore, each FETQI 1. The gate voltage waveform and source voltage waveform of Q12 change at the same IU4, and their amplitudes become almost the same. Therefore, each FETQll. There is almost no voltage change in the gate-source voltage Vg8 of Q12. As a result, it becomes possible to ignore the gate capacitance ta c gs generated between the gate and source of FETQIl and Q12. Further, the signal frequency range that this circuit can receive is inversely proportional to the time constant determined by the resistor R11 and the capacitor connected in parallel with it. This parallel capacitance is the junction capacitance of the PIN photodiode 11 and the gate capacitance C of the FETQII.
It is expressed as the sum of the circuit mounting capacity and gs. As mentioned above, since the gate capacitance C can be ignored, the parallel capacitance s becomes small and the receiving band of this circuit becomes the elbow band. FIG. 5 is a graph showing the frequency characteristics of the received signal when the resistance value of the resistor R11 and the number of stages of the source follower circuit are changed. The horizontal axis is the frequency [Hzl], and the vertical axis is the signal attenuation 11 [dB ] represents. A curve 17 shows the frequency characteristics of the received signal when the source follower circuit of the first reception 1=circuit has a one-stage configuration and the resistance value of the resistor R11 is 1 [KΩ]. Curves 18, 19 and 20 show the frequency characteristics when the number of stages of the source follower circuit is two stages as in this embodiment, and the resistance value of the resistor R11 is set to 1 [KΩ].
], 800[Ω1,600[Ω]. As understood from the +j'i1 diagram, when the resistance values of the resistors R11 are equal to ICKΩ], the two-stage source follower circuit shown by curve 18 has a wider frequency band. Furthermore, even with the same two-stage configuration, the lower the resistance value, the wider the frequency band. However, as described above, in order to maintain the "desirable performance" defined by the H-line Television Broadcasting Act, the resistance value of the resistor R11 must be IUKΩ. Therefore, the circuit configuration that best matches the frequency characteristics of the received signal in consideration of various conditions is the circuit configuration according to the present embodiment shown in FIG. Next, in the circuit configuration according to this embodiment, the output obtained when a sine wave voltage is input instead of the optical signal (the result of simulating the No. 2 distortion using a 41 calculator is shown below. The circuit shown in Fig. 1) In the configuration, 1 is connected to the gate of FETQII.
A sine wave voltage of 00 [MHz] is input, and the output voltage waveform at the terminal 12 is Fourier transformed. In addition, the calculation conditions are assumed to be the following three rice species. As the calculation condition ■, the final stage F
The gate width of ETQ12 is 260 [μm] and the load resistance is 1.
8

〔Effect of the invention〕

As described above, according to the present invention, even when a signal with a large amplitude is received, almost no distortion occurs in the demodulated signal. Furthermore, distortion can be reduced without being affected by manufacturing variations, power supply voltage fluctuations, and the like. Therefore, it is possible to always demodulate the received signal with good linearity. For this reason, the present invention is particularly effective when applied to a system that requires demodulating analog and negative signals with extremely high linearity. 4. Simple Eko 1. Fig. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, and Fig. 2 shows the transmission distance and C when the resistance value of resistor R11 is changed.
Figure 3 1/2 is a graph showing the relationship between FET drain voltage 1(1) and gate-source voltage V, Figure 4 S is a graph showing the relationship between FET gate voltage waveform and source. FIG. 5 is a graph for explaining the influence of voltage gain A on the voltage waveform; FIG.
The figure shows the gate voltage waveform 2 of FETQ12, which is the result of a computer simulation when the calculation conditions are set to ■.
7 is a graph showing the relationship between 1 and the source voltage waveform 22, and FIG. 7 shows the gate voltage waveform 21 of FETQ12, which is the result of a computer simulation when the subtraction condition is set to .
Graph showing the relationship between the source voltage waveform 22 and the source voltage waveform 22. FIG.
1 is a graph showing the relationship between No. 1 and the source voltage waveform 22, FIG. 9 is a circuit diagram for explaining the magnitude of the amplitude of No. 1- output from the source of the FET, and FIG. 10 is another example of the present invention. A circuit diagram showing (d or) of the embodiment, FIG. 11 is a circuit diagram showing the first conventional (
FIG. 12 is a four-way diagram showing the second conventional configuration. DESCRIPTION OF SYMBOLS 11... PIN photodiode, 12... Output terminal, R11, R13, R14... Resistor, R12... Resistor having a high resistance value, C1l, C12... Capacitor, 1. 2...ET that constitutes a source follower circuit.

Claims (1)

[Scope of Claims] A field effect transistor comprising a plurality of source follower circuits for impedance converting a received signal on the same semiconductor substrate, and which constitutes the first stage source follower circuit, has a gate to which the received signal is applied, and a gate and a source to which the field effect transistor is connected. A resistor with a high resistance value is connected between them, and a resistor is connected to the source, and the field effect transistors constituting each of the second and subsequent source follower circuits connected to the next stage of this first stage source follower circuit are , whose gate is connected to the source of the field effect transistor that constitutes the previous stage source follower circuit,
The source is connected to the gate of the field effect transistor constituting the next stage source follower circuit and also connected to the resistor, and the source is connected to the gate width and the source of the field effect transistor constituting each source follower circuit from the second stage onwards. The product of the resistor and the resistance value of the resistor is set equal to the product of the gate width of the field effect transistor constituting the first stage source follower circuit and the resistance value of the resistor connected to its source. A demodulation circuit characterized in that a gate width of a field effect transistor constituting the circuit is set such that an output impedance is smaller than an impedance of a load circuit connected to the source follower circuit.