JPH0339945Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a pulse width adjustment circuit that can modulate the pulse width at high speed, stably, and over a wide range.

[Prior art and its problems]

Accurate measurement of high-performance circuit elements, such as VLSIs, has recently become increasingly important. Such measurements require accurately generating high-speed pulse signals and transmitting them without distortion. However, it is virtually impossible to transmit data without distortion, so methods are used to correct distortion during transmission.

The distortion correction described above is achieved by adjusting the pulse position and pulse width. The present invention was made in connection with such pulse width adjustment.
A conventional example thereof is shown in FIG.

In FIG. 2, logic ICs 102, 106, 1
09 is the gate of ECL etc., and resistor 103,1
07 and 113 are respective emitter resistances.
The original signal Vi is input from the non-inverting input terminal 101 of the IC102, and the IC102 is connected to the IC via the resistor 104.
It is input to the non-inverting input terminal 1041 of 106.
The output of IC102 becomes an input signal.

A capacitor 105 is inserted between the terminal 1041 and the ground as necessary to widen the adjustment range of the pulse width. .

The inverting input terminal voltage Vb of IC 106 provides a threshold value that determines the pulse width.

The voltage waveform at terminal 1041 is as shown in FIG. Although FIG. 3 deals with positive pulses, the same applies to negative pulses, so only positive pulses will be explained.

The voltage at terminal 1041 is at the low logic voltage level V _L
It transitions from _VH to high logic voltage level, maintains a constant peak, and then transitions again to low logic voltage level _VL .

Therefore, V _b is defined as V _b1 , V _b2 , V _b3 (however, V _L < V _b3 <
If V _b1 < V _b2 < V _H ), the output pulse width of the IC 106 changes to W ₁ , W ₂ , and W ₃ respectively.

V _b is IC111, resistor 110, 112, voltage is
Non-inverting input terminal 1 held at V _BB (typically -1.29V)
It is obtained by applying the original adjustment voltage Va to the input terminal 108 of the inverting amplifier consisting of 09 and varying it.

With the above configuration, the input common mode voltage of the IC 106 when the output signal of the IC 106 is inverted is equal to V _b .

However, the allowable operating input voltage range of ICs used in logic circuits is smaller than their output voltage range, so the value of V _b cannot be set close to V _H or V _L , and therefore the pulse width adjustment range is limited. It is not possible to take a wide range of

Further, as the value of V _b approaches V _H or V _L , noise near the threshold increases, and delay jitter and pulse width jitter increase.

[Purpose of invention]

SUMMARY OF THE INVENTION It is an object of the present invention to overcome the above-mentioned drawbacks and to provide a low-jitter pulse width adjustment circuit in which the pulse width adjustment range of a signal is equal to the sum of the first and second transition times of the pulse.

[Summary of the idea]

In one embodiment of the invention, a regulation voltage and an input signal voltage are superimposed on both the inverting and non-inverting input terminals of the IC acting as the differential comparator. The voltages at each input terminal change complementarily when a signal is input, and the input voltages are always equal when the comparison output is inverted.

Therefore, since the comparison output can be inverted at any level of the input signal voltage, the pulse width adjustment width becomes equal to the sum of the first and second transition times of the input signal pulse.

Furthermore, since the input signal voltage when the comparison output is inverted can be set arbitrarily, it is selected (for example, -1.29V for ECL) so that the jitter of the output pulse is minimized.

[Example of idea]

FIG. 1 is a diagram showing one embodiment of the present invention, and FIG. 4 is a waveform diagram for explaining the operation of this embodiment.

In Figure 1, IC3, 8, and 15 are made up of ECL
Gate. The outputs of these ICs are open emitter outputs, with resistors 4 and 5; resistors 9 and 10;
Resistors 16 and 17 are the output resistances of ICs 3, 8, and 15, respectively, and are all selected to have the same value _RE .

The original input signal Vi is applied between the non-inverting input terminal 1 and the inverting input terminal 2 of the IC3, and generates complementary logic signal pulses as input signals at the non-inverting output terminal 41 and the inverting output terminal 42 of the IC3. Original input signal Vi and
The transition time of this complementary logic signal pulse is determined by the characteristics of IC3.

On the other hand, a feedback resistor 14 (resistance value R _D ) is inserted between the non-inverting input terminal and the inverting output terminal 171 of the IC 15, and an input resistor 13 (resistance value R _C ) is inserted between the non-inverting input terminal and the terminal 11. is connected.

The inverting input terminal of IC15 is set to the center value of the input voltage of IC15 (-1.29V at _VBB in ECL).

Assuming that the potential of the terminal 11 with respect to the ground 20 is Va, this is the original adjusted voltage. The voltage at the terminal 171 is expressed by the following equation when it is set as _VaN .

Va _N =V _BB -R _D /R _C (Va - V _BB ) ... (1) The regulated voltage is obtained at terminals 161 and 171.

Since the output voltage of the terminal 161 is complementary to the output voltage of the terminal 171, if it is designated as _VaP , it is expressed by the following equation.

Va _P = V _BB + R _D /R _C (Va−V _BB ) ...(2) The voltage between terminals 41 and 42 and ground, respectively.
Assuming Vi _P and Vi _N , Vi _P and Vi _N are complementary, so Vi _P + Vi _N = 2V _BB (3).

A resistor 6 (resistance value R _A ) and a resistor 18 (resistance value R _B ) are connected between the non-inverting input terminal 61 and terminals 41 and 161 of IC8, which acts as a differential comparator, respectively, and the inverting input terminal of IC8 62 and terminal 42,1
71, there is a resistor 7 (resistance value R _A ) and a resistor 19.
(resistance value R _B ) are connected to each other. Resistors 6, 7, 18, and 19 serve as coupling resistances for input signals and adjustment voltages.

The voltage between terminals 61, 62 and ground is Vt _P ,
Assuming Vt _N , they are expressed as shown below in a state that does not change over time.

Vt _P = R _B Vi _P + R _A Va _P /R _A +R _B ......(4) Vt _N = R _B Vi _N +R _A Va _N /R _A +R _B ......(5) Therefore, the output of IC8 is inverted. The threshold voltage V _t is
Given from V _tN = V _tP .

V _tN = V _tP ...(6) From R _B (Vi _P - Vi _N ) + R _A (Va _P - Va _N ) = 0 ... (7) Find Vi _P from equations (7) and (3) By substituting into equation (4), Vt _N =Vt _P =V _BB (8) is obtained.

In order to expand the amount of pulse width adjustment, terminal 61,
Capacitance 2 of equal value between 62 and ground
Similarly, (8) holds when 1 and 22 are connected.

Also, the time rate of change of the differential input to IC8 near Vt _N = Vt _P = V _BB is Va _P , where t is time.
Assuming that Va _N is constant, d/dt(Vt _P −Vt _N )=d/dt{R _B (Vi _p −Vi _N )/R _A +
R _B } ...(9) d/dt (Vi _P + Vi _N ) = 2 dV _BB /dt = 0... (10) From d/dt (Vt _P + Vt _N ) = 2R _B /R _A +R _B・dVi _P /dt……(11
) becomes.

Even in the typical case where R _A = R _B , from equation (11), d/dt (Vt _P + Vt _N ) = dVi _P /dt ...(12), which is the same as the transition slope in the conventional example. .

The waveforms resulting from the above operation are as shown in FIG. 4, where waveform A represents Vt _P and waveform B represents Vt _N.

Since the voltage difference V _G changes depending on the original adjustment voltage Va, the output pulse width W _a changes accordingly.

In addition, in the example, R _E = 68Ω, V _E = 3V R _A = R _B
= 147Ω R _D = 196Ω, R _C = 100Ω. The first and second transition times of the output pulse of the ECL gate are approximately equal and the waveform is as shown in FIG. 4, so the output pulse does not have a delay with respect to the input pulse due to amplitude variation. In the embodiment described above, both terminals 61 and 62 were excited complementary, but one terminal was connected to a fixed voltage V _BB
A configuration in which the power is energized is also possible.

In this case, the slope of the differential input when the output of IC8 is inverted is smaller than in the previous example, and although jitter increases, the circuit can be simplified.

[Effect of idea]

As detailed in the above embodiment, according to the present invention, it is possible to select a pulse width at any level within the entire amplitude range of the input signal, and the slope of the comparator input voltage can also be maintained, thereby eliminating the occurrence of jitter. does not occur.

Furthermore, when obtaining an adjustment range comparable to that of the conventional example, the linearity between the original adjustment voltage and the adjustment amount (and the adjustment voltage) improves, making control easier.

Therefore, it is useful for practical use.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing one embodiment of the present invention.
The figure is a circuit diagram showing a conventional example, FIG. 3 is a waveform diagram explaining the operation of the conventional example, and FIG. 4 is a waveform diagram explaining the operation of one embodiment of the present invention. 1, 2: Original signal input terminal, 3, 8, 15: IC
Gate, 4, 5, 9, 10, 16, 17: Emitter resistance, 13: Input resistance, 14: Feedback resistance, 6,
7, 18, 19: Resistor for combining input signal and adjustment voltage, 11: Original adjustment voltage input terminal, 1
2: V _BB input terminal, 21, 22: Adjustment width expansion capacitor, 101: Original signal input terminal, 102, 1
06,111: IC gate, 103,107,1
13: Emitter resistor, 104: Resistor for expanding adjustment width, 105: Capacitor for expanding adjustment width, 108:
Original adjustment voltage input terminal, 109: V _BB input terminal, 1
10: Input resistance, 112: Feedback resistance.

Claims (1)

[Scope of utility model registration request] a first ECL gate 3 having a first output terminal that inputs an input signal Vi and outputs a logic signal pulse; and a second output terminal that outputs a complementary logic signal pulse of the logic signal pulse; A differential comparator 8 having a second input terminal, and a first resistor 6 connecting the first input terminal and the first output terminal.
, a second resistor 7 that connects the second input terminal and the second output terminal, and a third resistor 18 that connects the first input terminal and the adjustment voltage input terminal 161; A pulse width adjustment circuit comprising a fourth resistor connecting the second input terminal and an input terminal 162 of a complementary voltage of the adjustment voltage.