JPH0339945U - - Google Patents

Info

Publication number
JPH0339945U
JPH0339945U JP10047489U JP10047489U JPH0339945U JP H0339945 U JPH0339945 U JP H0339945U JP 10047489 U JP10047489 U JP 10047489U JP 10047489 U JP10047489 U JP 10047489U JP H0339945 U JPH0339945 U JP H0339945U
Authority
JP
Japan
Prior art keywords
clock signal
pll circuit
reproduces
address
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10047489U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0720974Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989100474U priority Critical patent/JPH0720974Y2/ja
Publication of JPH0339945U publication Critical patent/JPH0339945U/ja
Application granted granted Critical
Publication of JPH0720974Y2 publication Critical patent/JPH0720974Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP1989100474U 1989-08-30 1989-08-30 ２重ｐｌｌ装置 Expired - Lifetime JPH0720974Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989100474U JPH0720974Y2 (ja) 1989-08-30 1989-08-30 ２重ｐｌｌ装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989100474U JPH0720974Y2 (ja) 1989-08-30 1989-08-30 ２重ｐｌｌ装置

Publications (2)

Publication Number Publication Date
JPH0339945U true JPH0339945U (enExample) 1991-04-17
JPH0720974Y2 JPH0720974Y2 (ja) 1995-05-15

Family

ID=31649481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989100474U Expired - Lifetime JPH0720974Y2 (ja) 1989-08-30 1989-08-30 ２重ｐｌｌ装置

Country Status (1)

Country Link
JP (1) JPH0720974Y2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11112338A (ja) * 1997-09-30 1999-04-23 Yamaha Corp 周波数制御方式

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291230A (ja) * 1986-05-29 1987-12-18 ノ−ザン・テレコム・リミテツド 同期デ−タ信号生成のために非同期デ−タ信号を同期化する方法及び装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62291230A (ja) * 1986-05-29 1987-12-18 ノ−ザン・テレコム・リミテツド 同期デ−タ信号生成のために非同期デ−タ信号を同期化する方法及び装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11112338A (ja) * 1997-09-30 1999-04-23 Yamaha Corp 周波数制御方式

Also Published As

Publication number Publication date
JPH0720974Y2 (ja) 1995-05-15

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