JPH0338923A - Pcm codec - Google Patents

Abstract

PURPOSE:To simplify the PCM CODEC and to attain circuit integration by providing an adder circuit selecting a linear code signal among them, and outputting the result with addition, and a means controlling and adjusting the level of the linear code signal. CONSTITUTION:An analog signal inputted from a terminal 54 is converted into a linear code signal by an A/D converter 2, inputted to an encoder 1, where the signal is converted into a prescribed PCM signal and it is outputted from a terminal 51. A PCM signal received from terminals 52, 53 is converted into a linear code signal by decoders 3, 4 and inputted to an adder circuit 5, selected by a control signal and the result is added and outputted to a gain variable circuit 6, converted into an analog signal by a D/A converter 7 and outputted from a terminal 55. Thus, each one circuit of the encoder 1, decoders 3, 4, A/D converter 2 and D/A converter 7 or the like is enough to plural PCM signal inputs, the circuit scale is simplified and large scale integration is easily attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PCM codec, and in particular, the present invention relates to a PCM codec.
[NTEGRATED 5ERVICES DIGIT
The present invention relates to a PCM codec used in voice communication in ALNETIllORK) communication.

[Conventional technology]

Conventionally, this type of PCM codec performs A/D conversion and D/D conversion between a pair of digital input signals and output signals and a pair of analog output signals and input signals.
It is generally configured with a function to perform A conversion.

[MME to be solved by the invention The conventional PCM codec described above only has the function of handling one pair of signals. The disadvantage is that a codec must be used.

[Means to solve the problem]

The PCM codec of the present invention includes means for inputting a plurality of PCM signals or time-division multiplexed PCM signals, converting each of the PCM signals individually, and generating and outputting a plurality of linear code signals; an adding circuit which inputs a linear code signal, selects each of the linear code signals and adds and outputs the linear code signals via a predetermined control signal; , and means for controlling and adjusting the level of the linear code signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the invention. As shown in FIG. 1, this embodiment has an encoder l and an A/
D converter 2, first decoder 3, and second decoder 4
, an adder circuit 5 , a variable gain circuit 6 , and a D/A converter 7 .

In FIG. 1, an analog signal inputted from a terminal 54 is converted into a linear code signal by an A/D converter 2, inputted to an encoder l, converted to a predetermined PCM signal, and then outputted from a terminal 51. Ru. The PC)4 signal inputted manually from the terminal 52 is converted into a linear code signal by the first decoder 3 and input to the adder circuit 5.

Similarly, the PCM signal input from the terminal 53 is converted into a linear code signal by the second decoder 4 and input to the adder circuit 5. In the adder circuit 5, the terminal 56
The two linear code signals are selected and added under the control of a control signal input from the
+71 is output to the receiver circuit 6. In the variable gain circuit 6, the level of the linear code signal input from the adder circuit 6 is controlled and adjusted by the control signal input from the terminal 57, and is output to the D/A converter 7. D/
In the A converter 7, the linear code signal is converted into an analog signal and outputted via the terminal 55.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram of a second embodiment of the invention. As shown in FIG. 2, this embodiment includes a time division output circuit 8,
An encoder, an A/D converter IO, a first signal holding circuit 11, a second signal holding circuit 12, a first decoder 13, a second decoder 14, an addition circuit 15,
It is configured to include a variable gain circuit 16 and a D/A converter 17.

In FIG. 2, the analog signal input from the '4I element 60 is converted into a PC+4 signal via the A/D converter 10 and encoder 9, and is input to the 1 time division output circuit 16. , the PCM signal is distributed to time slots specified by timing signals inputted from terminals 62 and 63, multiplexed by time division, and outputted via terminal 58.

On the other hand, in the first signal holding circuit 11, from among the time division multiplexed PCM signals inputted from the terminal 59,
Similarly, in the second signal holding circuit I2, the signal of the time slot specified by the timing signal inputted from the terminal 59 is extracted and held. The signal of the time slot specified by the timing signal manually inputted from the quadrature 62 is taken out and held.

First signal holding circuit 11 and second signal holding circuit 12
The signals held in are converted into linear code signals in the first decoder 13 and the second decoder 14, respectively, and both are input to the adder circuit 15. In the adder circuit 15, the two linear code signals are selected and added under the control of a control signal inputted from the terminal 64, and outputted to the variable gain circuit 16. In the variable gain circuit 16, the level of the linear code signal input from the adder circuit 15 is controlled by the control signal input from the terminal 65, and
It is output to the D/A converter 17. D/A converter 17
, the linear code signal is converted into an analog signal and outputted via the terminal 61.

[Effects of the Invention] As described above in detail, the present invention provides a
It is only necessary to provide one circuit each of encoders, decoders, A/D converters, D/A converters, etc. in response to signal input, and PCM By simplifying the codec circuit scale,
This has the advantage that it can be easily implemented as an LSI.

[Brief explanation of drawings]

1 and 2 are block diagrams of first and second embodiments of the present invention, respectively. In the figure, 1.9... Encoder, 2.10
...A/D converter, 3, L3...No.■
decoder, 4°14...th decoder, 5.
15...Addition circuit, 6.16...Variable gain circuit, 7.17...D/A converter, 8...
. . . Time division output circuit, 11 . . . First signal holding circuit, 12 . . . Second signal holding circuit.

Claims (1)

[Scope of Claims] Means for inputting a plurality of PCM signals or time-division multiplexed PCM signals, converting each of the PCM signals individually, and generating and outputting a plurality of linear code signals; An adder circuit inputs a linear code signal and selects and adds and outputs the linear code signals through a predetermined control signal; , means for controlling and adjusting the level of the linear code signal.