JPH0338922A - Analog/digital converter - Google Patents

Abstract

PURPOSE:To quicken a processing time by a time referencing a membership function and to obtain a fuzzy processor with simple constitution by outputting digitally a grade number corresponding to the membership function in response to an analog input signal. CONSTITUTION:Plural decoder blocks 1b1-1bn receiving plural reference voltages 1a1-1an and decoding them respectively corresponding to a prescribed membership function are provided, and outputs 1c1-1cn and an analog input voltage 3 are compared. Then the result of fuzzy deduction is outputted digitally in response to an analog input signal from its own A/D converter. Thus, the entire constitution of a fuzzy controller is simplified, and compactness and high speed processing are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an analog/digital converter (hereinafter abbreviated as an A/D converter), and particularly to an A/D converter suitable for a fuzzy controller.

[Prior art]

As a conventional A/D converter, there is one as shown in FIG. 6, for example.

Although there are many types of A/D converters, a successive approximation type is shown here. This successive approximation type has a medium speed (conversion time of several μs to several hundred μs), has a relatively small number of elements, and is suitable for high integration.

In FIG. 6, (a) shows a voltage comparison type, (b) shows a current comparison type, and (C) shows a charge comparison type.

In the circuit of Figure 6, the digital/analog converter (
Hereinafter abbreviated as D/A converter) 1 analog output (voltage V
D or current In) and analog input voltage 3 to be converted
is compared by the comparator circuit 2, and the output of the D/A converter 1 is successively changed by the control circuit 4 and the register 51.
When the data of the register 5 is taken out at the point where it seems to be exactly equal to the analog input voltage 3, the data is digitally converted data and f, A'.

FIGS. 7 and 8 show the A/C as shown in FIG.
Combining a D converter with a fuzzy chip
FIG. 3 is a diagram showing an example of a configuration of a controller. Regarding such a fuzzy controller, for example,
Nikkei Electronics, Nα457, ρP, 157-1
68, 1988J.

In the fuzzy controller shown in the figure, an input signal is converted into a digital quantity by an A/D converter, and then a fuzzy processor (in Fig. 7, S
Fuzzy inference is performed using a RAM (mainly composed of RAM, in FIG. 8, mainly composed of EPROM), and the result is converted into an analog quantity by a D/A converter.

As mentioned above, in a fuzzy inference machine that performs digital processing, in practice, it is often input as an analog quantity and output as an analog quantity, so the input signal is first A/D converted and then digitally processed.

Since the result is D/A converted and output, the overall scale increases and there is a limit to the effective inference speed (time from analog input to analog output). On the other hand, if everything is made up of analog circuits, the configuration will be simplified, but digital processing is more advantageous in terms of controller reliability, noise resistance, larger scale, and lower power consumption.

[Problem to be solved by the invention]

As mentioned above, when using a conventional A/D converter in a fuzzy controller, the input analog quantity is converted into a digital quantity, then fuzzy inference is performed, and the result is converted back into an analog quantity and output. Furthermore, since the configuration includes an A/D converter, a fuzzy digital processor, and a D/A converter, the configuration becomes large-scale and the processing flow becomes long.

Therefore, there was a problem in that the advantages of the fuzzy controller, such as being more compact and faster, were diminished.

The present invention aims to solve the problems of the prior art as described above.

[Means to solve the problem]

In order to achieve the above object, the present invention is configured as described in the claims.

That is, in the A/D converter of the present invention.

A plurality of decoder blocks are provided to input a plurality of reference voltages and decode each corresponding to a predetermined membership function, and the output is compared with an analog input signal, and the A/D converter itself is , by outputting fuzzy inference results (or intermediate results) in digital quantities according to analog input signals, fuzzy inference
This allows the overall configuration of the controller to be simplified.

Each decoder block described above has, for example, the characteristic of a multivalued function (for example, a bivalued function) in which there are multiple analog quantities corresponding to one digital quantity, as shown in FIG. 2(b) below. Furthermore, as shown in FIG. 2(c), the analog quantities of adjacent decoder blocks overlap each other.

〔Example〕

FIG. 1 is a block diagram of one embodiment of the present invention.

The circuit in the engineering drawing is 1! A reference voltage generator 1a that outputs voltages 1a, . . . lcn, and a decoder block 1
b□, 1b2. ...lbn, a comparator circuit 2, an up/down counter 5, and an output latch circuit 6. Also, 1 c, , 1 c2
,...lcn are decoder blocks 1b□, respectively.
lb2, . . . shows the output of lbo. Although not shown in the engineering drawings, some control logic circuits are required.

Moreover, the above decoder block lb is shown in FIG. 2(a).
The configuration is as shown in (details will be described later).

Next, the effect will be explained.

First, an outline of fuzzy inference will be explained based on FIG.

As shown in Figure 3, in fuzzy inference, multiple 1f-t
Consider a hen-style rule. Further, in this case, two rules (rule 1 and rule 2) will be explained as an example.

In FIG. 3, X, , X2 are input signals, specifically sensor signals and the like. y is an output signal, specifically an actuator control signal. Also, A)
1 to A 2 are fuzzy quantities, and specifically represent ambiguous expressions such as "a little big" and "a little big." And Ao, ~A 23 is x as shown
It is expressed as a function of l, x2, and y, and is called a membership function. The horizontal axis of the membership function is X-, Xz-:
/, but the vertical axis is called grade g and represents the degree of ambiguity. Normalizing the grade indicates that g=l is an unambiguous set, and g=Q is not included in that set. When expressed by membership functions according to the rules, it becomes as shown in the figure.

Here, when the values x,=x, , x,=x, @ are input to the input signal, a grade g is output according to each membership function. The inference method is to find the minimum gT of the great value of the antecedent part using each rule (grx and grz
), the membership function of the consequent part is cut by g'r. Combine the membership functions of each cut y (
(maximum value line), and finally find the center of gravity of the combined membership to calculate the output value yo. The details of this calculation method are as follows.

“Nikkei Electronics, Na2S2, pp, 160J
It is described in etc.

There are various methods for calculating the output value yo (defuzzification) in addition to the above. For example, the values y□, y2 of g=1 of the membership function of the consequent part and the grades gT, -gTx
Accordingly, it is possible to defuzzify by taking the average like gTx+gTz. FIG. 3 illustrates the case where this method is used. Regarding this method, for example, "International Workshop on Fuzzy System Applications"
on Fuzzy System Application
ons,” 198g.

ρp, 252-253. ) is described in J.

The role of the A/D converter of the present invention is to provide an analog input signal (x
The purpose is to output the grade gT in the form of a digital signal according to the membership function when the input signal (zo, x2°) is input.

Next, the operation of the circuit shown in FIG. 1 will be explained.

First, a group of U* output from the reference voltage generator 1a
, tt pressure 1a□, . The input analog signal 3 to be converted is compared with the above-mentioned reference voltage by the comparator circuit 2. Then, the reference voltage to be taken out is changed (details will be described later), and the above operation is repeated until the comparator circuit 2 is inverted.

When the output of the comparator circuit 2 (reset signal 2b) rises, the up/down counter 5 sends its output to the output latch circuit 6 and is reset.

The output 8 of the above output latch circuit 6 is the analog input (8
This is a digital signal corresponding to No. 3.

In order for this output 8 to correspond to the grade according to the membership function, decoder blocks lb, 1b2 .・
... lb, it is necessary to devise some measures. In FIG. 1, the shapes of membership functions are schematically drawn for each of decoder blocks 1b□, 1b2, . . . 1bn.

Note that the reason why there is input overlap between decoder blocks is because there is overlap between membership functions.

There are N levels of membership functions.1For example, N=
If it is 7, then [■ Negatively large, ■ Negatively normal.

It corresponds to seven types: ■negatively small, ■zero, ■positively small, ■positively normal, and ■positively large].

The above N levels are N decoder blocks 1
bx, 1 b2. ...lb, in one-to-one correspondence.

Further, the select signal 7(d) is a signal for selecting the decoder block (given from an external circuit, for example, a microcomputer, etc.), and is a signal for selecting the decoder block.
The decode signal 5b output from the decoder block is a signal for selecting within the decoder block. In addition, in the circuit of Fig. 1,
Each decoder block receives a 3-bit decode signal 5b.
(a, b.

C).

Next, the decoder block has a configuration as shown in FIG. 2(a).

In FIG. 2(a), the decoder block lb is
It is controlled by a 3-bit decode signal (a, b, c) and a select signal 7 (dn). Of course, the number of bits can be increased if necessary.

In other words, the above 3-bit belief ";'7 (a , b ,
c), the grade is (Ol) for 2 bits (a, b)
o) to (1,1). Also, 1 bit (
In C), when the membership function m is a binary function, choose whether it is on the upper side or the lower side. Further, this decoder block lb is selected by the select signal (d, 1).

In addition, the transmission gate 9 indicated by a circle has a signal of +1 Hi
It is in a conductive state when g h 11, and the decode signal (
a, b, c) and the selected analog signal according to the select signal (dn) is output to output 1cn.

For example, the upper analog quantity corresponding to grade (1, O) is output to the output 1cn and compared with the analog signal 3 in the comparator circuit 2.

Furthermore, each of the decoder blocks described above has, for example, the characteristic of a multivalued function in which a plurality of analog quantities correspond to one digital quantity, as shown in FIG. As shown in (c), adjacent decoder blocks have a characteristic in which the analog amounts of adjacent decoder blocks overlap.

In addition, in FIGS. 2(b) and (c), the parabolic 2
Although the case of a valence function is illustrated, other shapes such as a polygonal line or a trivalence function or more may also be used.

By configuring the decoder block as described above, it is possible to output an analog quantity corresponding to the grade of the selected membership function m, and the output latch circuit 6
The output signal 8 of is the grade corresponding to the analog input signal 3 (for example, X8°).

If you want to use membership functions of various types, the following methods are available: (i) Prepare decoder blocks for all types, (ii) EPRO the decoder block.
A possible solution would be to make it programmable using M or the like.

Next, FIG. 5 is a block diagram showing an example of constructing a fuzzy chip or a fuzzy processor using the above-mentioned A/D converter.

First, FIG. 5(a) shows a method in which each rule is inferred in a time-division manner. In this method, the scale does not depend on the number of rules, but the inference speed becomes slow.

In FIG. 5(a), the analog input signal X1. Enter X2°.

The signals are respectively input to the A/D converters 11 and 11' of the present invention. Further, the control circuit 13 first selects the membership function of the rule ↓ using the signals d□, d2, and d. Regarding the consequent part, the digital circuit 14 makes it grade 1.
It is sufficient to output only 1'Jyt. In this case, y I = d 3 is sufficient.

Next, the A/D converter 11. ↓Gray′- converted by 1′
gt (6 bits in the figure) is the minimum value circuit 12
The smallest gt is selected and input to the defuzzification circuit 15 and stored. Note that if there is any other digital gT input from the outside, it can be input to this 6-bit bus.

Next, for rule 2, the control circuit 13 specifies the Mentorship function, and similarly, the gray 16-2 is input to the defuzzification circuit 15 through A/D conversion.

As a result of the above operation (7), the defuzzification circuit 15 has the following.

yl, yz, gTl, g'rz force S is digitally manually calculated, y is calculated according to equation (1) above, and D
/A conversion, analog output y′″ as the inference result
is obtained.

Next, the circuit shown in FIG. 5(b) has an A/D
This is a configuration with conversion conversion earthwork 1.11-2.11-3.1↓-4. This configuration allows high-speed processing.

Next, FIG. 4 is a block diagram of another embodiment of the A/D converter of the present invention.

This embodiment includes decoder blocks lb1, lb2, .
...The output of lbn is divided into two outputs on the upper side and the lower side, and the comparator circuit 2 and the comparator circuit 2' are connected to each of them, and the logical sum of the outputs 2a' and 2a is calculated using the OR circuit 10. , it is latched and reset signal 2
C.

In this configuration, since the output of the decoder block is divided into two, the decoder signal 5b only needs to be two bits (a, b), and decoding is performed by a down (or up) counter 5'. With this configuration, comparison is performed in parallel, and the A/D conversion speed can be approximately doubled.

It is possible to further increase the speed by increasing the number of comparator circuits and parallelizing them, but the number of elements increases.

Power consumption increases.

As described above, if the A/D converter of the present invention is used, the A/D converter of the present invention can be used.
Since it automatically becomes a fuzzy quantity within the conversion time of D conversion,
Compared to the conventional examples shown in Figures 7 and 8, the time to read the membership function from memory (memory access time) is faster, speeding up the fuzzy inference circuit when there is an analog input. I can do it.

〔Effect of the invention〕

As explained above, according to the present invention, the grade number corresponding to the membership function is output as a digital quantity according to the analog input signal, thereby speeding up the time required to refer to the membership function. In addition, a fuzzy chip or a fuzzy processor that mainly performs digital processing on analog input can be realized with a simple configuration. Therefore, it is possible to construct a system that can handle higher speeds and lower power consumption. This effect can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the second embodiment of the present invention. FIG. 2 is a circuit diagram and characteristic diagram of one embodiment of the decoder block, FIG. 3 is a characteristic diagram for explaining fuzzy inference, FIG. 4 is a block diagram of the second embodiment of the present invention, and FIG. The figure is a block diagram of a fuzzy chip using the A/D converter of the present invention, FIG. 6 is an example of a conventional A/D converter, and FIGS. 7 and 8 are examples of a conventional fuzzy controller. FIG. <Explanation of symbols> 1...D/A converter 2...Comparator circuit 3...Analog input voltage 4...Control circuit 5...Up/down counter 6...Output latch 7...・Decoder block select 8...Digital output signal 9...Analog transmission gate O...OR gate signal

Claims (1)

[Claims] A reference voltage generator that generates a plurality of reference voltages, and a reference voltage generator that is controlled according to the output of the following counter, inputs the plurality of reference voltages, and decodes each of the plurality of reference voltages corresponding to a predetermined membership function. a plurality of decoder blocks; one or more comparator circuits for comparing the magnitude of an analog input signal to be converted into a digital signal with an output signal of the decoder block; and an output of the comparator circuit or a logical sum of the outputs. An analog/digital converter comprising: a counter that is reset in synchronization with an edge of an output; and a latch circuit that latches the output of the counter and outputs it as a digital output signal.