JPH0834429B2 - Fuzzy inference circuit including analog / digital converter - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a fuzzy inference circuit including an analog / digital converter (hereinafter abbreviated as A / D converter).

[Prior Art] As a conventional A / D converter, for example, there is one shown in FIG.

Although there are many types of A / D converters, the successive approximation type is shown here. This successive approximation type is suitable for high integration at a medium speed (conversion time of several μs to several hundreds of μs) and a relatively small number of elements.

In FIG. 6, (a) shows a voltage comparison type, (b) shows a current comparison type, and (c) shows a charge comparison type.

In the circuit of FIG. 6, the analog output (voltage V _D of the digital / analog converter (hereinafter abbreviated as D / A converter) 1)
Alternatively, the current I _D ) is compared with the analog input voltage 3 to be converted by the comparator circuit 2, and the output of the D / A converter 1 is sequentially changed by the control circuit 4 and the register 51, and it seems that the analog input voltage 3 is exactly the same. When the data in the register 51 is taken out, the data becomes digitally converted data.

7 and 8 show the A / A as shown in FIG. 6 above.
Combine the D converter with a fuzzy chip to
It is a figure which shows the example which comprised the controller. Regarding such a fuzzy controller, for example,
`` Nikkei Electronics, No.457, pp.157-168, 198
8 ”.

In the fuzzy controller shown in the figure, a fuzzy processor that converts an input signal into a digital value with an A / D converter and then performs digital processing (SR in FIG.
Fuzzy inference is performed with AM as the main component and EPROM as the main component in Fig. 8), and the result is converted into an analog amount by the D / A converter.

As described above, in a fuzzy reasoner that performs digital processing, in practice, it is often input in an analog amount and output in an analog amount, so after the input signal is A / D converted and digitally processed, Since the result is D / A converted and output, the overall scale increases and the effective inference speed (time from analog input to analog output) also comes to a limit. On the other hand, if all are configured by analog circuits, the configuration is simplified, but digital processing is more advantageous in consideration of reliability, noise resistance, large scale, and low power consumption of the controller.

[Problems to be Solved by the Invention]

As described above, when using a conventional A / D converter for a fuzzy controller, the fuzzy inference is performed after converting the input analog quantity into a digital quantity, and the result is converted back into an analog quantity for output. , A / D converter,
Since the fuzzy digital processor and the D / A converter were configured, the configuration became large and the processing flow became long. Therefore, there is a problem in that the advantage of the fuzzy controller that it can be made compact and high speed is diminished.

The present invention is intended to solve the problems of the prior art as described above.

[Means for solving the problem]

In order to achieve the above object, the present invention is configured as described in the claims.

That is, in the present invention, a plurality of decoder blocks for inputting a plurality of reference voltages and outputting an analog value corresponding to a predetermined membership function are provided, and the outputs are compared with the analog input signal. Then
By configuring the A / D converter itself to output the fuzzy inference result (or intermediate result) in digital amount according to the analog input signal, it is possible to simplify the overall configuration of the fuzzy controller. It was done.

It should be noted that each of the above decoder blocks has a multi-valued function (for example, 2 if there are a plurality of analog amounts corresponding to one digital amount, as shown in FIG. 2B).
2), and also has the characteristic that the analog amounts of adjacent ones of the plurality of decoder blocks overlap each other, as shown in FIG. 2 (c).

〔Example〕

 FIG. 1 is a block diagram of an embodiment of the present invention.

The circuit shown in FIG. 1 includes a reference voltage generator 1a that outputs reference voltages 1a ₁ ... 1a _n ... And decoder blocks 1b ₁ , 1b ₂ , ... 1b _n.
A comparator circuit 2, an up / down counter 5, and an output latch circuit 6. Also,
1c ₁ , 1c ₂ , ... 1c _n are decoder blocks 1b ₁ , 1b, respectively
₂ ... Shows the output of 1b _n . Although not shown in FIG. 1, some control logic circuits are required.

Also, the above decoder block 1b _n is shown in FIG. 2 (a).
The configuration is as shown in (details will be described later).

 Next, the operation will be described.

First, the outline of fuzzy inference will be described with reference to FIG.

As shown in Fig. 3, fuzzy inference involves multiple if-the
Consider an n-type rule. In this case, two rules (rulel, rule2) will be described as an example.

In FIG. 3, x ₁ and x ₂ are input signals, specifically sensor signals and the like. y is an output signal, specifically, an actuator control signal or the like. Also, A _{11 to} A ₂₃
Is a fuzzy amount, and specifically expresses an ambiguous expression such as "slightly large" or "slightly small". And
A _{11 to} A ₂₃ are expressed by the functions of x ₁ , x ₂ and y as shown in the figure,
Called the membership function. The horizontal axis of the membership function is x ₁ , x ₂ , y, while the vertical axis is called grade g, which represents the degree of ambiguity. When the grades are normalized, g = 1 indicates an unambiguous set, and g = 0 indicates that it is not included in the set. When it is expressed by a membership function according to the rule, it becomes as shown in the figure.

Here, when values of x ₁ = x ₁ ° and x ₂ = x ₂ ° are input to the input signal, the grade g is obtained according to each membership function. As a method of inference, the minimum g _T of the grade g of the antecedent part is obtained by each rule (g _T1 and g _T2 ), and the membership function of the consequent part is cut by g _T. Each y cut
The membership function of (1) is combined (the maximum value line), the center of gravity of the finally combined membership is calculated, and the output value y ° is calculated. The details of this calculation method are described in "Nikkei Electronics, No.457, pp.160" and the like.

There are various methods for obtaining the output value y ° (defuzzification) other than the above, for example, the values y ₁ and y _{2 of the} membership function g = 1 and the grades g _T1 and g of the consequent part. _{With T2} , It is possible to defuzzify by taking an average like. FIG. 3 illustrates the case where this method is used. Regarding this method, for example, "International Workshop on Fuzzy System Applications (" International Workshop on Fuzzy System
Applications, "1988, pp.252-253,)".

The ratio of the A / D converter of the present invention is the analog input signal (x ₁
° or x ₂ °) is input, its grade g _T is output as a digital signal according to the membership function.

 Next, the operation of the circuit shown in FIG. 1 will be described.

First, _{one of the} group of reference voltages 1a ₁ , ... 1a _n ... Output from the reference voltage generator 1a is connected to the decoder block 1
1b _n are taken out as their outputs 1c ₁ , 1c ₂ , ... 1c _n via b ₁ , 1b ₂ , ... 1b _n, and are input to the input 1c of the comparator circuit 2 to convert the input analog signal 3 to be converted and the above reference voltage. The comparison circuit 2 compares. Then, the reference voltage to be taken out is changed (details will be described later), and the comparator circuit 2 performs comparison. Then, the reference voltage to be taken out is changed (details will be described later), and the above operation is repeated until the comparator circuit 2 is inverted. In addition,
This operation is performed in synchronization with a clock signal (not shown). The up / down counter 5 counts the clock signal. When the output of the comparator circuit 2 (reset signal 2b) rises, the up / down counter 5 sends its output to the output latch circuit 6 and is reset.

The output 8 of the output latch circuit 6 is a digital signal corresponding to the analog input signal 3.

In order for this output 8 to correspond to the grade by the membership function, decoder blocks 1b ₁ , 1b ₂ , ... 1b _n
Need to be devised. Figure 1 shows the decoder block
The form of the membership function is schematically written in each of 1b ₁ , 1b ₂ , ... 1b _n .

It should be noted that there is an overlap of inputs between decoder blocks because there is an overlap between membership functions.

The numbership function has N levels, for example, N
If = 7, it corresponds to 7 kinds of [negative large, normal negative, negative small, almost zero, positive small, positive normal, positive large].

The above N levels are N decoder blocks 1b.
There is a one-to-one correspondence with ₁ , 1b ₂ , ... 1b _n .

Further, the select signal 7 (d) is a signal for selecting a decoder block (given from an external circuit such as a microcomputer), and the decode signal 5b output from the up / down counter 5 is in the decoder block. This is a signal for selection. In addition, in the circuit of FIG.
Each decoder block has a 3-bit decode signal 5b
It operates in (a, b, c).

Next, the decoder block has a structure as shown in FIG.

In FIG. 2 (a), the decoder block 1b _n is
It is controlled by a 3-bit decode signal (a, b, c) and a select signal 7 (d _n ). Of course, the number of bits can be increased if necessary.

That is, in the above 3-bit signal (a, b, c), 2 bits (a, b) are graded from (0, 0) to (1,
Up to 1) is specified. In addition, with 1 bit (c), when the membership function m is a binary function, the upper side or the lower side is selected. Further, this decoder block 1b _n is selected by the select signal (d _n ).

Also, the signals of the transmission gates 9 indicated by circles are "High".
Is in the conductive state when, and the decode signals (a, b, c)
And the analog signal selected according to the select signal (d _n ) appears at the output 1c _n . For example, the upper analog quantity corresponding to the grade (1, 0) is output to the output 1c _n and compared with the analog signal 3 by the comparator circuit 2.

 The operation of FIG. 2 will be described below based on an actual example.

For example, it is assumed that each reference voltage output from the reference voltage generator 1a has a lowest value of 1a _{1 and} is a voltage that sequentially increases at a predetermined interval as it becomes 1a ₂ , 1a _3, ... Each of these reference voltages is input to the input terminal 1an of the decoder block of FIG. 2 (a).
Each decoder block is connected so as to correspond to a predetermined membership function. For example, as an example of realizing the triangular membership function indicated by the broken line m on the left side of FIG. 2 (a), the lowest reference voltage 1a ₁ is simply connected to the input terminals in order from the lowest. To 1a ₂ , to 1a ₃ , to 1a ₄ , to 1a ₅ , to 1a ₆ ,
1a ₇ and 1a ₈ should be connected respectively. That is, in the case of a linear characteristic such as the polygonal line m, the equally spaced reference voltages may be sequentially connected from the lower side to the higher side. In this case, the reference voltages output from the reference voltage generator 1a may be connected in a discontinuous manner, such as 1a ₁ , 1a ₄ , 1a ₇ ... In short, in the case of linearity, since the count value and the grade correspond linearly, it suffices to input the reference voltage at equal intervals to each input terminal. Incidentally, FIG. 2 (b)
In the case of a curve such as that shown in FIG. 6C or 7C, according to the characteristics, the connection is made such that the interval of the reference voltage is small in the portion where the characteristic changes largely and the interval of the reference voltage is large in the portion where the change is small. . For example, to 1a ₁ , to 1a ₂ , to 1a
₄ , to 1a ₈ , to 1a ₁₂ , to 1a ₁₄ , to 1a ₁₅ , to 1a ₁₆
Connect as.

Next, the up / down counter 5 is set to 2 of (a, b).
The bit corresponds to the grade, and 1 bit in (c) is used for switching between up-counting and down-counting.
That is, (c) is initially 0, and (a, b) is sequentially up-counted as (0,0) → (0,1) → (1,0) → (1,1), and then, When c becomes 1, (1,1) → (1,0) → (0,
1) → Count down as (0,0). When c = 0, since = 1, the c-side (lower half) transmission gate is turned on, and when c = 1, the c-side (upper half) transmission gate is turned on. When a = 0, = 1 and b
When = 0, it becomes = 1. Therefore, depending on the count value of the counter 5, when counting up, first, in the case of (0,0), the transmission gate connected to the input terminal is turned on and the reference Voltage 1a ₁ is output from 1cn. Similarly, as the count value increases, the transmission gates are turned on in the order of →→→, and when the count is down, the transmission gates are turned on in the order of →→→.
Therefore, as a whole, →→→→→→
The transmission gates are turned on in the order of →, and 1a ₁ → 1a ₂ → 1a ₃
→ 1a ₄ → 1a ₅ → 1a ₆ → 1a ₇ → 1a ₈ The reference voltage is output in this order. In addition, the grade of the membership function corresponds to the above count value, (0,0) → (0,1)
→ (1,0) → (1,1) → (1,1) → (1,0) → (0,1) →
It changes with (0,0). That is, the grade value has a triangular (correctly trapezoidal in this example) characteristic, as shown by a broken line m in FIG.

The above example shows the case where the membership function has a triangular characteristic. However, by setting the relationship between the reference voltage and the installation position of the transmission gate in the decoder block as appropriate, the membership of an arbitrary characteristic can be obtained. Function can be realized.

Further, dn is a signal for selecting a corresponding block from a plurality of decoder blocks, whereby the decoder blocks 1b ₁ to 1b _n of FIG. 1 are sequentially selected one by one, and The output of the selected decoder block is sent to the comparator circuit 2.

The comparator circuit 2 sequentially compares the reference voltage given from the decoder block and the input analog voltage, and when the magnitude relationship between the reference voltage and the input analog voltage is inverted, the output is inverted. .

The counter 5 counts and sequentially outputs the clock signal, and is reset each time the output of the comparator circuit 2 is inverted, and the output at that time is held and output by the latch circuit 6. Therefore, the output of the latch circuit 6 is a count value until the magnitude relationship between the reference voltage and the input analog voltage is inverted after resetting, that is, a digital value corresponding to the grade value at that time. It becomes the value converted to. Therefore, the converted digital value automatically becomes a fuzzy amount.

Also, each of the above decoder blocks is, for example, the second
As shown in FIG. (B), it has a characteristic of a polyvalent function in which there are a plurality of analog quantities corresponding to one digital quantity,
Further, as shown in FIG. 2 (c), it has a characteristic that the analog amounts of adjacent ones of the plurality of decoder blocks overlap. In addition, in FIGS. 2B and 2C, the case of a parabolic divalent function is illustrated, but there are also cases of characteristics of other shapes such as a polygonal shape or a trivalent function or more.

By configuring the decoder block as described above, it is possible to output an analog amount corresponding to the grade of the selected membership function m, and the output signal 8 of the output latch circuit 6 is the analog input signal 3 (for example, x ₁ °) corresponding grade.

If you want to use various types of membership functions, consider (i) preparing decoder blocks for all types, (ii) making the decoder part programmable with EPROM, etc. To be

Next, FIG. 5 is a block diagram showing an example in which a fuzzy chip or a fuzzy processor is configured using the A / D converter as described above.

First, FIG. 5 (a) shows a method of inferring each rule by time division. In this method, the scale does not depend on the number of rules, but the inference speed becomes slow.

In FIG. 5 (a), the analog input signal x ₁ ° by the sample-and-hold type the x ₂ °, respectively inputted to the A / D converter 11, 11 'of the present invention. Further, the control circuit 13 first determines that the membership function of rule 1 is the signal d ₁ ,
Selected by d ₂ and d ₃ . Digital circuit for the consequent part
According to 14, it is sufficient to output only the grade 1 coordinates y _i . In this case, y _i = d ₃ is sufficient.

Next, transformed Grade g _T by the A / D converter 11, 11 'is (are 6 bits in the figure) smallest g _T1 at the minimum value circuit 12 is selected, input to a defuzzification circuit 15 Are stored. If there is another digital g _T input from the outside, it can be input to this 6-bit bus.

Next, for rule 2, the control circuit 13 specifies the membership function, and similarly the grade g _T2 is input to the defuzzification circuit 15 by A / D conversion.

With the above operation, the defuzzification circuit 15 has y ₁ ,
This means that y ₂ , g _T1 and g _T2 have been digitally input, and y ₀ is calculated according to the equation (1) and D / A converted to obtain an analog output y ° as an inference result.

Next, the circuit shown in FIG. 5 (b) uses A / D for each rule.
The converters 11 _-1 , 11 _-2 , 11 _-3 , 11 _-4 are provided. According to this configuration, high speed processing is possible.

Next, FIG. 4 is a block diagram of another embodiment of the present invention.

In this embodiment, the decoder blocks 1b ₁ , 1b ₂ , ... 1b _n
Is divided into two on the upper side and the lower side to form two outputs, the comparator circuit 2 and the comparator circuit 2 ′ are connected to each, and the OR of the outputs 2a ′ and 2a is obtained by the OR circuit 10,
It is 2c for the latch / reset signal.

In this configuration, the decoder block output is 2
Since it is divided into two, the decoder signal 5b may be 2 bits of (a, b), and the decoder is performed by the down (or up) counter 5 '. According to this structure, the comparisons are performed in parallel, and the A / D conversion speed can be increased about twice.

It should be noted that if the number of comparator circuits is further increased and parallelized, the speed can be further increased, but the number of elements and power consumption increase.

As described above, according to the present invention, since the fuzzy amount is automatically set within the conversion time of the A / D conversion, the membership function can be compared with the conventional examples shown in FIGS. 7 and 8. It becomes faster by the time of reading from the memory (memory access time), and the fuzzy inference circuit when there is an analog input can be made faster.

[Effects of the Invention] As described above, according to the present invention, since the number of grades corresponding to the membership function is output in a digital amount according to the analog input signal, the membership function is referred to. Therefore, it is possible to speed up the operation for a certain period of time, and it is possible to realize a fuzzy chip or a fuzzy processor that mainly performs digital processing for analog input with a simple configuration. Therefore, there is an effect that it is possible to construct a system that can cope with high speed and low power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram and a characteristic diagram of an embodiment of a decoder block,
FIG. 3 is a characteristic diagram for explaining fuzzy reasoning, FIG. 4 is a block diagram of a second embodiment of the present invention, FIG. 5 is a block diagram of a fuzzy chip to which the present invention is applied, and FIG. An example of a conventional A / D converter, FIGS. 7 and 8 are block diagrams of an example of a conventional fuzzy controller. <Description of Codes> 1 ... D / A converter 2 ... Comparator circuit 3 ... Analog input voltage 4 ... Control circuit 5 ... Up / down counter 6 ... Output latch 7 ... Decoder block select signal 8 ... Digital output signal 9 ... Analog transmission gate 10… OR gate

Claims (1)

[Claims] 1. A reference voltage generator for generating reference voltages of a plurality of analog values having different values, and a relationship between an output of a counter and a grade value is preset corresponding to a predetermined membership function, A voltage having a preset value corresponding to the grade value corresponding to the output of the counter is selected from a plurality of reference voltages given from the reference voltage generator corresponding to the output of the counter, and sequentially. A circuit for outputting as an analog voltage, each of which has a characteristic corresponding to a predetermined membership function, and a plurality of the decoder blocks are sequentially selected, and each decoder is selected in the selected order.・ Circuit that sequentially outputs block output, analog input signal to be converted to digital signal, and analog output from the above decoder block A comparator circuit that compares the magnitude with a voltage, a counter that counts and outputs clock signals sequentially, and is reset in synchronization with the output of the comparator circuit or the edge of the logical sum output of the outputs, and the output of the counter A fuzzy inference circuit including an analog / digital converter, which comprises: