JPH0338881A - Vertical insulated gate field effect transistor - Google Patents
Vertical insulated gate field effect transistorInfo
- Publication number
- JPH0338881A JPH0338881A JP17460189A JP17460189A JPH0338881A JP H0338881 A JPH0338881 A JP H0338881A JP 17460189 A JP17460189 A JP 17460189A JP 17460189 A JP17460189 A JP 17460189A JP H0338881 A JPH0338881 A JP H0338881A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- drain
- type
- diode
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims description 8
- 230000002457 bidirectional effect Effects 0.000 claims abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 14
- 229920005591 polysilicon Polymers 0.000 abstract description 14
- 230000015556 catabolic process Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 230000003071 parasitic effect Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は絶縁ゲート電界効果ｌ・ランジスタに関し、特
に、電力用のスイッチング用トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to insulated gate field effect transistors, and more particularly to power switching transistors.
現在、電力用絶縁ゲート電界効果トランジスタ（以下パ
ワーＭＯＳＦＥＴと記す）は、高速性と１、
熱暴走しにくいことなどからモーター・アクチュエータ
ー リレーなど、コイルを負荷として使われている。特
にバイポーラ−トランジスタに比べて多数キャリアで動
作するパワーＭＯＳＦＥＴは、発熱するとオン抵抗が上
がり、ドレイン電流を減らすためチップの一部に発熱が
集中しにくく、熱暴走しにくい。ところがパワーＭＯＳ
ＦＥＴはオン時の動作は多数キャリア動作のため熱暴走
しにくいが、コイル負荷でオフする際に発生するコイル
の逆起電力サージが特に問題となっている。Currently, insulated gate field effect transistors (hereinafter referred to as power MOSFETs) for power use are used as coil loads in motors, actuators, relays, etc. due to their high speed,1, and resistance to thermal runaway. In particular, compared to bipolar transistors, power MOSFETs that operate with majority carriers have an increased on-resistance when they generate heat, and because they reduce drain current, it is difficult for heat to concentrate on a part of the chip, making it difficult for thermal runaway to occur. However, power MOS
FETs are less prone to thermal runaway because they operate as majority carriers when they are on, but the back electromotive force surge in the coil that occurs when the FET is turned off due to a coil load is particularly problematic.
第７図は従来のパワーＭＯＳＦＥＴを示す半導体チップ
の断面図、第８図はコイル負荷駆動時の等価回路図であ
る。FIG. 7 is a sectional view of a semiconductor chip showing a conventional power MOSFET, and FIG. 8 is an equivalent circuit diagram when driving a coil load.
ＤｉはＰベース領域５とＮ−ドレイン領域１間の接合ダ
イオード、ＴｒはＰベース領域、Ｎ＋ソース領域６．Ｎ
−ドレイン領域をそれぞれベース、エミッタ、コレクタ
とする寄生トランジスタ、ＲＢは寄生ベース抵抗である
。Di is a junction diode between the P base region 5 and the N- drain region 1, and Tr is the P base region and the N+ source region 6. N
- A parasitic transistor whose drain region is its base, emitter, and collector, respectively, RB is a parasitic base resistance.
第９図はコイル負荷駆動時の動作を説明するためのタイ
ミングチャートである。FIG. 9 is a timing chart for explaining the operation when driving a coil load.
）ワー
最初オンしていたパワーＭＯＳＦＥＴがｔｏｆｆでオフ
するとコイルＬに逆起電力が発生し、ドレイン・ソース
間電圧■Ｄ３が急上昇し、ドレイン・ソース間降伏電圧
ＢＶＤＳに至ってコイルに蓄積されたエネルギーを放電
し始める。この放電はドレイン・ソース間の降伏電流で
行なわれるが、ノくワーＭＯ３ＦＥＴにおいては構造上
寄生トランジスタＴｒができてしまうため、ドレイン・
ソース間降伏電流は、寄生トランジスタＴｒにも流れて
しまう。この電流は寄生トランジスタＴｒのベス電位を
上昇させいわゆるラッチバックを引きおこし熱暴走に至
る。) When the power MOSFET, which was initially on, turns off due to toff, a back electromotive force is generated in the coil L, and the drain-source voltage D3 rises rapidly, reaching the drain-source breakdown voltage BVDS, and the energy stored in the coil. begins to discharge. This discharge occurs due to the breakdown current between the drain and the source, but since a parasitic transistor Tr is created in the structure of the NOWER MO3FET, the drain and source
The source-to-source breakdown current also flows to the parasitic transistor Tr. This current increases the base potential of the parasitic transistor Tr, causing so-called latchback, leading to thermal runaway.
これを防止するため、ドレイン・ソース間にツェナーダ
イオードを入れて放電電流をこのツェナーダイオードに
流すことが行なわれている。To prevent this, a Zener diode is inserted between the drain and source, and a discharge current is passed through the Zener diode.
またバイポーラ−トランジスタではベース・ドレイン間
にツェナーダイオードを入れてツェナーを降伏させてベ
ース電流を流すことでトランジスタをオンさせ放電電流
を流すことが行なわれている。Furthermore, in a bipolar transistor, a Zener diode is inserted between the base and drain to cause the Zener to break down and allow a base current to flow, thereby turning on the transistor and causing a discharge current to flow.
上述した従来のパワーＭＯＳＦＥＴでは、寄生トランジ
スタのラッチバックを防止するためドレイン・ソース間
にツェナー・ダイオードを挿入してコイルの放電電流を
流していた。このツェナー・ダイオードは大きい放電電
流を流しても、本体の寄生トランジスタの降伏電圧を越
えないようにするため降伏時の動作抵抗を下げる必要が
あり、必然的に大面積になるという欠点がある。In the above-mentioned conventional power MOSFET, a Zener diode is inserted between the drain and source to prevent the parasitic transistor from latchback, and the discharge current of the coil is caused to flow. This Zener diode has the disadvantage that even if a large discharge current flows through it, the operating resistance at breakdown must be lowered so as not to exceed the breakdown voltage of the parasitic transistor in the main body, which inevitably results in a large area.
本発明の縦型絶縁ゲート電界効果トランジスタは、 保
護用の双方向ツェナーダイオードをゲート・ソース間及
びドレイン・ゲート間にそれぞれ挿入して縦型絶縁ゲー
ト電界効果トランジスタ本体と同一チップ上に集積して
なるというものである。The vertical insulated gate field effect transistor of the present invention has protective bidirectional Zener diodes inserted between the gate and the source and between the drain and the gate and integrated on the same chip as the vertical insulated gate field effect transistor body. It becomes.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す半導体チップの断面図
、第２図は一実施例の等価回路図である。FIG. 1 is a sectional view of a semiconductor chip showing an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the embodiment.
ケート・ソース間には、双方向ツェナータイオード２゜
ｓ （Ｎ型ポリシリコン膜１０−１．Ｐ”型ポリシリコ
ン膜１１．Ｎ型ポリシリコン膜１〇−２からなる）を接
続する。ドレイン・ゲート間にはＮ−ドレイン領域１中
に形成したＮ＋ドレイン領域２．Ｐ型拡散層３．Ｎ＋型
型数散層４らなる双方向ツェナーダイオードＺＤＯを接
続する。A bidirectional Zener diode 2°s (consisting of an N-type polysilicon film 10-1, a P''-type polysilicon film 11, and an N-type polysilicon film 10-2) is connected between the gate and source.Drain - A bidirectional Zener diode ZDO consisting of an N+ drain region 2 formed in the N- drain region 1, a P type diffusion layer 3, and an N+ type scattering layer 4 is connected between the gates.
ツェナーダイオード２゜Ｓは本体のゲートポリシリコン
に連続して形成する。ＺＯＳの降伏電圧は２５〜４５Ｖ
として、サージ吸収時にゲート酸化膜８が破壊しないよ
うにする。The Zener diode 2°S is formed continuously on the gate polysilicon of the main body. Breakdown voltage of ZOS is 25-45V
As a result, gate oxide film 8 is prevented from being destroyed during surge absorption.
ツェナーダイオードＺＤＧはＮ−ドレイン領域１中にイ
オン注入と、押込で形成する。降伏電圧を本体ＦＥＴの
降伏電圧より下げるためドレインと同一導電型でドレイ
ン層よりやや高濃度の層２を形成しておき、この中にツ
ェナーダイオードを形成する。ダイオードの表面端子は
ゲートポリシリコンと接続する。The Zener diode ZDG is formed in the N-drain region 1 by ion implantation and pushing. In order to lower the breakdown voltage below that of the main FET, a layer 2 of the same conductivity type as the drain and slightly higher concentration than the drain layer is formed, and a Zener diode is formed in this layer. The surface terminal of the diode is connected to the gate polysilicon.
第３図は一実施例によるコイル負荷駆動時の回路図、第
４図は動作を説明するためのタイミング５、τ、
チャートである。FIG. 3 is a circuit diagram when driving a coil load according to one embodiment, and FIG. 4 is a timing 5, τ, chart for explaining the operation.
ツェナーダイオードＺＤＯの降伏電圧Ｂ Ｖ ＺＤＯは
以下の条件を満たすように設計する。The breakdown voltage B V ZDO of the Zener diode ZDO is designed to satisfy the following conditions.
Ｂ Ｖ ＺＤＯ＜ Ｌ Ｖ ＣＥＲＢ Ｖ ｚｏｓ 。B V ZDO < L V CERB V zos.
Ｌ Ｖ ｃｇ＊・・・・・・寄生トランジスタのラッチ
バック電圧、
ＢＶｗａｓ・・・・・・ツェナーダイオード２゜Ｓの降
伏電圧、
Ｂ Ｖ ｚｏｓは以下の条件を満たすように設計する。L V cg*... Latchback voltage of parasitic transistor, BVwas... Breakdown voltage of Zener diode 2°S, B V zos are designed to satisfy the following conditions.
Ｖｏ８（。ｎ） ＜ Ｂ Ｖ ＺＱＳ ＜ Ｖ （Ｂ！
（ｍａ Ｘ） ７ＶＧ１１（。ｎ）・・・・・・パワ
ーＭＯＳＦＥＴがオンする時のゲート電圧、
■ｏ８（□、り・・・・・・ゲート破壊電圧ゲート電圧
が上昇してパワーＭＯＳＦＥＴがオすると、次式
％式％）
に従ってドレイン電流が上昇し、ドレイン電圧はＶＤＳ
（。、、）となる。ｔｏｆｆで入力電圧は下がりパワー
ＭＯＳＦＥＴのドレイン電圧は急上昇しはじめるがＢ
Ｖ ａｓ 十Ｂ Ｖ ＺＤＧを越えた瞬間にパワーＭＯ
８−６ニ
ＦＥＴのドレイン電圧の上昇を抑えるようにゲト電圧が
印加される。Vo8 (.n) < B V ZQS < V (B!
(ma Then, the drain current increases according to the following formula (% formula %), and the drain voltage becomes VDS
(.,,) becomes. At toff, the input voltage decreases and the drain voltage of the power MOSFET begins to rise rapidly, but B
V as 10B V Power MO at the moment you cross ZDG
A gate voltage is applied to suppress an increase in the drain voltage of the 8-6 FET.
つまり、小電力のツェナーダイオードＺＤＧでも本体の
パワーＭＯＳＦＥＴの増幅作用を使って充分大きな放電
電流を流すことができる。In other words, even a small-power Zener diode ZDG can cause a sufficiently large discharge current to flow by using the amplification effect of the power MOSFET in the main body.
第５図は本発明の他の実施例を示す半導体チップの断面
図、第６図はその等価回路図である。FIG. 5 is a sectional view of a semiconductor chip showing another embodiment of the present invention, and FIG. 6 is an equivalent circuit diagram thereof.
この実施例では、ツェナーダイオードＺＤＧＩ。In this example, a Zener diode ZDGI.
ＺＤＧ２をＮ−ドレイン領域内にではなく、ゲートポリ
シリコンに連続してポリシリコンツェナーダイオードと
して形成する。つまりＺＤＯＩ、ＺＤＧ２はＮ型ポリシ
リコン膜１０−１．１０−２，１０３、Ｐ＋型ポリシリ
コン膜１１−１．１１−２からなっている。この実施例
ではＢ Ｖ ＺＤＧがＮ−ドレイン領域と無関係に決め
られるため、より自由度が太きいという利点がある。ZDG2 is formed as a polysilicon Zener diode, not in the N-drain region, but continuous to the gate polysilicon. That is, ZDOI and ZDG2 are composed of N type polysilicon films 10-1, 10-2, 103 and P+ type polysilicon films 11-1, 11-2. In this embodiment, since B V ZDG is determined independently of the N-drain region, there is an advantage that the degree of freedom is greater.
以上説明したように、本発明はドレイン・ゲート間とゲ
ート・ソース間に双方向ツェナー・ダイオードを挿入す
ることによって、小さい面積の７＝
）
ツェナーダイオードで大きいザージ電流を吸収すること
ができ、保護用ダイオードを備えた縦型絶縁ゲート電界
効果トランジスタのチップ面積を小さくすることができ
る効果がある。As explained above, by inserting bidirectional Zener diodes between the drain and the gate and between the gate and the source, the Zener diode with a small area can absorb a large surge current and provide protection. This has the effect that the chip area of a vertical insulated gate field effect transistor equipped with a diode can be reduced.
第１図及び第２図はそれぞれ本発明の一実施例を示す半
導体チップの断面図及び等価回路図、第３図及び第４図
はそれぞれ一実施例によるコイル負荷駆動時の等価回路
図及びタイミングチャート、第５図及び第６図は他の実
施例を示す半導体チップの断面図及び等価回路図、第７
図は従来例を示す半導体チップの断面図、第８図及び第
９図は従来例によるコイル負荷駆動時の等価回路図及び
タイミングチャートである。
１・・・・・・Ｎ−ドレイン領域、２・・・・・・Ｎ＋
ドレイン領域、３・・・・・・Ｐ型拡散層、４・・・・
・・Ｎ＋型型数散層５・・・・・・Ｐベース領域、６・
・・・・・Ｎ＋ンース領域、７・・・・・・Ｐウェル、
８・・・・・・ゲート絶縁膜、９・・・・・・ゲート電
極、１０−１〜１０−４・・・・・・Ｎ型ポリシＢ
、”１
リコン膜、
１１゜
１ １−１゜
２・・・・・・Ｐ＋型ポ
リシリコン膜。1 and 2 are a cross-sectional view and an equivalent circuit diagram of a semiconductor chip showing one embodiment of the present invention, respectively, and FIGS. 3 and 4 are an equivalent circuit diagram and timing diagram when driving a coil load according to one embodiment, respectively. Charts, FIGS. 5 and 6 are cross-sectional views and equivalent circuit diagrams of semiconductor chips showing other embodiments, and FIGS.
The figure is a sectional view of a semiconductor chip showing a conventional example, and FIGS. 8 and 9 are equivalent circuit diagrams and timing charts when driving a coil load according to the conventional example. 1...N- drain region, 2...N+
Drain region, 3... P-type diffusion layer, 4...
...N+ type scattered layer 5...P base region, 6.
...N+ region, 7...P well,
8... Gate insulating film, 9... Gate electrode, 10-1 to 10-4... N-type policy B, "1 Recon film, 11°1 1-1゜2...P+ type polysilicon film.
Claims (1)
及びドレイン・ゲート間にそれぞれ挿入して縦型絶縁ゲ
ート電界効果トランジスタ本体と同一チップ上に集積し
てなることを特徴とする縦型絶縁ゲート電界効果トラン
ジスタ。A vertical insulated gate field effect transistor characterized in that bidirectional Zener diodes for protection are inserted between the gate and the source and between the drain and the gate and integrated on the same chip as the main body of the vertical insulated gate field effect transistor. transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1174601A JP2762581B2 (en) | 1989-07-05 | 1989-07-05 | Vertical insulated gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1174601A JP2762581B2 (en) | 1989-07-05 | 1989-07-05 | Vertical insulated gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0338881A true JPH0338881A (en) | 1991-02-19 |
| JP2762581B2 JP2762581B2 (en) | 1998-06-04 |
Family
ID=15981430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1174601A Expired - Lifetime JP2762581B2 (en) | 1989-07-05 | 1989-07-05 | Vertical insulated gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2762581B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0520168A2 (en) * | 1991-06-12 | 1992-12-30 | Fuji Electric Co., Ltd. | MOS-type semiconductor device drive circuit |
| US5502338A (en) * | 1992-04-30 | 1996-03-26 | Hitachi, Ltd. | Power transistor device having collector voltage clamped to stable level over wide temperature range |
| WO2008153142A1 (en) * | 2007-06-15 | 2008-12-18 | Rohm Co., Ltd. | Semiconductor device |
| JP2015185618A (en) * | 2014-03-20 | 2015-10-22 | 株式会社東芝 | semiconductor device |
-
1989
- 1989-07-05 JP JP1174601A patent/JP2762581B2/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0520168A2 (en) * | 1991-06-12 | 1992-12-30 | Fuji Electric Co., Ltd. | MOS-type semiconductor device drive circuit |
| EP0520168A3 (en) * | 1991-06-12 | 1995-05-17 | Fuji Electric Co Ltd | |
| US5502338A (en) * | 1992-04-30 | 1996-03-26 | Hitachi, Ltd. | Power transistor device having collector voltage clamped to stable level over wide temperature range |
| WO2008153142A1 (en) * | 2007-06-15 | 2008-12-18 | Rohm Co., Ltd. | Semiconductor device |
| US8217419B2 (en) | 2007-06-15 | 2012-07-10 | Rohm Co., Ltd. | Semiconductor device |
| US8729605B2 (en) | 2007-06-15 | 2014-05-20 | Rohm Co., Ltd. | Semiconductor switch device |
| US9419127B2 (en) | 2007-06-15 | 2016-08-16 | Rohm Co., Ltd. | Semiconductor device including switching devices in an epitaxial layer |
| JP2015185618A (en) * | 2014-03-20 | 2015-10-22 | 株式会社東芝 | semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2762581B2 (en) | 1998-06-04 |
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