JPH0338830A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a high integration and a high speed without lowering reliability by a method wherein a low-capacity wiring layer is constituted of wiring layers in mutually perpendicular directions at an upper layer and a high-density wiring layer is constituted of wiring layers which are situated at the lower part than the upper layer. CONSTITUTION:A low-capacity wiring layer is constituted of wiring layers M13, M14 in mutually perpendicular directions at an upper layer; a high-density wiring layer is constituted of wiring layers M11, M12 which are situated at the lower part than the upper layer. Consequently, high speed is realize without causing an electromigration phenomenon at the low-capacity wiring layers M13, M14 at the upper layer; on the other hand, a high integration is realized at the high-density wiring layers M11, M12 at the lower part than the upper layer. Thereby, the high integration and the high speed are realized simultaneously without lowering reliability.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a technology that is effective when applied to semiconductor devices. It relates to techniques that are effective for use in devices.

[Prior art] In recent years, due to the demand for higher integration of LSIs, a three-layer wiring structure has been created by stacking further wiring layers on top of the conventional two-layer wiring layers running vertically and horizontally (orthogonally to each other). is emerging.

For a semiconductor device with this three-layer wiring structure, for example, Y
, 5uehiro et al “A 1.20-G
ATIE USA [lLE CMO5SEA OF G
ATES PACKING 1.3M TRANSIS
TOR5'', CICC 1,988, p, 20.5.2.

According to this description, the inter-wiring pitch P1 of the first N-th wiring M1
is 2.9 μm, and the inter-wire pitch P2 of the second layer wiring M2 is 3
．． 8 μm, and the inter-wiring pitch P3 of the third layer wiring M3 is 5.8
μm, and the inter-wiring pitch P3 of the third-layer wiring M3 on the top layer is longer than that of the other two wiring layers Ml and M2, making it a low-capacitance wiring. It is thought to be used for wiring and clock wiring. Here, each wiring layer Ml, M2 . Although there is no clear description regarding the wiring direction of M3, the pitch P3 between the wirings of the second layer wiring 4M3 is twice the pitch P1 between the wirings of the first layer wiring M1. Since the layer wiring layer M1 and the second layer wiring 4M2 are usually perpendicular to each other, the first layer wiring M1 and the third layer wiring M3 are in the same direction as shown in FIG. 15, FIG. 16, and FIG. 7, respectively. The receiver has the wiring of
The second layer wiring M2 is the 1N wiring M1 and the third layer wiring M2.
It is thought that the Uke has wiring in a direction perpendicular to 3.

Wiring material and wiring (between wiring NMl and M2, M
There is no description of the thickness of the interlayer insulating film (between M2 and M3), but this interlayer insulating film thickness is described in Documents T and Ko
bayashi“DLN/TLM Compatible
e 1゜0μm Gate Array tiith
0ver 100K Llsable Gates.

According to CICC 1988, p. 20.9.1, approximately
Interlayer insulating film 3 between first layer wiring M1 and second layer wiring M2
The film thickness 'F1' of the interlayer insulating film 4 between the second layer wiring M2 and the third layer wiring M3 are both about 1.0 μm, and the film thicknesses Tl and T2 are approximately 1.0 μm. are considered to be equal.

Note that 1 represents the semiconductor substrate, and 2 represents the semiconductor substrate l and the first
Reference numeral 5 indicates an insulating film between the layer wiring M1 and a passivation film on the third layer wiring MMa.

[Problems to be Solved by the Invention] However, the semiconductor device having the above configuration has the following problems.

That is, when the current density of the wiring is increased (increased) in order to increase the speed of the semiconductor device, an electromigration phenomenon occurs, resulting in a decrease in reliability.

Here, as mentioned above, if the pitch between wires is simply widened, the wire capacitance will be reduced to some extent, and it will be possible to achieve a slight increase in speed without increasing the current density, that is, without reducing reliability. This is not sufficient, and furthermore, it becomes difficult to achieve high integration.

Although this problem is not so much of a problem in semiconductor devices having a wiring structure of three or less layers, it becomes a serious problem especially for semiconductor devices having multilayer wiring of four or more layers, which will increase in the future.

The present invention has been made in view of the above problems, and its main purpose is to easily provide a semiconductor device that is simultaneously highly integrated and high-speed without causing a decrease in reliability.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, in a semiconductor device having four or more ffR wiring layers for handling electrical signals, the wiring layers in the upper layer in directions orthogonal to each other are made into low-capacitance wiring layers, and the wiring layers below the upper layer are made into high-density wiring layers. They are configured to be different from each other.

[Function] According to the above-mentioned means, the wiring layers in the upper layer in the mutually orthogonal directions are configured to be low-capacitance wiring layers, and the wiring layers below the upper layer are configured to be high-density wiring layers. In the wiring layer, the speed can be increased without causing electromigration, but on the other hand, the high-density wiring layer below the second layer! Because each layer can be highly integrated, the dual purpose of achieving high integration and high speed at the same time without deteriorating reliability can be achieved.

In addition, since the upper low-capacitance wiring layer is composed of wiring layers in directions perpendicular to each other, the low-capacitance wiring layer can be wired with a greater degree of freedom.
(design automation) becomes easy, and the above-mentioned purpose of simple manufacturing is achieved.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

Embodiments of the semiconductor device according to the present invention are shown in FIG. 1, FIG. 2, and FIG. 3. The outline is as follows.

In FIGS. 1, 2, and 3, the reference numeral 11 indicates a semiconductor substrate, and this semiconductor substrate 1'' has an insulating film 1.
The first layer wiring Mll is connected to the first layer wiring M1.2 via the first layer wiring M1.2.
On top of 1 is the upper layer #l! The second layer wiring M1.2 is connected to the second layer wiring M12 through the first edge film 13, and the third layer wiring M1.2 is connected to the third layer wiring M1.2 through the second interlayer insulating film 14.
A fourth wire is placed on the M wire M13 via the third interlayer insulating film 5.
Layer wiring M14 is formed respectively, and the fourth layer wiring @
A passivation film 16 is formed on M14. The first layer wiring Mll, the third layer wiring M13, the second layer wiring M12, and the fourth layer wiring M1.4 face the same direction, and the first layer wiring Mll and the third layer wiring M1.4 face the same direction.
3, the second layer wiring M12, and the fourth layer wiring M1.4 are arranged so as to face directions perpendicular to each other.

Here, the inter-wiring pitch Pi1 of the first layer wiring Mll and the inter-wiring pitch P↓2 of the second M wiring M12 are each 3 μm.
In addition, the inter-wiring pitch P13 of the third layer wiring M13 and the inter-wiring pinch P14 of the fourth layer wiring M1.4 are each 6 μm.
The inter-wiring pitch of the upper wiring layer, that is, the inter-wiring pitch P 1.3 of the third layer wiring M13 = 7- and the inter-wiring pitch P14 of the fourth layer wiring M 1.4 is the same as that of the upper wiring layer. The inter-wiring pitch of the lower wiring layer, that is, the inter-wiring pitch pH of the first layer wiring Mll and the inter-wiring pitch P12 of the second layer wiring M1.2
It is twice as much.

Further, the first interlayer, 11! Thickness T of membrane 13]-1
The thickness T12 of the second interlayer insulating film 14 and the thickness T13 of the third interlayer insulating film J5 are each 2 μm, and the thickness of the interlayer insulating film in the region where the upper wiring layer is formed is 1 μm. , that is, the second interlayer insulating film]-4 film thickness T12
and third interlayer insulating film] 5 is twice the thickness of the interlayer insulating film in the region formed below it, that is, the film thickness Tll of the first interlayer insulating film 13. It has become.

Here, the inventor investigated the capacitance between adjacent wires and the wire capacitance through experiments. The results are shown in Table 1 and FIG.

Table 1 is a comparison table of the capacitance between adjacent layers when the interlayer #@edge film is made thicker without changing the pitch between wires. Here, both A and B are interconnects in the same layer in the parallel direction and each have an interconnect width of 1.6 μm.

As is clear from the table, the space between wires A and B (1
, 6 μm) and simply increase the thickness of the interlayer insulating film (0.8 μm is case 2.3, 2 μm is case l),
It can be seen that the adjacent capacitance (the capacitance between the pair of wires A and 8 relative to the capacitance of the wire A) CAB/CTOTAL becomes large.

That is, it is derived that when the interlayer insulating film is made thicker, the capacitance between adjacent wires cannot be reduced unless the pitch between wires is also increased. Further, when the interlayer insulating film is made thicker, the capacitance between adjacent wires is larger with respect to the total capacitance CTOTAL, so it is derived that the wire A is more susceptible to noise from the wire B.

Table 1 FIG. 4 is a diagram showing the relationship between interlayer insulating film thickness and wiring capacitance when the pitch between wirings is used as a parameter.

As is clear from the figure, when the thickness of the interlayer insulating film is increased, the interconnect capacitance cannot be reduced satisfactorily unless the pitch S between the interconnects is made relatively long.

That is, it can be seen that if only either the pitch between the wirings or the thickness of the interlayer insulating film is increased, the wiring capacitance cannot be reduced much.

As described above, according to the inventor's experiments, the capacitance of the wiring layer cannot be effectively lowered unless both the pitch between the wirings and the interlayer insulation film thickness are increased.

It can also be seen that it is easily affected by noise from adjacent wiring.

By the way, in the semiconductor device of this example, the wiring layers (the third M wiring M13 and the fourth M wiring M13 and the fourth M wiring M13 and
The inter-wiring pitches P13 and PI3 of the layer wiring M14) are lengthened, respectively, and the wiring 1M13. The second and third inter-M insulating films 14 in the region where M14 is formed. ．． 15 is made thicker, this upper layer arrangement 1. N (3rd N distribution A
IM13 and the fourth layer wiring M↓4) are wiring layers with extremely low capacitance. Additionally, noise from adjacent wiring is also reduced.

In this way, in the upper layer of the semiconductor device of this embodiment, it is possible to increase the speed without causing the electromigration phenomenon.

Therefore, in this embodiment, these low capacitance wiring 1Ml
3. For M14, locations with large circuit delays (locations where speeding up is desired) are preferentially used.

Furthermore, as the wiring capacitance decreases, the CR time constant of the wiring becomes shorter, making it possible to transmit short pulses, and the charging current of the wiring becomes smaller, improving reliability.
The low capacitance wiring layer M13. M14 is preferentially used for such wiring, that is, long wiring that transmits short pulses, and locations where the wiring current increases to charge the wiring capacitance and the reliability of the wiring decreases.

11- In particular, the top layer wiring layer (in this example, the fourth layer wiring M
14. ), the pitch between the wires increases due to the layout, and since no wiring layer is formed above it, the wiring capacitance is particularly small. The problem area has been identified.

On the other hand, the upper low capacitance wiring layer M13. Wiring layer below M1.4 (first layer wiring M, 11 and second layer wiring M12)
Inter-wiring pitch pH, P 1.2 and this wiring layer Ml
1. Third inter-M insulating film 1 in the region where Ml2 is formed
4 are each shortened as before (the length is the same as before), so that the wiring layers M1 .
], , M12 is a high-density wiring layer.

Therefore, it is possible to achieve higher integration in the wiring layer below the upper layer.

Further, the low capacitance wiring layer M13. M1.4 is made of aluminum, copper, silver, etc., while high-density wiring layer M1
-1. , M1.2 are each made of a high melting point metal such as tungsten, and "N1?" Low capacity distribution IIA layer M13. The material of M14 is higher than that of the high-density wiring layer M1.1. Since it has a lower resistance than the material of M12, the low capacitance wiring layer M13. The effect of speeding up M14 is enhanced.

Moreover, in this embodiment, the low capacitance wiring layers Ml3, Ml
Since the cross-sectional area of the high-density wiring layers Mll and M12 is configured to be larger than that of the low-capacity wiring layers M13.
The effect of speeding up M14 is further enhanced.

Furthermore, the low capacitance wiring layer M13. The high-density wiring layers Mli and M12 connected to M14 are connected to M13. Since the same current as that of Ml4 flows, the current density will be higher than that of the low-capacitance wiring layer Ml3゜M1.4, and there is a risk that electromigration will occur. The material (high melting point metal such as tungsten) has a lower capacitance than the wiring layer M13. Since the material of M14 (aluminum, copper, silver, etc.) has stronger resistance to electromigration, that fear has disappeared.

In this manner, in the semiconductor device of this embodiment, it is possible to achieve high integration and high speed at the same time without causing a decrease in reliability.

Next, an example of a method for manufacturing a semiconductor device configured as described above will be described below with reference to FIGS. 5 to 14.

First, as shown in FIG. 5, a semiconductor substrate 11 on which active elements such as FETs and bipolar devices are to be integrated is prepared. Since the present invention relates to wiring, the detailed structure of the substrate 11 will not be described.

Next, BPSG (B) with a thickness of 1.0 μm was applied to the entire surface.

A BPSG film (insulating film) 12 is formed by forming a BPSG film (ron-doped PSG) by the CVD method, and the surface is flattened by reflow during heat treatment at 950° C., and the state shown in FIG. 6 is obtained.

Next, the BPSG film 12 is removed by a known photoetching method.
A contact hole 3] is formed in the structure shown in FIG. 7.

Next, a TiN film is formed on the entire surface by sputtering to a thickness of 0.1 μm, and then W (a high melting point metal A'3 such as Mo can also be used) is formed to a thickness of 0.6 μm by sputtering.

Here, the TiN film prevents the reaction between W and 81 and
It functions to improve adhesion with the SG film 12. The laminated film may be made of AQ, Cu alloy, etc. in addition to the above-mentioned high-melting point metal such as W, but the high-melting point metal such as W is
, Ag, etc. (desired in the lower wiring layer), and can withstand the high-temperature heat treatment in the process shown in FIGS. 9 and 11. In this example, W, etc. High melting point metals are used. Here, the resistance of W is higher than that of AQ gold alloy, Cu alloy, etc., and speeding up is somewhat problematic, but in this example, it is short to the lower wiring layer (first layer wiring IM11 and second layer wiring M12, which will be described later). Since wiring is mainly used, the influence on electrical characteristics is reduced. Thereafter, patterning is performed by a known photoetching method to form a second soil layer MMII, resulting in the state shown in FIG. This first scrap wiring Mll has wiring in the left and right directions in FIG. 8, and the pitch between the wirings shown in FIG. hand. ,ru.

Next, the entire surface was coated with SOG (Spin on Gla
ss) to a thickness of 0.3 μm and baked at a high temperature of 600° C. to solidify the SOG. Here, if the first layer wiring M11 is made of A, Q alloy, etc. instead of a high melting point metal such as W, it cannot withstand high temperature heat treatment than the high melting point metal such as the AQ gold alloy W, so the baking temperature is should be approximately 500°C. In that case, SOG with slightly weaker strength will be formed. SOG is applied thickly to the underlying recesses and is coated on the SOG film 3 as shown in Figure 9.
It is extremely effective in flattening the surface. Then, a film of 0.7 μm of S ]O is formed by a known plasma method to form the entire first interlayer insulating film 13, and the film thickness T of the first interlayer insulating film 13 is shown in FIGS. 2 and 3. , 1 to 1
．． It is set to 0 μm.

Next, using a known photoetch method, the first layer wiring Mll and the second /l! Through hole 3 connecting with iI wiring M12
After that, T'iN was formed on the entire surface by sputtering to a thickness of 0.16 μm, and then W
is formed by sputtering to a thickness of 0.6 μm. ” In addition to W, high melting point metals such as Mo and AQ gold alloy Cu
It is also possible to use alloys, but when using metals other than high-melting point metals (Af1 alloy, etc.), there are two problems:
That is, the required strength against elene 1-romigration is weakened, and the temperature of the subsequent high-temperature heat treatment is lowered, resulting in the formation of SOG with weak strength. Subsequently, patterning is performed using a known photoetching method to form the second Jl wiring M1.
2 and the state shown in FIG. 10 is obtained.

Here, the second layer wiring @M12 has wiring in the direction perpendicular to the drawing, and the pitch between the wirings PL2 shown in FIG.
is 3.0 μm.

In this way, the inter-wiring pitch P11. ．． The film thicknesses Tll of P12 and the first interlayer insulating film 13 are each shortened, and both the upper wiring layer Mll and the second wiring layer 12 are high-density wiring layers.

Next, SOG is applied to the entire surface to a thickness of 0.3 μm and baked at 600° C. to flatten the surface. Here, when the first layer wiring Mll and the second layer wiring M12 are made of AQ gold alloy instead of a high melting point metal such as W, the baking temperature is set to about 50° C. as described above. Then, by plasma CVD method, Sj○2 is formed into a 1.7 μm shape and the entire second interlayer insulating film 14 is formed, and the film thickness T12 of the second interlayer insulating film 14 shown in FIGS. 2 and 3 is set to 2. ．． OIim. Subsequently, a through hole 20 is formed using a known photoetching method,
The state shown in the first king map shall be established.

Next, W is selectively formed only in the through-hole portion 20 by a CVD method (a known method using Sil-I41g material of WF6). This method was used because the through hole 31.3 in the lower layer was used without increasing the diameter of the through hole 20.
The through hole 20 is formed by sputtering method similar to 2.
If the second interlayer insulating film 14 is thick, the inside of the through hole 20 will not be filled properly and there is a risk of disconnection, etc. To avoid this, the through hole 2o
If the diameter of i1. M12
This is because the second M wiring M12 has to be made thicker, making it impossible to achieve high density wiring layering of the second M wiring M12. Next, the Aa gold alloy was formed by sputtering Cu to a thickness of 0.8 μm.
Patterning is performed using a known photoetching method to form third layer wiring M13, resulting in the state shown in FIG. 12. Here, the third layer wiring M13 is arranged in the first layer j! Mll
Similarly, the receiver has wiring in the horizontal direction in the figure, and the pitch P13 between the wirings shown in FIG. 3 is 6.0 μm.

Next, the third interlayer insulating film 15 and the through holes 21 are formed in the same manner as in FIG. 11, resulting in the state shown in FIG. 3.

Next, the formation of W in the through-hole portion 21 and the fourth layer wiring M1
4 is formed in the same manner as in the case of FIG. 12, resulting in the state shown in FIG. 14. Here, like the second layer wiring M12, the fourth layer wiring M14 has wiring in the direction perpendicular to the figure, and the pitch P14 between the wirings shown in FIG. 2 is 6.0μ.
It has become m.

In this way, the pitch between the third M wiring MM1319- and the fourth layer wiring M14 constituting the upper layer, P1], Pi2, the film thickness T i 2 of the second interlayer insulating film 14, and the third interlayer bag edge film Since the film thickness T13 of the layer 5 is made longer, both the third layer wiring M1.3 and the fourth layer wiring M14 are low capacitance wiring layers.

Moreover, the third layer wiring M13 and the fourth layer wiring M]-4 are Af1
It is composed of alloy, Cu alloy, etc., and the lower layer is made of metal! Since the resistance is lower than that of the high melting point metal such as W that constitutes the metal, higher speeds are achieved.

As described above, the upper layer has a low capacity distribution #! ;A layer (third layer wiring M, 13, fourth layer wiring M14) and high-density wiring layer below the upper layer (first layer wiring M11, second M wiring M12)
are formed, and when the pansivation film 16 is coated on the semiconductor device shown in FIG. 14, 1.2.
A semiconductor device shown in FIG. 3 is obtained.

Here, the above-mentioned first to fourth N wirings Mll to M14 are DA(
The arrangement is determined by Design O 1 to Macyon).

In the automatic wiring of this embodiment, first, the first calendar gM11
．． ．． 2nd/1st WIt! The wiring capacitances of gM12, 3rd M wiring M13, and 4th N wiring M14 are shown in Tables 2 and 3 below, for example.
, are calculated in advance two-dimensionally from the adjacent conditions (surrounding conditions) as shown in Table 4 (these tables show examples in the case of a three-layer wiring structure), and then the first The delay time when wiring is performed using the layer wiring Mll and the second layer wiring M12 is calculated based on the sum of the wiring capacitances determined in advance, and if the result is a delay time larger than the design value, , the wiring is mainly used as the third layer wiring M13 and the fourth layer wiring MM14, and the layout of the wiring is determined.

Table 4 (Third Layer Wiring Capacitance) In this way, in this example, the wiring capacitance is calculated under the adjacent conditions (surroundings) by performing a two-dimensional simulation without performing the conventional three-dimensional simulation. Since the two-dimensional wiring capacitances are calculated in advance from the above (conditions) and the three-dimensional wiring capacitance is determined by the sum of the wiring capacitances, DA conversion can be easily performed.

Moreover, the third layer wiring M13 and the fourth layer wiring M14 are wiring layers that are perpendicular to each other, and the wiring is arranged in the same way as in the case of the conventional first layer wiring Mll and second layer wiring M], 2. Since there is a high degree of freedom when doing so, it has become extremely easy to convert it into DA.

According to the semiconductor device configured in this way, the following effects can be obtained.

In other words, two wiring layers (the third
Layer wiring M13 and fourth layer wiring M14) to a low capacitance wiring layer,
The wiring layer below the upper layer (fourth layer arrangement 1Mll and second
Since the M wiring M12) is arranged in each high-density wiring layer, high-speed operation can be achieved without electromigration in the upper low-capacitance wiring layer, while in the high-density wiring layer below the upper layer. Due to the effect that higher integration can be achieved, and by using a wiring material that is more resistant to electromigration than the upper layer, it is possible to simultaneously achieve high integration and high speed without causing a decrease in reliability.

In addition, since the upper low-capacitance wiring layer is composed of wiring layers in directions perpendicular to each other, the low-capacitance wiring layer can be wired with a greater degree of freedom.
(Design Automation) and easy manufacturing.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, in the above embodiment, an example of application to a semiconductor device having four wiring layers is described, but the present invention is applicable to a semiconductor device having five wiring layers.
Of course, the present invention can also be applied to a semiconductor device having more than one wiring layer. In this case as well, it goes without saying that the low capacitance wiring layer is constituted by the wiring layers in the upper layer in directions orthogonal to each other. In this case, it is also possible to configure the wiring layer with three wiring layers (an odd number), which are orthogonal to each other, the fifth layer, the sixth layer, and the seventh layer.

Further, in the above embodiment, when the time calculated based on the sum of the wiring capacitances becomes a delay time larger than the design value, the wiring is connected to the third layer wiring M13 and the fourth layer wiring M1.
4 is mainly used, but it is simply used when the wiring length is longer than a certain reference length that has been set.
13, the fourth layer arrangement 1M14 may be used.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in a semiconductor device in which four or more wiring layers handling electrical signals are laminated, the wiring layers in the upper layer in directions perpendicular to each other are called low-capacitance wiring layers, and the wiring layers below the upper layer are called high-density wiring layers. As a result, high speed can be achieved in the upper low capacitance wiring layer without electromigration, while high integration can be achieved in the high density wiring layer below the upper layer. As a result, it becomes possible to achieve high integration and high speed at the same time without causing a decrease in reliability.

Furthermore, since the two low-capacitance wiring layers are composed of wiring layers in directions perpendicular to each other, the low-capacitance wiring layers can be routed with a greater degree of freedom, making it easier to use DA (design automation) for wiring. This makes it possible to easily manufacture the product.

[Brief Description of the Drawings] The first construction drawing is a top view of an embodiment of the semiconductor device according to the present invention, FIG. 2 is a sectional view taken along the line CC in FIG. 1, and FIG. D sectional view, FIG. 4 is a diagram of the relationship between interlayer insulating film thickness and interconnect capacitance when the pitch between interconnects is used as a parameter, and FIGS. 5 to 14 are steps showing the method for manufacturing a semiconductor device according to the present invention. 15 is a top view of a conventional semiconductor device, FIG. 16 is a sectional view taken along line A-A in FIG. 15, and FIG. 17 is a cross-sectional view taken along line B in FIG.
-B sectional view. Mll, M12... Wiring layer below the upper layer (high-density wiring layer), M13. M14... Upper wiring layer (low capacitance wiring layer)

Claims (1)

[Claims] 1. In a semiconductor device in which four or more wiring layers for handling electrical signals are laminated, the upper wiring layers in directions orthogonal to each other are low capacitance wiring layers, and the wiring layers below the upper layer are low capacitance wiring layers. A semiconductor device characterized in that it is configured to have high-density wiring layers. 2. The semiconductor device according to claim 1, wherein the pitch between wires in the low-capacitance wiring layer is larger than that in the high-density wiring layer. 3. The interlayer insulating film in the region where the low capacitance wiring layer is formed is thicker than that in the region where the high density wiring layer is formed. The semiconductor device according to item 2.