JPH0338169A - Signal processing circuit for solid-state image pickup device - Google Patents

Abstract

PURPOSE:To reduce the period below a line period in which most of noise exists by providing a control circuit supplying a timing signal for A/D conversion to an A/D converter and supplying a calculation command subtracting a digital signal for a picture output period and an arithmetic data for a pause period read from a memory to a digital arithmetic circuit. CONSTITUTION:An arithmetic logic circuit (ALU) 31 accumulates zero level data Z1-Z4 corresponding to four picture elements with an arithmetic instruction from a control circuit 25 and the resulting accumulated value is divided by 4 when the zero level data Z4 is calculated to calculate the mean value of the zero level data Z1-Z4. The mean value of the zero level data Z1-Z4 is stored tentatively in a memory 24 provided newly. Succeedingly, the ALU 31 reads the zero level mean value data stored in the memory 24 every time picture data D1-D4 being valid signals are inputted by one picture element each and the mean value is subtracted from the input picture data. Thus, a picture data (processed pickup signal) in which the zero level fluctuation in one line period is reduced is extracted from the ALU 31.

Description

[Detailed Description of the Invention] (Summary) Regarding a signal processing circuit for reducing noise included in an image pickup signal, the l11g1 with a period less than line circumference II is provided with an inexpensive configuration.
(The purpose of this is to reduce noise in No. 8, and is an imaging signal in which an image output period and a rest period appear sequentially in each line period from an imaging unit having multiple rows of solid-state imaging devices in a -dimensional or two-dimensional array. A signal processing circuit of the solid-state Ill imaging device that extracts the image signal and reduces noise in the image signal, converts the output image signal of the image pickup unit into a digital signal for each of the image output period and the pause m. a D converter, a digital arithmetic circuit which is supplied with the output digital signal of the A/D converter and performs digital arithmetic operations, and temporarily stores the arithmetic data of the image pickup signal of the pause bright P1 obtained by the digital arithmetic circuit. A timing signal for A/D conversion is supplied to the memory and the A/D converter, and the image output m is supplied to the digital arithmetic circuit.
and an 11111 circuit that supplies an arithmetic instruction to subtract the digital signal between and the arithmetic data of the pause period read from the memory, and receives the processed I#iI& signal with reduced noise from the digital arithmetic circuit. Configure to obtain.

[Industrial application field]

The present invention relates to a signal processing circuit for a solid-state m-image device, and particularly to a signal processing circuit for a solid-state m-image device.
In a 1° infrared 1jlffi imaging device related to a signal processing circuit for reducing t# sound included in a ll image signal, a function is required not only to visualize the imaging target but also to detect the temperature of the VRI image target. . Therefore, the output signal of the infrared sensing element needs to be low noise and stable over a long period of time.

[Conventional technology]

The noise contained in the output signal of the infrared sensing element is mainly caused by: - Random coupling generated by the element itself, - Noise caused by fluctuations in the signal 3 for driving and controlling the infrared sensing element, and - Temperature fluctuations in the device. This consists of offset fluctuations in the output signal of the infrared sensing element due to this, and (2) N magnetic induction noise mixed in from the outside.

Among these noises, in-phase components in which the effective signal portion and invalid signal portion of the output signal of the infrared detection element fluctuate in the same way at the same time and low frequency components have traditionally been processed using the following signal processing circuit. had been removed.

Figure 4 is a one-dimensional array photoden* (PC: Photo.

1 is a circuit diagram of an example of a signal processing circuit of a conventional imaging device using a conductive type infrared sensing element.

In the figure, 10 is a one-dimensional array pca infrared detection element, n
Infrared sensing elements (light receiving elements) 101 to 10π are arranged in a straight line, and bias currents 11 to 1■ are applied to each infrared sensing element.

Each of the n infrared sensing elements F101 to 10n has amplifiers 111 to 11π and capacitors 121 to 12 on the output terminal side.
T1. Switch SW+~SWπ, amplifier 13+~1
3n are connected in cascade.

This I-image device creates a two-dimensional image by scanning the viewing suspension in one-dimensional direction using a vibrating mirror or the like.

For this reason, infrared sensing element? Output signal a from 10+ to 10π
As shown in FIG. 5(A), during one frame period 12, in addition to the effective signal a obtained by scanning, there is a return vt of the vibrating mirror.
Invalid beliefs @b appear due to questions etc.

During the period m during which this invalid signal appears, the bias current [+~Iy
+ is stopped, and the output of the infrared sensing elements 101 to 101+ (
Set g to zero, and then switch SW +~
By turning off the 5WTl as schematically shown in FIG. 5(B), the signal level between m can be newly clamped as a pyro level. As a result, as shown in FIG. 5(C), it is possible to extract 07@ from which the t# sound has been removed from the fluctuations in the Kugero level (indicated by C in FIG. 5(A)) from Ann 1131 to 13π.

FIG. 6 shows another conventional example of a CCD (Charge
A circuit diagram of a signal processing circuit of a prisoner transport device using a coupled device type infrared sensing element is shown.

In the figure, 151 to 151 are CCD type infrared detection elements,
- A total of n pieces are arranged on a straight line. Reference numeral 16 denotes a signal transfer COD, which is provided corresponding to the infrared detection elements 151 to 15n.

The electric charge obtained by photoelectrically converting the infrared rays by the infrared detecting elements 151 to 15Tl is transferred in parallel to the signal transfer C0D 16, and further transferred serially from this to the seventh amplifier 17. As shown in FIG. 7(A), the imaging signals taken out serially from the signal transfer CCD 16 are transmitted from line 1 to line k during a pause period t during one frame l1.
The signals of one line are taken out sequentially through the infrared detecting element 1 as shown in FIG.
The signals from pixels 1 to n corresponding to 51 to 15□ are synthesized in time series.

Here, as shown in FIG. 7(B), the signal output period of each pixel consists of a zero level period fJ j o and an effective No. 8 output period ts. Therefore, the image pickup signal taken out from the amplifier 17 in FIG. 6 is supplied to the ripple hold circuit 18, and the zero level period t is set as shown in FIG. 7(C).
After the signal level between the pillow levels is sampled by a sampling pulse output for a period corresponding to o, it is held and supplied to the subtracter 19, where it is subtracted from the imaging signal from the amplifier 17 by 11.

As a result, as shown in FIG. 7(D), the subtracter 19 extracts a zero level fluctuation, that is, an imaging signal in which noise has been canceled, and outputs it to the output terminal 20.

(Problem to be Solved by the Invention) However, since the conventional circuit shown in FIG. 4 clamps the zero level for each frame, it is not possible to remove level fluctuations in period II, which is shorter than the frame period. , noise removal was insufficient.

Furthermore, although the conventional circuit shown in FIG. 6 can eliminate short-cycle level fluctuations, the frequency band of the sample-and-hold circuit 18 must be widened because the sampling pulse cycle is short and the gap between samples is also short. There was Cao. For this reason, the g/# sound generated in the sample bold circuit 18 increases, and the overall noise may increase. Furthermore, the high-speed sample-and-hold circuit 18 is expensive, causing an increase in cost.

The present invention has been made in view of the above points, and an object of the present invention is to provide a signal processing circuit for a solid-state imaging device that can remove noise in an image signal having a cycle equal to or less than the line cycle with an inexpensive configuration. do.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. Reference numeral 21 denotes a seed image section, which is composed of a plurality of rows of solid-state VA image elements arranged in a -dimensional or two-dimensional array, and outputs a lie image in which an image output period of 1 g and a rest period of 1 m appear sequentially in each line period.

22 is an A/D converter that converts the above-mentioned imaging signal into a digital signal. A digital arithmetic circuit 23 performs a digital arithmetic operation on the digital signal to obtain a processed image signal.

Reference numeral 24 denotes a memory that temporarily stores calculation data regarding the image pickup signal 8 during the pause r#. Reference numeral 25 denotes a control circuit which supplies a timing signal for A/D conversion to the A/D converter 22 and outputs an image output signal 151 to the digital arithmetic circuit 23.
An arithmetic instruction is supplied to subtract the digital signal from the arithmetic data read from the memory 24.

As described above, in the present invention, after calculating the digital signal during the pause 11 and temporarily storing it in the memory 24, the digital calculation circuit 23 subtracts the digital signal for the next image output period and the data read from the memory 24. The processed Ill times signal obtained is output.

[For n]

11 [1 line JI of the imaging signal output from the 1 section 21
The rest period al in III is between JFJ and JFJ generated by the fffi number transfer operation, and does not include image information from the object to be imaged and indicates the zero level of the silver image signal. Moreover, this pause period lasts for each pixel during the t(o level 11 (see Fig. 7)).
B) is 1 minute longer than jo).

On the other hand, in most cases in conventional solid-state imaging devices, A/
Dv! The converter 22 and the digital arithmetic circuit 23 are already provided and are used for subtraction to correct offset variations for each pixel signal, multiplication to correct sensitivity variations, and the like.

Therefore, in the present invention, we focus on this pause WI, and
Using the A/D converter 22 and digital performance circuit 23, the timing of the 111 circuit 25 ( change the number, and
A memory 24 is provided to store the A/D-converted l1l11 signal (biO level signal) of the pause incision, and a digital arithmetic circuit performs a reduction operation of subtracting the low level signal from the digital signal of the next image output period. The control circuit 25 is configured to output an arithmetic instruction to be performed by the control circuit 23.

As a result, in the present invention, by only making slight changes such as adding the memory 24, the digital performance circuit 23 can output a 1-line long-range image and a processed image with reduced zero-level fluctuations in the 1-row imaging signal. signal can be extracted.

〔Example〕

FIG. 2 shows a configuration diagram of an embodiment of the present invention. In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. In Figure 2, 281 to 28y+ are n C
It is a CD type infrared sensing element, and is arranged in a one-dimensional array in a negative column. Reference numeral 29 denotes a 4:3 transfer CCD, which is provided corresponding to the infrared detection elements 281 to 28m.

Infrared detection element 281-28m and CCD 2 for signal transfer
The structure of the imaging section 21 consisting of 9 is the same as the conventional one-dimensional array infrared mis section shown in FIG. The waveforms shown in FIGS. 3A and 3B are similar to those shown in FIGS. 3A and 8).

As shown in Fig. 3<A), the imaging signal No. 1 is a two-dimensional image signal obtained by the known main scanning and a1 scanning, and each line imaging signal from line 1 to line k constitutes a 1° frame. In addition, as shown in FIG. 3(B), the imaging signal U of each line period r1, the signal of the line pause incision ta for each line, and the n infrared detecting elements 281~
The effective signal 8 of the image output period tb is obtained by using 28π as pixels.

This image pickup signal is amplified by a filter amplifier 30 as shown in FIG. Pause JHitta&: Image output Jfll even if you leave it! I
AID conversion is performed at the same timing as .

Here, it is assumed that the timing signal is output four times during the rest period 11 ta, so the A/D converter 22 outputs the timing signal during the rest period r51 ta as schematically shown in FIG. 3 ([)).
Four zero level data Z+ to Z4 are obtained. In addition, as schematically shown in FIG. 3(D), image output) Htb
In this step, image data of D+-D1+ (valid signal 3) is obtained from the A/D converter 22.

The output data of the A/D converter 22 described above is transmitted to the Ensonron Egg circuit (
Supplied to ALLJ>31. Here, the A 131 and the memory 32 constitute conventionally known correction means for performing subtraction for correcting onoset variations for each pixel data, multiplication for correcting sensitivity variations, and the like.

In this embodiment, the ALU 31 further receives the Z0 level data Z corresponding to 4 pixels in response to a calculation instruction from the W circuit 25.
1 to z4 are integrated, and when the zero level data Z4 is collected, this 8% calculated value is set to "4"#Ii to calculate the average value of the zero level data z1 to Z4. The average value of the above pillow level data 21 to ZJ is temporarily stored in a newly provided memory 24.

Subsequently, the ALLI 31 reads out the zero level average value data stored in the memory 24 and inputs the input image data every time f pixels of the image data D1 to D, which are valid signals, are manually input. and subtract. As a result, A.L.
Image data (processed m-image signal) with reduced zero level fluctuation within one line period is extracted from U31.

In this embodiment, the imaging signal of the pause period 1jfl j a for each line is collected as multiple columns of digital data Z+=74 representing the zero level, and the average value is subtracted from the image data. , zero level strange vJ
Random noise other than the above can be removed.

In addition, as in the conventional circuit shown in FIG.
Since the signal of the level period (indicated by to in FIG. 7(B)) is not sampled and held, the sample-and-hold circuit 18 and the subtracter 19 are not required, and the noise generated from these circuits 18 and 19 is eliminated. Can be removed.

Further, in this embodiment, the amplifier 30. Since offset fluctuations in the signal due to temperature fluctuations of the A/D converter 22 itself are sampled as zero level fluctuations, offset fluctuations in the signal due to temperature fluctuations can also be reduced at the same time.

Furthermore, the present invention adds a memory 24 with small capacity loss and
Since this can be realized by only partially changing the control timing of one circuit 25, there is almost no increase in cost.

It should be noted that the present invention is not limited to the above-mentioned embodiments; for example, the imaging section 21 may be of a secondary arrangement in which a large number of CCD-type infrared sensing elements are arranged in a matrix. . Further, although it is most effective when applied to a CCD type infrared sensing element, it is also applicable in principle to other visible light solid-state imaging elements.

〔Effect of the invention〕

As described above, according to the present invention, zero-level fluctuations in the effective signal portion of image output period 1 in each line period are suppressed, thereby reducing noise in periods shorter than the line period, which account for most of the noise. In addition, since the effective signal component of the image output period is subtracted by the average value of the pillow level of 1llllJ, which is longer than the conventional method, the effective signal component of the image output period is not affected by random noise other than the pillow level fluctuation, and the period less than the line period Noise caused by temperature changes in circuit components! In addition, since a sample and hold circuit is not required, noise generated in the sample and hold circuit can be removed. Furthermore, according to the present invention, the A
/D converter and digital arithmetic circuit can be used, and the present invention can be implemented with only a small memory for storing zero-level data as an additional circuit, so expensive circuit parts such as sample and hold circuits can be eliminated. Together, these features include being able to be constructed at low cost.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention; Fig. 2 is a configuration diagram of an embodiment of the present invention; Fig. 3 is a time chart for explaining the operation of Fig. 2; Fig. 4 is a circuit diagram of a conventional example; Figure 5 is a time chart for explaining the operation of Figure 4, Figure 6q
A circuit diagram of another conventional example, FIG. 7 is a time chart for explaining the operation of FIG. 6. In the figure, 214 is an imaging unit, 22 is an A/D converter, 23 is a digital arithmetic circuit, 24 is a memory, 25 is a control circuit 1, and 281 to 28Tl are infrared detection elements. Half-play l principle figure, 72-cut figure line method - / PI's turn figure 4
Fig. 5. APl with the force of the clothes is placed ゛ times.

Claims (1)

[Scope of Claims] An imaging signal in which an image output period and a pause period appear sequentially in each line period is extracted from an imaging unit (21) having a plurality of rows of solid-state imaging devices in a one-dimensional or two-dimensional array, and the imaging signal is In a signal processing circuit of a solid-state imaging device that reduces noise in a solid-state imaging device, an A/D converter (22) converts an output imaging signal of the imaging unit (21) into a digital signal for each of the image output period and the rest period. and a digital arithmetic circuit (23) to which the output digital signal of the A/D converter (22) is supplied and performs digital arithmetic operations; and a digital arithmetic circuit (23) that performs digital arithmetic operations on the imaging signal obtained during the rest period by the digital arithmetic circuit (23). Memory for temporarily storing data (2
4), supplying a timing signal for A/D conversion to the A/D converter (22), and supplying the digital signal of the image output period and the memory to the digital arithmetic circuit (23); A control circuit (25) supplies an arithmetic command to perform subtraction with the arithmetic data of the pause period read from the digital arithmetic circuit (23), and receives a processed image signal with reduced noise from the digital arithmetic circuit (23). A signal processing circuit for a solid-state imaging device, characterized in that: