JPH0337717A - Arithmetic circuit - Google Patents

Abstract

PURPOSE:To check trouble by providing a dual carry look ahead circuit (CLA) to check results and inputting the same random numbers to inputs of respective 4-bit ALUs at the time of executing a micro instruction accompanied with no arithmetic operations and comparing results of ALUs with one another to check them. CONSTITUTION:When a micro instruction is an arithmetic instruction, an output signal 31 of a decoder 3 is '0'. Each of selectors 5a to 5h selects and outputs X and Y inputs, and a CLA 2a generates carry-in signals C0 to C2 in accordance with a carry generation function signal G1 and a carry propagation signal P1 of each ALU, and arithmetic results Z (0 to 16) are calculated by carry-in data and input data. Simultaneously, values of CLAs 2a and 2b are compared with each other by a comparator 7 to check the abnormality. Unless the micro instruction is an arithmetic instruction, comparators 6a and 6b compare output results of ALUs 1a and 1b and those of ALUs 1c and 1d. Thus, trouble is checked.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an arithmetic circuit used in an information processing device.

[Conventional technology]

Conventionally, this type of arithmetic circuit has a method of duplicating the arithmetic circuit in order to prevent incorrect output data due to failure.

Alternatively, a parity prediction means is used that predicts the parity of an output value from input data and its parity.

The arithmetic circuit duplication means has two series of the same arithmetic circuit, applies the same input data, compares the output results, and checks whether they match.

The parity prediction means is a method of predicting and outputting the input data, its parity, the arithmetic function element, and the parity of the output result, and comparing the arithmetic result area with the generated parity to check whether there is any abnormality in the arithmetic unit.

[Problem to be solved by the invention]

However, both of the above-mentioned conventional means have the drawback of requiring a large amount of hardware, and are often not actually adopted in small computers and the like where the amount of hardware is limited. Further, although the parity/prediction means requires less hardware than duplication, only parity is checked, so there is a problem that 2-bit errors cannot be detected.

The present invention is an attempt to solve the above-mentioned problems of the conventional circuits, and provides an arithmetic circuit that can perform failure checking with a small amount of hardware.

[Means to solve the problem]

The arithmetic circuit of the first invention is an arithmetic circuit having a plurality of arithmetic units that perform arithmetic operations in units of several bits and a carry look-ahead circuit that generates carry-in signals for the six arithmetic units based on carry information of each arithmetic unit. means for comparing the output values of the two carry look-ahead circuits, a random number generation circuit that generates a carry-in signal and a random number equal to the number of input bits of the arithmetic unit, and the arithmetic operation circuit. an instruction decoding means for determining whether or not an arithmetic instruction uses an arithmetic operation; a selection circuit for selecting test data and a carry-in signal generated by the random number generation circuit for each arithmetic unit according to instructions from the decoding means; It is configured to include comparison means for comparing output results.

Further, the arithmetic circuit of the second invention includes a plurality of arithmetic units that perform arithmetic operations in units of several bits, and a carry look-ahead circuit that generates carry-in signals of the six arithmetic units based on carry information of each of the six arithmetic units. The circuit includes two sets of carry lookahead circuits, means for comparing output values of the two carry lookahead circuits, a ROM for storing test input data and carry-in signals of each of the arithmetic units, and a ROM for storing test input data and carry-in signals of each of the arithmetic units; an instruction decoding means for determining whether or not an arithmetic instruction uses a circuit; an address counter in a ROM that performs a counting operation according to instructions from the decoding means; It is comprised of a selection circuit for selecting a signal and a comparison means for comparing the output results of each of the arithmetic units.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a configuration diagram of an embodiment of the first invention. This arithmetic circuit calculates X (0:16) and Y (0:16) based on microinstructions stored in a control storage circuit (not shown).
) is a 16-bit arithmetic circuit that outputs data of (for example, addition) L, z (0:16).

This 16-bit arithmetic unit is a 4-bit ALU 1a.

lb, 1c, ia, carry-in data from the lower order of each AI, H, carry generation function signal Gl in each bit ALU
(t=o~3) and a carry look ahead circuit (carry look ahead circuit (hereinafter abbreviated as /CI, A) 2a that is generated by a carry propagation function signal P.

of Consisting of 2b. CLA2a and 2b are the same circuit.

CLA2a and C! The output value of LA2b is compared and checked by comparator 7.

The instruction decoder 6 is a decoder that determines whether to execute a microinstruction or to use an arithmetic circuit.

When it is not an arithmetic instruction, "1" is supplied to the i signal line 31. The random number generation circuit 4 sends test data to each arithmetic unit input valve, each 4
A total of 9 bits, including bits and 1 bit of carry-in data, are generated.

Selector 5a+5b+5c+5d, 5c+5ct5g+
5h is the input signal selector for ALU Ia, lb, 1c, Id, and when the signal line 51 is @0'', x (0:16), Y
(Divide 0:1(S) into 4-bit units and send 1
”, the value generated by the random number generation circuit 4 is supplied to each ALIU.

When the signal line 61 is "1", the comparator 6a
Check the comparison between the output signal Z (0:4) of 1a and the output signal Z (4:4) of ALUlb.

1 [When the signal line 31 is "1", the conoparator 6b
ALU Ic output signal z (8:4) and ALU 1a
Compare and check the output signal z(12:4)e. Selectors 8a, 8b, and 8c are CLA when signal line 1 is "0".
The signal line 31 carries out the carry-in data generated by 2a.
When the signal line 31 is 1'', test carry-in data generated by the random number generation circuit 4 is selectively supplied to each ALU.The gate 9 is an AND gate that similarly supplies test carry-in data when the signal line 31 is 1''. be.

Next, the operation of this arithmetic unit will be explained.

When the microinstruction is an arithmetic instruction, the output signal 51 of the decoder 6 becomes 0''.Each input selector 5a+5b, 5c+
5a, 5e, 5ft 5g + 5h from Pi, carry-in signal co + c, l C2 is generated by CLA2a, processed into carry-in data and input data, and the calculation result z(o:
ib) is calculated.

At the same time, the values of CLA Za and 2b are compared by a comparator to check for any abnormality.

If the microinstruction is not an arithmetic instruction, the output signal 31 of the decoder 3 becomes "1". Each ALU receives random numbers generated by the random number generation circuit 4 and performs calculations. If the failure is eliminated, the same output result will be calculated. Comparators 6a and 6b are A
Compare the output results of LU Ia and 1b and the output results of ALUIC and 1d to check for any abnormality.

FIG. 2 is a configuration diagram of an embodiment of the second invention.

The same reference numerals as in FIG. 1 indicate the same components.

The parts not explained in FIG. 1 will be explained below.

Selectors 5a, 5b, 5c+5ct, 5e, 5f.

5g and 5h are the input data selectors of ALUla, 1b, IC, 1d, and when the signal line 61 is 0'', X (0:16)
, Y (0:16) are divided into 4-bit units and supplied to the ALU, and when it is "1", the output data of the ROM 10 is supplied to each ALU.

The gate RO unit 10 is a read-only memory having a width of 9 bits and a configuration of 16 hoods, and stores test data as shown in FIG. 3 suitable for detecting failures in the ALU. The address of the ROM 10 is indicated by an address counter 11. This counter 1 is a 4-bit wide counter that performs a count-up operation every cycle when the signal line 31 is 1''.

Selectors 8a, 8b, and 8c are ALUs 1a and ib.

A selector that supplies carry-in data to 1C carry-in input co, C1, and C2, and when signal line 31 is 0'',
The carry-in data generated by CLA2a is transferred to the signal line 31.
When is "1", the carry-in data output from the ROM 10 is selectively supplied. When the signal line 31 is "1", the gate 9 supplies the carry-in data of the ROM 10 to the ALU 1d in the same way as in 2.

Next, the operation of the arithmetic circuit of the present invention will be explained.

When the microinstruction is an arithmetic instruction, the output signal 31 of the decoder B becomes 10". Each selector 5a, 5b, 5c, 5
a, 5e, 5t', 5g, 5h are respectively x (0:16
), y' (0:16) is selected and output, a carry-in signal CO+C1+02iCLA2a is generated from the carry generation function signal G1 of each ALU and the carry propagation signal Pl, and the calculation result Z(0: 16)
is calculated. At the same time, the values of 0LA2a and 0LA2b are compared by a comparator 7 to check for any abnormality.

If the microinstruction is not an arithmetic instruction, the output signal 61 of the decoder 6 becomes "1", and the selectors 5a+5b+5c,
5d, 5e,! ! . Similarly, the carry-in signal of each ALU is
Ten data are selectively supplied, and each ALU outputs the same operation result based on the same input data.

Comparators 6a and 6b are ALUla and ib.

1c and 1d are compared and checked to see if there is any abnormality in each ALU.

If the data to be tested is not an arithmetic instruction, it changes every cycle and provides data suitable for fault detection.
LU abnormalities can be detected immediately.

〔Effect of the invention〕

As explained above, in the first nine inventions, only the CLA is duplicated and the result is checked.

4-bit ALU each when executing microinstructions that do not perform operations
By inputting the same random number to each input and comparing and checking the results between 4-bit ALUs, the second invention doubles only the ODA, checks the results, and tests the ALU in 4-bit units. Each AI is equipped with a ROM'i that stores data to be executed.

A case where the arithmetic circuit is completely duplicated by giving the same test data to U and comparing the results.

The parity prediction circuit can check for failures in the arithmetic circuit with a smaller amount of Hw than is required, which has the effect of increasing the reliability of the information processing device.

[Brief explanation of drawings]

1 and 2 are block diagrams of an embodiment of the first and second inventions, and FIG. 3 is a pattern diagram of an example stored in the ROM in FIG. Explanation of symbols: 1a, 1b, 1c, ta-1, 4-bit ALU, 2a, 2b... Carry look ahead circuit, 3...
Microinstruction decoder, 4...Random number generation circuit, 5a. 5b, 5c, 5a, 5e, 5f, 5g, 5h, 8a, 8
b. 8c...Selector, 6a, 6b, 7...Comparator. 9...AND gate, 10...ROM, 11...
address counter.

Claims (1)

[Claims] (1) In an arithmetic circuit having a plurality of arithmetic units that perform arithmetic operations in units of several bits, and a carry look-ahead circuit that generates a carry-in signal for each of the arithmetic units from carry information of each of the arithmetic units,
means for comparing the output values of the two carry look-ahead circuits, a random number generation circuit that generates a carry-in signal and a random number equal to the number of input bits of the arithmetic unit, and the arithmetic operation circuit. an instruction decoding means for determining whether or not an arithmetic instruction using and comparison means for comparing the output results of the calculator. (2) In an arithmetic circuit consisting of a plurality of arithmetic units that perform arithmetic operations in units of several bits, and a carry lookahead circuit that generates a carry-in signal of each arithmetic unit from carry information of each arithmetic unit, the carry lookahead circuit means for comparing the output values of the two respective carry look-ahead circuits, and an RO storing test input data and carry-in signals of the arithmetic unit.
M, an instruction decoding means for determining whether or not an arithmetic instruction uses the arithmetic circuit, an address counter of the ROM that performs a counting operation according to instructions of the decoding means, and an address counter stored in the ROM for each of the arithmetic units. An arithmetic circuit comprising: a selection circuit for selecting input data and a carry-in signal; and comparison means for comparing output results of each of the arithmetic units.