JPH0336746A - Wafer probe - Google Patents

Wafer probe

Info

Publication number
JPH0336746A
JPH0336746A JP17231589A JP17231589A JPH0336746A JP H0336746 A JPH0336746 A JP H0336746A JP 17231589 A JP17231589 A JP 17231589A JP 17231589 A JP17231589 A JP 17231589A JP H0336746 A JPH0336746 A JP H0336746A
Authority
JP
Japan
Prior art keywords
probe needle
needle
shape
semiconductor device
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17231589A
Other languages
Japanese (ja)
Inventor
Masashi Sato
正志 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP17231589A priority Critical patent/JPH0336746A/en
Publication of JPH0336746A publication Critical patent/JPH0336746A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To prevent the time for deciding whether or not the shape and position of a probe needle is satisfactory from overlapping with the time for measuring and testing a semiconductor device by providing a mechanism for recognizing the shape and position of the probe needle and conducting a composition and judgement with a normal shape and position. CONSTITUTION:The shape and position of a normal state probe needle 12 are stored using a camera 1 and an image processing circuit 8. For decision of whether or not the probe needle 123 is satisfactory, the shape and position of the probe needle 12 are again incorporated at that time and compared with image data at the normal state of the same. The result is fed to a body control circuit through a control circuit 9. For timing for performing a needle check, the incorporation of the normal state is done at a time when a probe card 4 is exchanged or before the measurement and testing of the semiconductor device, and for decision of whether or not the probe needle is satisfactory, it can be done at arbitrary timing in the measurement and test of the semiconductor device.

Description

【発明の詳細な説明】 [産業上の利用分野1 ウェハ上に形成された半導体装置の電気的特性及び機能
を測定、試験するためのウェハープローバーに関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a wafer prober for measuring and testing the electrical characteristics and functions of semiconductor devices formed on a wafer.

【従来の技術] 従来針チェック機構を備えたプローバーはなかった。そ
の代用として測定、試験後にパッドについた針路を画像
処理技術を用いてチェックすることにより、測定、試験
の信頼性を保証していた。
[Prior Art] Conventionally, there has been no prober equipped with a needle check mechanism. Instead, the reliability of the measurements and tests was guaranteed by checking the course on the pad using image processing technology after the measurements and tests.

[発明が解決しようとする課題] しかしながら従来の技術では。[Problem to be solved by the invention] However, with conventional technology.

(1)実際に針跡をつけてみないと良否の判断ができな
いため、プローブ針が既に変形していた場合、ウェハー
に致命的なキズをっけてしまうおそれがある。
(1) Since it is impossible to judge whether the probe is good or bad without actually making a needle mark, if the probe needle is already deformed, there is a risk of fatal scratches on the wafer.

(2)測定、試験前やウェハー交換後の最初のチェック
は、あらかじめ決めておいたチェック用の半導体装置を
用いるため、時間が無駄になる。
(2) The first check before measurement or testing or after wafer exchange uses a predetermined semiconductor device for checking, which wastes time.

という問題点を有していた。There was a problem.

そこで、本発明は従来のこのような問題点を解決するた
め、 (1)ウェハーにプローブ針を接触させる以前にプロー
ブ針の形状及び位置の良否を判断する。
In order to solve these conventional problems, the present invention has the following objectives: (1) Before bringing the probe needle into contact with the wafer, it is determined whether the shape and position of the probe needle are good or bad.

(2)(1)のための時間を半導体装置の測定、試験の
時間にくい込ませない。
(2) The time for (1) should not be added to the time for measuring and testing semiconductor devices.

ことを目的とする。The purpose is to

[課題を解決するための手段] 本発明のウェハープローバーは、 (1)プローブ針の形状及び位置を認識し、正常な形状
及び位置との比較判断する機構(以下「針チェック機構
」と記す)を設けた。
[Means for Solving the Problems] The wafer prober of the present invention includes: (1) a mechanism that recognizes the shape and position of the probe needle and compares and judges the shape and position with the normal shape and position (hereinafter referred to as "needle checking mechanism"); has been established.

(2)前記針チェック機構に、画像取込用カメラ、照明
、画像処理回路を備えた。
(2) The needle check mechanism is equipped with an image capturing camera, lighting, and an image processing circuit.

(3)前記画像取込用カメラを複数台異なる位置に設け
た。
(3) A plurality of the image capturing cameras were provided at different positions.

(4)前記画像取込用カメラを前記プローブ針の取り付
け位置に対して、垂直下方向と、水平方向の二ケ所に設
けたこと を特徴とする。
(4) The image capturing camera is provided at two locations, one vertically downward and the other horizontally relative to the probe needle attachment position.

[作 用] 本発明は以上のような機構を有するので、前述針チェッ
ク機構により、針跡を試しにつけてみる必要がなくなり
、半導体装置の測定、試験時間を無駄にすることがなく
なるとともに、変形したプローブ針でウェハーにキズを
つけてしまうことら未然に防ぐことができる。
[Function] Since the present invention has the above-described mechanism, the needle check mechanism eliminates the need to test needle marks, eliminates wasted time for measuring and testing semiconductor devices, and prevents deformation. This prevents the wafer from being scratched by the probe needle.

〔実 施 例] 第1図は本発明のウェハープローバーの横断面図、第2
図は本発明のウェハープローバーの横断面図、第3図は
本発明のウェハープローバーの制御系ブロック図である
。以下図面にそって実施例を説明する。制御回路9は本
体制御回路11と接続されており、針チェックの動作を
コントロールする。針チェックの方法として、 (1)正常な状態のプローブ針12の形状及び位置をカ
メラl及び画像処理回路8にて記憶する。そのとき画像
を鮮明に取り込めるように、照明2をオンする。
[Example] Figure 1 is a cross-sectional view of the wafer prober of the present invention, and Figure 2 is a cross-sectional view of the wafer prober of the present invention.
The figure is a cross-sectional view of the wafer prober of the present invention, and FIG. 3 is a block diagram of the control system of the wafer prober of the present invention. Examples will be described below with reference to the drawings. The control circuit 9 is connected to the main body control circuit 11 and controls the needle check operation. As a needle check method, (1) The shape and position of the probe needle 12 in a normal state are memorized by the camera l and the image processing circuit 8. At that time, the lighting 2 is turned on so that the image can be captured clearly.

(2)プローブ針12の良否の判断は、その時点におい
て再度(1)と同様にプローブ針12の形状及び位置を
取り込み、正常な時の画像データと比較して良否を判断
する。
(2) To judge whether the probe needle 12 is good or bad, at that point, the shape and position of the probe needle 12 are taken in again in the same manner as in (1), and compared with normal image data to judge whether the probe needle is good or bad.

(3)(2)の結果を制御回路9を通し本体制御回路に
伝える。
(3) The result of (2) is transmitted to the main body control circuit through the control circuit 9.

針チェックの実施のタイミングとしては、正常な状態の
取り込みは、プローブカード4を交換した時点、または
半導体装置の測定、試験の前とし、良否の判定について
は、半導体装置の測定、試験中の任意のタイミングで可
能とする1以上のタイミングは、本体制御回路11より
制御回路9をコントロールする。そして制御回路9より
の良否の結果に応じて、測定、試験の中止、アラーム発
生等の処理を行なう。
The timing of the needle check is to capture the normal state when the probe card 4 is replaced or before the measurement or test of the semiconductor device, and to determine the pass/fail condition at any time during the measurement or test of the semiconductor device. The main body control circuit 11 controls the control circuit 9 to enable one or more timings. Then, depending on the pass/fail result from the control circuit 9, processing such as stopping the measurement or test or generating an alarm is performed.

次にカメラ1の取り付け位置について示す。プローブ針
12の形状の異常が問題になる場合は、(1)半導体装
置の試験用パッドとプローブ針12の位置関係が狂った
場合。
Next, the mounting position of the camera 1 will be described. Cases where an abnormality in the shape of the probe needle 12 becomes a problem include (1) when the positional relationship between the test pad of the semiconductor device and the probe needle 12 is out of order;

(2)プローブ針12が高さ方向に変形してしまった場
合。
(2) When the probe needle 12 is deformed in the height direction.

の2通りがあり、いずれの場合も半導体装置に傷をつけ
てしまったり、電気的接触がとれず測定、試験が正確に
できない事態が生じてしまう、そこで本実施例では、カ
メラ1を第1図及び第2図に示す通りプローブ針12の
垂直下方向と、水平方向に取りつけ、位置と高さをチェ
ックできるようにしである。尚この場合半導体装置の測
定、試験中はステージ6がプローブカード3の下に移動
している為カメラ1−aを遮ぎる形となり、プローブ針
12の形状及び位置の取り込みが不可能になるが、この
点に関しては針チェックのタイミング時には本体制御回
路11がステージ6を第1図及び第2図の位置(カメラ
lの視野を遮ぎらない位置)に移動させることを行なう
ことにより、問題とはならない、また、実際の運用面に
おいて針チェックのタイミングを下記に示す通りとすれ
ば、上記のステージ移動による時間のロスは最小限にと
どめることができる。
There are two ways to do this, and in either case, the semiconductor device may be damaged or electrical contact may not be established, making it impossible to perform accurate measurements or tests.Therefore, in this embodiment, camera 1 is As shown in the figure and FIG. 2, the probe needle 12 is attached vertically downward and horizontally so that the position and height can be checked. In this case, during the measurement and testing of the semiconductor device, the stage 6 is moved below the probe card 3, so it blocks the camera 1-a, making it impossible to capture the shape and position of the probe needle 12. Regarding this point, the problem can be solved by moving the stage 6 to the position shown in FIGS. 1 and 2 (a position that does not block the field of view of the camera l) by the main body control circuit 11 at the timing of the needle check. In addition, in actual operation, if the timing of the needle check is as shown below, the time loss due to the above stage movement can be kept to a minimum.

(1)ウェハー交換時にステージ6がローダ−/アンロ
ーダー7側に移動した時に行なう。
(1) This is performed when the stage 6 moves to the loader/unloader 7 side during wafer exchange.

(2)半導体装置の測定、試験時に一定数個毎に行なう
(2) Perform every certain number of semiconductor devices during measurement and testing.

(3)(2)の代りに一定数個の不良が続いて起きた場
合のみ行なう。
(3) Instead of (2), perform this only if a certain number of defects occur in succession.

〔発明の効果1 以上述べたように本発明によれば、針チェック機構lO
を設けたことにより、半導体装置にプローブ針12を接
触させることなく、事前にプローブ針12の形状及び位
置の良否を判定できるため、 (1)ウェハーに傷をつける危険減少 (2)半導体装置の測定、試験の信頼性向上に多大な効
果を6たらす。
[Effect of the invention 1 As described above, according to the present invention, the needle check mechanism lO
By providing this, the shape and position of the probe needle 12 can be determined in advance without contacting the semiconductor device with the probe needle 12, thereby (1) reducing the risk of damaging the wafer; and (2) reducing the risk of damaging the semiconductor device. It has a great effect on improving the reliability of measurements and tests.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明のウェハープローバーの横断面図。 第2図は、本発明のウェハープローバーの縦断面図。 第3図は、本発明のウェハープローバーの制御系ブロッ
ク図。 ・カメラ ・ p3明 ・テストシステムとのインターフェース・プローブカー
ド ・ステージ駆動軸 ・ステージ ・ローグー/アンローダ− ・画像処理回路 ・制御回路 ・針チェック機構 ・本体制御回路
FIG. 1 is a cross-sectional view of the wafer prober of the present invention. FIG. 2 is a longitudinal sectional view of the wafer prober of the present invention. FIG. 3 is a block diagram of the control system of the wafer prober of the present invention.・Camera・P3 light・Interface with test system・Probe card・Stage drive shaft・Stage・Rogue/unloader・Image processing circuit・Control circuit・Needle check mechanism・Main body control circuit

Claims (4)

【特許請求の範囲】[Claims] (1)ウェハー上に形成された半導体装置の試験用パッ
ドとプローブ針を接触させて、前記半導体装置の電気的
特性及び機能を測定、評価するウェハープローバーにお
いて、前記プローブ針の形状及び位置を認識し、正常な
形状及び位置との比較判断する機構(以下「針チェック
機構」と記す)を設けたことを特徴とするウェハープロ
ーバー。
(1) In a wafer prober that measures and evaluates the electrical characteristics and functions of a semiconductor device by bringing the probe needle into contact with a test pad of a semiconductor device formed on a wafer, the shape and position of the probe needle are recognized. A wafer prober characterized in that it is provided with a mechanism (hereinafter referred to as a "needle checking mechanism") for comparing and determining the shape and position of the wafer with a normal shape and position.
(2)前記針チェック機構に、画像取込用カメラ、照明
、画像処理回路を備えた請求項1記載のウェハープロー
バー。
(2) The wafer prober according to claim 1, wherein the needle check mechanism includes an image capturing camera, illumination, and an image processing circuit.
(3)前記画像取込用カメラを複数台異なる位置に設け
た請求項2記載のウェハープローバー。
(3) The wafer prober according to claim 2, wherein a plurality of said image capturing cameras are provided at different positions.
(4)前記画像取込用カメラを前記プローブ針の取り付
け位置に対して垂直下方向と水平方向の2ケ所に設けた
ことを特徴とする請求項3記載のウェハープローバー。
(4) The wafer prober according to claim 3, wherein the image capturing camera is provided at two locations, one vertically downward and the other horizontally relative to the attachment position of the probe needle.
JP17231589A 1989-07-04 1989-07-04 Wafer probe Pending JPH0336746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17231589A JPH0336746A (en) 1989-07-04 1989-07-04 Wafer probe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17231589A JPH0336746A (en) 1989-07-04 1989-07-04 Wafer probe

Publications (1)

Publication Number Publication Date
JPH0336746A true JPH0336746A (en) 1991-02-18

Family

ID=15939638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17231589A Pending JPH0336746A (en) 1989-07-04 1989-07-04 Wafer probe

Country Status (1)

Country Link
JP (1) JPH0336746A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0592878A2 (en) * 1992-10-15 1994-04-20 Eckhard Dr. Ehlermann Method and device for inspecting probe cards for testing integrated circuits
WO2009090296A1 (en) * 2008-01-11 2009-07-23 Veli-Pekka Johansson A method and an apparatus for removing a glue protection at a joint in a paper reel

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0592878A2 (en) * 1992-10-15 1994-04-20 Eckhard Dr. Ehlermann Method and device for inspecting probe cards for testing integrated circuits
EP0592878A3 (en) * 1992-10-15 1995-02-01 Ehlermann Eckhard Method and device for inspecting probe cards for testing integrated circuits.
WO2009090296A1 (en) * 2008-01-11 2009-07-23 Veli-Pekka Johansson A method and an apparatus for removing a glue protection at a joint in a paper reel

Similar Documents

Publication Publication Date Title
KR950015701A (en) Probing method and probe device
JPH0376137A (en) Wire bonding testing device
KR20070115737A (en) Method for detecting tips of probes, alignment method and storage medium storing the methods, and probe apparatus
US11133214B2 (en) Substrate transportation method
CN111386595A (en) Method for adjusting position of probe tip and inspection device
KR20080112964A (en) Method for registering probe card and a storage medium storing program thereof
JP3028095B2 (en) Probing apparatus and method
KR102150940B1 (en) Apparatus for Testing Array for Precise Control of Probe Blocks
JPH0336746A (en) Wafer probe
KR20220044741A (en) Wafer appearance inspection apparatus and method
CN111474598A (en) Electronic component mounting state detection device
JPH11347985A (en) Trouble diagnostic method for robot system with visual sensor
TWI772465B (en) Inspection device, inspection method, and storage medium
JP2007095753A (en) Prober, prober contact method, and program therefor
KR20020051846A (en) Carrier positional displacement detecting mechanism
JP3202577B2 (en) Probe method
JPH033941B2 (en)
JP4783271B2 (en) Wafer electrode registration method, wafer alignment method, and recording medium recording these methods
JP2577525Y2 (en) Short / open inspection equipment
KR102199108B1 (en) Wafer examination apparatus
TWI845721B (en) Wafer appearance inspection device and method
WO2022176664A1 (en) Inspection device set-up method and inspection device
JPS62136041A (en) Wafer prober
CN118131016A (en) Integrated circuit test probe card device and method
JP2560645B2 (en) Semiconductor device lead bending inspection method