JPH0336122U - - Google Patents
Info
- Publication number
- JPH0336122U JPH0336122U JP9597489U JP9597489U JPH0336122U JP H0336122 U JPH0336122 U JP H0336122U JP 9597489 U JP9597489 U JP 9597489U JP 9597489 U JP9597489 U JP 9597489U JP H0336122 U JPH0336122 U JP H0336122U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- view
- ceramic capacitor
- type composite
- showing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003985 ceramic capacitor Substances 0.000 claims description 6
- 239000002131 composite material Substances 0.000 claims description 3
- 239000000919 ceramic Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Description
第１図は本考案によるチツプ型積層セラミツク
コンデンサの外観斜視図、第２図はその内部構造
を示す一部省略分解斜視図、第３図は本考案によ
るチツプ型複合積層セラミツクコンデンサをプリ
ント基板上に実装した状態を示す平面図、第４図
は第２実施例を示す外観斜視図、第５図は第４図
の−線に沿う断面図、第６図は第３実施例を
示す外観斜視図である。第７図は従来のチツプ型
積層セラミツクコンデンサの外観斜視図、第８図
はその縦断面図、第９図はその内部構造を示す一
部省略分解斜視図、第１０図は従来のプリント基
板上に形成した半田付けランドの平面図、第１１
図はこの上にチツプ型積層セラミツクコンデンサ
を実装した状態を示す平面図である。
２０ａ，２０ｂ……外部電極、３０……セラミ
ツクシート、４０……内部電極、７０……チツプ
型複合積層セラミツクコンデンサ（チツプ）、７
Ａ……チツプ素子。
Fig. 1 is an external perspective view of a chip-type multilayer ceramic capacitor according to the present invention, Fig. 2 is a partially omitted exploded perspective view showing its internal structure, and Fig. 3 is a chip-type composite multilayer ceramic capacitor according to the present invention mounted on a printed circuit board. 4 is an external perspective view showing the second embodiment, FIG. 5 is a sectional view taken along the - line in FIG. 4, and FIG. 6 is an external perspective view showing the third embodiment. It is a diagram. Fig. 7 is an external perspective view of a conventional chip-type multilayer ceramic capacitor, Fig. 8 is a vertical sectional view thereof, Fig. 9 is a partially omitted exploded perspective view showing its internal structure, and Fig. 10 is a conventional printed circuit board. 11th plan view of the soldering land formed in
The figure is a plan view showing a chip type multilayer ceramic capacitor mounted thereon. 20a, 20b...external electrode, 30...ceramic sheet, 40...internal electrode, 70...chip type composite laminated ceramic capacitor (chip), 7
A... Chip element.
Claims (1)
とを積層し、独立した複数組の外部電極を形成し
てなる同一容量のチツプ素子が一体化されたチツ
プ型複合セラミツクコンデンサ。 A chip-type composite ceramic capacitor that integrates chip elements with the same capacity, which are made by laminating a common ceramic sheet and divided internal electrodes to form multiple sets of independent external electrodes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9597489U JPH0336122U (en) | 1989-08-16 | 1989-08-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9597489U JPH0336122U (en) | 1989-08-16 | 1989-08-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0336122U true JPH0336122U (en) | 1991-04-09 |
Family
ID=31645203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9597489U Pending JPH0336122U (en) | 1989-08-16 | 1989-08-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0336122U (en) |
-
1989
- 1989-08-16 JP JP9597489U patent/JPH0336122U/ja active Pending
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