JPH01156502U

JPH01156502U -

Info

Publication number: JPH01156502U
Application number: JP5327888U
Authority: JP
Priority date: 1988-04-19
Filing date: 1988-04-19
Publication date: 1989-10-27

Description

[Brief explanation of the drawing]

第１図〜第６図は本考案の一実施例に係り、第
１図は積層チツプバリスタを示す斜視図、第２図
は第１図Ａ―Ａ断面図、第３図は焼成前の長方体
状積層バリスタ素体を示す展開斜視図、第４図は
焼成前の長方体状積層バリスタ素体を示す斜視図
、第５図は第１図及び第２図を構成する板状端子
を示す斜視図、第６図は積層チツプバリスタを回
路基板に装着した状態を示す正面図、第７図は本
考案の他の実施例に係る積層チツプバリスタを示
す一部切欠正面図、第８図〜第１０図は従来の参
考例に係り、第８図は積層チツプバリスタを示す
斜視図、第９図は第８図Ｂ―Ｂ断面図、第１０図
は積層チツプバリスタを回路基板に装着した状態
を示す正面図、第１１図及び第１２図は従来の他
の参考例に係り、第１１図は積層チツプバリスタ
を示す正面図、第１２図は第１１図イ部拡大図で
ある。２……内部電極、５……長方体状積層バリスタ
素体、６……内部電極導出部、８……回路接続部
、９……板状端子。 1 to 6 relate to one embodiment of the present invention, in which FIG. 1 is a perspective view showing a laminated chip varistor, FIG. 2 is a sectional view taken along line A-A in FIG. FIG. 4 is a perspective view showing a rectangular multilayer varistor element before firing; FIG. 5 is a plate-shaped terminal configuring FIGS. 1 and 2. FIG. 6 is a front view showing a laminated chip varistor mounted on a circuit board, FIG. 7 is a partially cutaway front view showing a laminated chip varistor according to another embodiment of the present invention, and FIG. Figures to Figures 10 relate to conventional reference examples, Figure 8 is a perspective view showing a laminated chip varistor, Figure 9 is a sectional view taken along line B-B in Figure 8, and Figure 10 is a laminated chip varistor mounted on a circuit board. FIG. 11 and FIG. 12 are a front view showing a state in which the varistor is in the same state as shown in FIG. 2... Internal electrode, 5... Rectangular laminated varistor element body, 6... Internal electrode lead-out portion, 8... Circuit connection portion, 9... Plate terminal.

Claims

[Scope of utility model registration request]

A rectangular laminated varistor element whose internal electrodes are exposed and whose end faces are square; an internal electrode lead-out portion formed on both end faces of the laminated varistor element; A multilayer chip varistor characterized in that it is equipped with plate-shaped terminals in which circuit connection parts are located on each of the four sides of the element body.