JPH0335827B2 - - Google Patents
Info
- Publication number
- JPH0335827B2 JPH0335827B2 JP56065719A JP6571981A JPH0335827B2 JP H0335827 B2 JPH0335827 B2 JP H0335827B2 JP 56065719 A JP56065719 A JP 56065719A JP 6571981 A JP6571981 A JP 6571981A JP H0335827 B2 JPH0335827 B2 JP H0335827B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive material
- material layer
- film
- resist film
- shoulder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000004528 spin coating Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に半
導体装置のコンタクト電極の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a contact electrode of a semiconductor device.
半導体装置の電極配線は、通常半導体基板表面
を被覆する絶縁膜に開口されたコンタクト窓内の
基板表面より前記絶縁膜上に導出して形成され
る。しかしかかる構造では周知の如く基板表面に
凹凸を生じ、その段階肩部において配線層の膜切
れを生じ易い。半導体装置が大規模化するに伴な
い多層配線か多く用いられるようになると、上述
の基板表面の凹凸は益々深刻な問題となつてい
る。 Electrode wiring of a semiconductor device is usually formed by leading out onto the insulating film from the substrate surface within a contact window opened in the insulating film covering the surface of the semiconductor substrate. However, in such a structure, as is well known, unevenness occurs on the surface of the substrate, and film breakage of the wiring layer is likely to occur at the shoulder portion of the substrate. As semiconductor devices become larger in scale and multilayer interconnections are increasingly used, the above-mentioned unevenness on the substrate surface becomes an increasingly serious problem.
そこで半導体装置の信頼度を高め製造歩留りを
向上させるため、基板表面を極力平坦化する半導
体装置の製造方法が既に種々提唱されている。し
かしこれらはいずれも工程が煩雑である等の問題
があり、十分満足し得るものとは言い難い。 Therefore, in order to increase the reliability of semiconductor devices and improve manufacturing yields, various semiconductor device manufacturing methods have already been proposed in which the substrate surface is made as flat as possible. However, all of these methods have problems such as complicated processes, and cannot be said to be fully satisfactory.
本発明は上記問題点を解消し、絶縁膜とコンタ
クト電極の表面を略同一平面に形成し得る半導体
装置の製造方法を提供することを目的とし、この
目的は本発明において、絶縁膜に開口されたコン
タクト窓部を含む半導体基板上全面に所定の導電
材料層を形成し、該導電材料層表面の前記コンタ
クト窓部に形成された凹部８内に厚く、凸部上に
は薄く、特に凸部と凹部間の肩１０部分では極め
て薄いフオトレジスト膜を形成し、前記凹部８お
よび凸部と凹部間の肩１０部分のレジスト膜を露
光した後、現像処理によつて前記凸部および凸部
と凹部の肩１０部分のレジスト膜を所定時間で一
様に除去するようにする。その後前記現像処理工
程で残留したレジスト膜をマスクとして前記導電
材料層を選択的に除去し前記開口部内の導電材料
層を前記絶縁膜と略同等の厚さに形成することに
より達成される。 An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device in which the surfaces of an insulating film and a contact electrode can be formed on substantially the same plane. A predetermined conductive material layer is formed on the entire surface of the semiconductor substrate including the contact window, and is thick in the recess 8 formed in the contact window on the surface of the conductive material layer, and thin in the convex part, especially in the convex part. An extremely thin photoresist film is formed on the shoulder 10 portion between the concave portion and the concave portion, and after exposing the resist film on the shoulder 10 portion between the concave portion 8 and the convex portion, the convex portion and the convex portion are separated by a development process. The resist film on the shoulder 10 portion of the recess is uniformly removed over a predetermined period of time. Thereafter, the conductive material layer is selectively removed using the resist film remaining in the development process as a mask, and the conductive material layer in the opening is formed to have substantially the same thickness as the insulating film.
以下第１図ないし第６図により本発明の一実施
例を製造工程の順に説明する。 An embodiment of the present invention will be explained below in the order of manufacturing steps with reference to FIGS. 1 to 6.
第１図においては１はシリコン基板、２は例え
ばnpnトランジスタのｐ型ベース領域、３はその
ｎ型エミツタ領域、４，５はそれぞれシリコン基
板１表面を被覆する二酸化シリコン（SiO2）膜
及び燐シリケートガラス（PSG）膜を示す。こ
のSiO2膜４及びPSG膜５に通常のフオトエツチ
ング法により電極コンタクト窓６を開口する。 In FIG. 1, 1 is a silicon substrate, 2 is, for example, a p-type base region of an npn transistor, 3 is an n-type emitter region thereof, and 4 and 5 are a silicon dioxide (SiO 2 ) film and phosphorus that cover the surface of the silicon substrate 1, respectively. A silicate glass (PSG) membrane is shown. Electrode contact windows 6 are opened in the SiO 2 film 4 and PSG film 5 by the usual photoetching method.
次いで第２図に示すように化学気相成長
（CVD）法によりシリコン基板１上全面に燐
（Ｐ）または砒素（As）のようなｎ型不純物をド
ープしたシリコン多結晶層７をSiO2膜４とPSG
膜５の合計厚さとほぼ同じ厚さに形成する。この
ようにして形成したシリコン多結晶７の表面には
前記コンタクト窓６部において凹部８が形成され
る。なお上記ｎ型不純物はCVD法でシリコン多
結晶層７を成長せしめる際に同時にドープしても
よく、或いはシリコン多結晶層７を形成した後拡
散法等によりドープしてもよい。 Next, as shown in FIG. 2, a silicon polycrystalline layer 7 doped with an n-type impurity such as phosphorus (P) or arsenic (As) is deposited on the entire surface of the silicon substrate 1 by chemical vapor deposition (CVD) as a SiO 2 film. 4 and PSG
The thickness is approximately the same as the total thickness of the film 5. A recess 8 is formed in the surface of the silicon polycrystal 7 thus formed at the contact window 6 portion. Note that the n-type impurity may be doped at the same time when the silicon polycrystalline layer 7 is grown by the CVD method, or may be doped by a diffusion method or the like after the silicon polycrystalline layer 7 is formed.
次いで第３図に示すように、回転塗布法により
ネガ型のフオトレジスト液を上記シリコン多結晶
７上に塗布し、上記凹部８内には厚く、凸部上に
は薄く、特に凸部の肩１０の所ではきわめて薄く
なるレジスト膜９を形成する。 Next, as shown in FIG. 3, a negative type photoresist solution is applied onto the silicon polycrystalline 7 by a spin coating method, thickly in the recesses 8 and thinly on the convexes, especially on the shoulders of the convexes. At 10, a resist film 9 is formed which becomes extremely thin.
次いで上記凹部８と凸部の肩１０部分を透光部
とするフオトマスク１１を用いてフオトレジスト
膜９を露光する。なお矢線１２は露光光を示す。 Next, the photoresist film 9 is exposed using a photomask 11 whose light-transmitting portions are the concave portions 8 and the shoulder portions 10 of the convex portions. Note that an arrow line 12 indicates exposure light.
次いで上記露光を終了したフオトレジスト膜９
に現像処理を施すこと、第４図に示すように、露
光されない凸部の薄いフオトレジスト膜と露光さ
れた凹部の肩１０の極めて薄いフオトレジスト膜
とが所定の時間で一様に除去され、凹部８内にの
みフオトレジスト膜が残留する。このようにフオ
トレジスト膜９のきわめて薄い部分はたとえ露光
されても現像処理によつて除去されるので、前記
フオトマスク１１の透光部パターンは凹部８より
稍大きいものとしてよく、従つて位置合わせに際
しても厳密な精度は必要としない。なおフオトレ
ジスト膜９が上記凹部８以外の場所に残留するよ
うなときは、酸素（O2）プラズマを照射してこ
れを除去してもよい。 Next, the photoresist film 9 after the above-mentioned exposure
As shown in FIG. 4, the thin photoresist film on the unexposed convex portions and the extremely thin photoresist film on the shoulders 10 of the exposed concave portions are uniformly removed in a predetermined period of time, as shown in FIG. The photoresist film remains only within the recess 8. In this way, even if the extremely thin portion of the photoresist film 9 is exposed, it will be removed by the development process, so the light-transmitting pattern of the photomask 11 may be slightly larger than the recessed portion 8, and therefore, it will be difficult to Also, exact accuracy is not required. Note that if the photoresist film 9 remains in a location other than the recess 8, it may be removed by irradiating oxygen (O 2 ) plasma.
次いで第５図に示すごとく上記凹部８内に残留
せしめたフオトレジスト膜９をマスクとして、例
えば四弗化炭素（CF4）と酸素（O2）の混合気体
を反応ガスとするプラズマエツチングを行なつて
前記露光せるシリコ多結晶層７を選択的に除去す
る。このとき前記PSG膜５上のシリコン多結晶
層７が完全に除去される程度にエツチング量を制
御することにより、前記コンタクト窓６内に残留
せるシリコン多結晶層７の表面は図示のごとく
PSG膜５の表面とほぼ同一平面に形成される。 Next, as shown in FIG. 5, using the photoresist film 9 left in the recess 8 as a mask, plasma etching is performed using, for example, a mixed gas of carbon tetrafluoride (CF 4 ) and oxygen (O 2 ) as a reactive gas. Then, the exposed silicon polycrystalline layer 7 is selectively removed. At this time, by controlling the amount of etching to such an extent that the silicon polycrystalline layer 7 on the PSG film 5 is completely removed, the surface of the silicon polycrystalline layer 7 remaining in the contact window 6 is reduced as shown in the figure.
It is formed almost on the same plane as the surface of the PSG film 5.
従つてこのあと通常の製造工程に従つてアルミ
ニウム（Al）等よりなる配線体１３を形成すれ
ば、下地層表面が略平坦面とされているので配線
体１３には凹凸を生じることなく、従つて断線等
が発生する危険が除去された。 Therefore, if the wiring body 13 made of aluminum (Al) or the like is then formed according to the normal manufacturing process, since the surface of the base layer is a substantially flat surface, the wiring body 13 will not have any unevenness. This eliminates the risk of wire breakage, etc.
本発明において上記コンタクト窓内を充填して
形成したシリコン多結晶層７はコンタクト電極と
して用いているが、このコンタクト電極をｐ型領
域上に形成するときは、前記一実施例とは異な
り、ボロン(B)のようなｐ型不純物を含有せしめ
る。 In the present invention, the silicon polycrystalline layer 7 formed by filling the contact window is used as a contact electrode, but when this contact electrode is formed on the p-type region, unlike in the above embodiment, boron Contains p-type impurities such as (B).
また本発明はバイポーラ素子及びMISFETを
いずれを製作する場合にも適用し得ることは特に
説明を要しないであろう。 Further, it does not require any particular explanation that the present invention can be applied to the production of both bipolar elements and MISFETs.
以上説明したごとく、本発明によればコンタク
ト電極を周囲の絶縁膜とをほぼ同じ高さに形成す
るので上層の配線体が断線することはない。しか
も本発明において新たに使用するフオト工程は厳
しい精度を必要としないので、作業はいたつて容
易である。更に本発明は多層配線の形成にも用い
ることができる。 As explained above, according to the present invention, since the contact electrode is formed at approximately the same height as the surrounding insulating film, the upper layer wiring body will not be disconnected. Moreover, the photo process newly used in the present invention does not require strict precision, so the work is easy. Furthermore, the present invention can also be used to form multilayer wiring.
第１図ないし第６図は本発明の一実施例を示す
要部断面図である。
図において、１は半導体基板、４，５は絶縁
膜、６はコンタクト窓、７はシリコン多結晶層、
８は凹部、９はフオトレジスト膜を示す。
1 to 6 are sectional views of essential parts showing one embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 4 and 5 are insulating films, 6 is a contact window, 7 is a silicon polycrystalline layer,
Reference numeral 8 indicates a recess, and reference numeral 9 indicates a photoresist film.
Claims (1)
を選択的に除去して開口を設け、該開口部を含む
前記半導体基板上に所定の導電材料層を前記絶縁
膜の厚さと略同等の厚さに形成する工程と、 前記開口部に沿つて形成された凹凸状の前記導
電材料層の開口部上の凹部内に厚く、凸部上には
薄く、かつ凸部と凹部間の肩部分では選択的に特
に薄いフオトレジスト膜を回転塗布法によつて形
成するレジスト膜形成工程と、 前記凹部を包含し、前記フオトレジスト膜が特
に薄く形成された凸部と凹部間の肩部分領域を概
ね越えない範囲のレジスト膜を露光する露光工程
と、 前記凸部および前記凸部と凹部間の肩部分のレ
ジスト膜を所定時間で一様に除去する現像処理工
程と、 前記現像処理工程で残留したレジスト膜をマス
クとして前記導電材料層を選択的に除去し前記開
口内部の導電材料層を前記絶縁膜と略同等の厚さ
に形成する工程とを含むことを特徴とする半導体
装置の製造方法。[Claims] 1. A predetermined portion of an insulating film covering the surface of a semiconductor substrate is selectively removed to form an opening, and a predetermined conductive material layer is deposited on the semiconductor substrate including the opening to a thickness of the insulating film. forming the conductive material layer to have a thickness substantially equal to that of the conductive material layer; a resist film forming step in which a particularly thin photoresist film is selectively formed by a spin coating method on the shoulder portions between the convex portions and the concave portions, which include the concave portions and where the photoresist film is particularly thinly formed; an exposure step of exposing a resist film within a range that does not generally exceed the shoulder area; a development process of uniformly removing the resist film in the convex portion and the shoulder portion between the convex portion and the concave portion over a predetermined period of time; and the developing step. A semiconductor characterized by comprising the step of selectively removing the conductive material layer using a resist film remaining in the processing step as a mask, and forming the conductive material layer inside the opening to have a thickness substantially equal to that of the insulating film. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6571981A JPS57180123A (en) | 1981-04-29 | 1981-04-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6571981A JPS57180123A (en) | 1981-04-29 | 1981-04-29 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57180123A JPS57180123A (en) | 1982-11-06 |
| JPH0335827B2 true JPH0335827B2 (en) | 1991-05-29 |
Family
ID=13295104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6571981A Granted JPS57180123A (en) | 1981-04-29 | 1981-04-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57180123A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5121724A (en) * | 1989-11-16 | 1992-06-16 | Nissan Motor Company, Ltd. | Multi-cylinder internal combustion engine with individual port throttles upstream of intake valves |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50107877A (en) * | 1974-01-30 | 1975-08-25 | ||
| JPS511586A (en) * | 1974-06-26 | 1976-01-08 | Toyo Kogyo Co | KARIUGOMUTOKINZOKUTONO SETSUCHAKUHOHO |
-
1981
- 1981-04-29 JP JP6571981A patent/JPS57180123A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50107877A (en) * | 1974-01-30 | 1975-08-25 | ||
| JPS511586A (en) * | 1974-06-26 | 1976-01-08 | Toyo Kogyo Co | KARIUGOMUTOKINZOKUTONO SETSUCHAKUHOHO |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57180123A (en) | 1982-11-06 |
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