JPH0334805Y2 - - Google Patents

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Publication number
JPH0334805Y2
JPH0334805Y2 JP15181182U JP15181182U JPH0334805Y2 JP H0334805 Y2 JPH0334805 Y2 JP H0334805Y2 JP 15181182 U JP15181182 U JP 15181182U JP 15181182 U JP15181182 U JP 15181182U JP H0334805 Y2 JPH0334805 Y2 JP H0334805Y2
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JP
Japan
Prior art keywords
circuit
switch
current source
memory
source circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15181182U
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Japanese (ja)
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JPS5955826U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15181182U priority Critical patent/JPS5955826U/en
Priority to US06/537,825 priority patent/US4633444A/en
Priority to DE19833336447 priority patent/DE3336447A1/en
Publication of JPS5955826U publication Critical patent/JPS5955826U/en
Application granted granted Critical
Publication of JPH0334805Y2 publication Critical patent/JPH0334805Y2/ja
Granted legal-status Critical Current

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  • Electronic Switches (AREA)

Description

【考案の詳細な説明】 本考案は手動スイツチからの信号をスイツチ駆
動回路を介し電子スイツチ(アナログ・スイツチ
等)に伝達して開閉動作をさせるスイツチ回路に
関し、殊に主電源投入時スイツチの初期状態を設
定する機能を具えたスイツチ回路に係る。
[Detailed description of the invention] The present invention relates to a switch circuit that transmits a signal from a manual switch to an electronic switch (analog switch, etc.) via a switch drive circuit to open/close the switch. It relates to a switch circuit that has a function to set the state.

本考案のスイツチ回路はその主要部がI2L
(Integrrated Injection Logic)回路で形成され、
そして主電源遮断時にインジエクタ電流を注入す
る補助電流源回路を具なえている。また、その補
助電流源回路はスイツチの設定条件を記憶する記
憶回路のみに主電源遮断時インジエクタ電流を注
入するようになされる。
The main part of the switch circuit of this invention is I2L .
(Integrated Injection Logic) circuit,
It also includes an auxiliary current source circuit that injects an injector current when the main power is cut off. Further, the auxiliary current source circuit is configured to inject the injector current only into the memory circuit that stores the setting conditions of the switch when the main power supply is cut off.

上述のように一部の記憶回路のみに補助電流源
回路からインジエクタ電流を注入する方法であつ
ても長時間主電源が遮断された場合は、補助電流
源回路の容量が不足して記憶回路の記憶が消去さ
れる可能性があり、主電源復帰時に不安定な設定
条件となる欠点がある。
Even if the injector current is injected from the auxiliary current source circuit to only some of the memory circuits as described above, if the main power is cut off for a long time, the capacity of the auxiliary current source circuit will be insufficient and the memory circuit will be damaged. This has the disadvantage that the memory may be erased and the setting conditions become unstable when the main power is restored.

本考案は上述の如き欠点を解消するもので、そ
の主な目的は主電源投入時に補助電流源回路の能
力が不充分なときはスイツチ回路の予め定められ
たスイツチをオンとして初期状態を設定する機能
を具えたスイツチ回路を提供するにある。
The present invention is intended to solve the above-mentioned drawbacks, and its main purpose is to turn on a predetermined switch in the switch circuit to set the initial state when the ability of the auxiliary current source circuit is insufficient when the main power is turned on. The purpose is to provide a switch circuit with functions.

また、補助電流源回路に含まれる充電回路の充
電電位が高い電位のときは記憶回路の設定条件に
よつてスイツチのオン・オフを定めるスイツチ回
路を提供するにある。
Another object of the present invention is to provide a switch circuit which determines whether the switch is turned on or off depending on the setting conditions of the memory circuit when the charging potential of the charging circuit included in the auxiliary current source circuit is high.

斯るスイツチ回路は補助電流源回路を具え、そ
の主要部がI2L回路で形成されている。そして主
電源投入時に予め設定されたスイツチが動作する
ようになされ、また主電源復帰時、記憶回路によ
つてスイツチの設定条件を記憶している場合はそ
の記憶に基づいてスイツチが設定される。
Such a switch circuit includes an auxiliary current source circuit, the main part of which is formed by an I 2 L circuit. Then, when the main power is turned on, a preset switch is activated, and when the main power is restored, if the setting conditions for the switch are stored in the memory circuit, the switch is set based on the memory.

以下、本考案に係るスイツチ回路に就いて第1
図乃至第4図に基づき説明する。
Below, the first part of the switch circuit according to the present invention will be explained.
This will be explained based on FIGS. 4 to 4.

第1図はスイツチ回路のブロツク図である。信
号入力段は自己復帰型の接点を有するスイツチ1
と表示灯2から形成されている。検出回路3、記
憶回路4及び駆動回路9はスイツチ駆動回路部で
ある。検出回路3はスイツチ1からの信号をパル
スに変換して記憶回路4に伝達され記憶される。
更に信号は伝達され、アナログスイツチ5を開閉
すると共に駆動回路9に信号を伝達し表示灯2の
内の一つを点灯保持する。また、検出回路3の一
部と記憶回路4がI2L素子で形成されており、そ
れらのI2L素子に電流源回路6から抵抗11、ダ
イオード12並びに抵抗13を介しインジエクタ
電流が注入されている。主電流源投入時は補助電
流源回路7に充電々流が抵抗15を介しコンデン
サ16に流れ込んでいる。
FIG. 1 is a block diagram of a switch circuit. The signal input stage is a switch 1 with a self-returning contact.
and an indicator light 2. The detection circuit 3, memory circuit 4, and drive circuit 9 are a switch drive circuit section. The detection circuit 3 converts the signal from the switch 1 into a pulse, which is transmitted to the storage circuit 4 and stored therein.
Furthermore, the signal is transmitted to open and close the analog switch 5, and also transmits the signal to the drive circuit 9 to keep one of the indicator lights 2 lit. Further, a part of the detection circuit 3 and the memory circuit 4 are formed of I 2 L elements, and an injector current is injected into these I 2 L elements from the current source circuit 6 via the resistor 11, the diode 12, and the resistor 13. ing. When the main current source is turned on, a charging current flows into the auxiliary current source circuit 7 through the resistor 15 and into the capacitor 16.

さて、主電源遮断時は補助電流源回路7から記
憶回路4を形成するI2L回路にインジエクタ電流
が注入され記憶を保持している。一方、補助電流
源回路7の充電回路の電位がレベルシフト回路8
によつて監視され、補助電流源回路7の端子間電
圧が所定のレベル以下となつたとき、レベルシフ
ト回路8、ダイオード14を介して補助電流源回
路7に充電電流が供給され、スイツチ1の一つを
疑似的にオン状態とし、他のスイツチはリセツト
状態となる。また、ダイオード14は補助電流源
回路7からの電流の流れ込みを防止する。
Now, when the main power supply is cut off, an injector current is injected from the auxiliary current source circuit 7 into the I 2 L circuit forming the memory circuit 4 to maintain the memory. On the other hand, the potential of the charging circuit of the auxiliary current source circuit 7 is
When the voltage between the terminals of the auxiliary current source circuit 7 falls below a predetermined level, a charging current is supplied to the auxiliary current source circuit 7 via the level shift circuit 8 and the diode 14, and the voltage of the switch 1 is One switch is put into a pseudo on state, and the other switches are put into a reset state. Further, the diode 14 prevents current from flowing from the auxiliary current source circuit 7.

本考案のスイツチ回路はスイツチ1の初期状態
を補助電流源回路7の端子間電圧の電位によつて
制御している。主電源投入時は補助電流源回路7
の充電回路を形成するコンデンサ16が放電され
た状態であり、コンデンサ16の端子間電圧は零
電位である。しかし、コンデンサ16の端子間電
圧は、所定の表示灯2、レベルシフト回路8、ダ
イオード14及び抵抗15を介して充電々流が流
れ込み電位は上昇する。従つて、主電源投入時は
スイツチ1の一つの接続点17の電位は低レベル
になり、他はスイツチが開放状態であるので高レ
ベルに設定される。このようにして、補助電流源
回路7のコンデンサ16に充電電流を供給して所
定のスイツチの接点間を短絡することにより擬似
的に信号が発せられて初期状態が設定される。信
号入力段のスイツチ1が任意に設定され、この設
定条件が記憶回路4に記憶され、主電源が遮断さ
れた場合、補助電流源7から該記憶回路4にイン
ジエクタ電流が注入され、その記憶を保持する。
そして、主電源が復帰された場合、記憶回路4の
記憶に基づきスイツチが設定される。また、主電
源が長時間遮断状態にあつて、補助電流源回路7
の容量が消費され、記憶回路4の保持が困難とな
るとスイツチの設定条件は消失される。この場
合、主電源復帰時は予め設定されたスイツチの接
点間電位を低レベルとしてスイツチ1の初期状態
が設定される。
In the switch circuit of the present invention, the initial state of the switch 1 is controlled by the potential of the voltage between the terminals of the auxiliary current source circuit 7. When the main power is turned on, the auxiliary current source circuit 7
The capacitor 16 forming the charging circuit is in a discharged state, and the voltage across the terminals of the capacitor 16 is zero potential. However, the potential of the voltage across the terminals of the capacitor 16 increases as a charging current flows through the predetermined indicator light 2, level shift circuit 8, diode 14, and resistor 15. Therefore, when the main power is turned on, the potential at one connection point 17 of the switch 1 is at a low level, and the other connections are set at a high level since the switch is in an open state. In this way, a charging current is supplied to the capacitor 16 of the auxiliary current source circuit 7 to short-circuit the contacts of a predetermined switch, thereby generating a pseudo signal and setting an initial state. When the switch 1 of the signal input stage is arbitrarily set and the setting conditions are stored in the memory circuit 4, and the main power supply is cut off, an injector current is injected from the auxiliary current source 7 into the memory circuit 4, and the memory is stored. Hold.
Then, when the main power is restored, the switch is set based on the memory in the memory circuit 4. In addition, if the main power supply is cut off for a long time, the auxiliary current source circuit 7
When the capacity of the memory circuit 4 is consumed and it becomes difficult to hold the memory circuit 4, the setting conditions of the switch are lost. In this case, when the main power is restored, the initial state of the switch 1 is set by setting the preset potential between the contacts of the switch to a low level.

第4図は本考案のスイツチ回路の一実施例であ
る。尚、I2L素子の記号を第2図に示し、その等
価回路を第3図に記した。Iはインジエクタ端子
である。第4図に於て、信号入力段は複数の自己
復帰型の接点を有するスイツチ11〜1oと発光ダ
イオード21〜2oが直列接続されている。検出回
路31はトランジスタT1〜T3とI2L素子A1等によ
り形成され、検出回路3nも同様な構成となつて
いる。記憶回路41はI2L素子A2,A3からなるフ
リツプ・フロツプ(以下F/Fと略す。)から形
成され、F/F4oも同様な構成となつている。
18は信号伝送回路であり、I2L素子A4の出力端
子の一つは電子スイツチ51へ、他の出力端子は
I2L素子A5を介し駆動回路91のトランジスタT7
のベースに接続されている。I2L素子A9も同様な
接続となつている。電子スイツチ51〜5oはアナ
ログ・スイツチ等であり、a,nは信号源であ
る。
FIG. 4 shows an embodiment of the switch circuit of the present invention. The symbol of the I 2 L element is shown in FIG. 2, and its equivalent circuit is shown in FIG. I is an injector terminal. In FIG. 4, the signal input stage includes switches 1 1 -1 o having a plurality of self-resetting contacts and light emitting diodes 2 1 -2 o connected in series. The detection circuit 31 is formed of transistors T1 to T3 , I2L element A1, etc., and the detection circuit 3n has a similar configuration. The memory circuit 4 1 is formed from a flip-flop (hereinafter abbreviated as F/F) consisting of I 2 L elements A 2 and A 3 , and the F/F 4 o has a similar structure.
18 is a signal transmission circuit, one of the output terminals of I2L element A4 goes to electronic switch 51 , and the other output terminals
Transistor T 7 of drive circuit 9 1 via I 2 L element A 5
connected to the base of. I 2 L element A 9 is also connected in a similar manner. Electronic switches 5 1 to 5 o are analog switches, etc., and a and n are signal sources.

スイツチ回路を形成するI2L素子は電流源回路
6からインジエクタ電流を供給している。その構
成は電圧源回路10及びインジエクタ抵抗11と
ダイオード12並びにインジエクタ抵抗13から
形成されている。インジエクタ抵抗11の他端は
記憶回路4を形成するI2L素子A2,A3……A7
A8にインジエクタ端子に接続されると共に補助
電流源回路7に接続される。且つ、ダイオード1
4とレベルシフト回路8を介してスイツチ11
発光ダイオード21との接続点に接続される。補
助電流源回路7は抵抗15とコンデンサ16から
形成されている。
The I 2 L element forming the switch circuit is supplied with an injector current from the current source circuit 6. Its configuration includes a voltage source circuit 10, an injector resistor 11, a diode 12, and an injector resistor 13. The other end of the injector resistor 11 is connected to I 2 L elements A 2 , A 3 ...A 7 , which form the memory circuit 4.
A 8 is connected to the injector terminal and also to the auxiliary current source circuit 7. And diode 1
4 and a level shift circuit 8 to the connection point between the switch 1 1 and the light emitting diode 2 1 . The auxiliary current source circuit 7 is formed from a resistor 15 and a capacitor 16.

さて、このスイツチ回路の主電源を投入する。
補助電流源回路7のコンデンサ16は放電された
状態となつているので補助電流源回路7の端子間
電圧の電位は低電位となつている。従つて、スイ
ツチ11と発光ダイオード21との接続点17は略
零電位となるのでスイツチ11は短絡状態に等し
く、スイツチオン信号が伝送され検出回路31
トランジスタT1〜T3がオフとなる。また、I2L素
子A1の入力端子の電位は高電位(Hレベル)と
なるので出力端子はLレベルとなると同時にF/
F4oをリセツトする。また、順次I2L素子A4
A5が作動し、トランジスタT7がオンとなつて駆
動回路91が作動し、発光ダイオード21は点灯状
態を保持する。また、駆動回路91の動作に基づ
き検出回路31のI2L素子A1の出力端子はLレベ
ルからHレベルに反転する。また、補助電流源回
路7のコンデンサ16は充電されるのでその端子
間電圧の電位及び接続点17の電位はHレベルと
なる。
Now, turn on the main power to this switch circuit.
Since the capacitor 16 of the auxiliary current source circuit 7 is in a discharged state, the potential of the voltage between the terminals of the auxiliary current source circuit 7 is at a low potential. Therefore, the connection point 17 between the switch 11 and the light emitting diode 21 has approximately zero potential, so the switch 11 is equivalent to a short-circuited state, and a switch-on signal is transmitted, turning off the transistors T1 to T3 of the detection circuit 31 . becomes. Also, since the potential of the input terminal of I 2 L element A1 becomes a high potential (H level), the output terminal becomes L level and at the same time the F/
Reset F4 o . Also, sequentially I 2 L elements A 4 ,
A 5 is activated, transistor T 7 is turned on, drive circuit 9 1 is activated, and light emitting diode 2 1 remains lit. Further, based on the operation of the drive circuit 9 1 , the output terminal of the I 2 L element A 1 of the detection circuit 3 1 is inverted from the L level to the H level. Further, since the capacitor 16 of the auxiliary current source circuit 7 is charged, the potential of the voltage between its terminals and the potential of the connection point 17 become H level.

スイツチ1oを押すとスイツチ駆動回路が作動
し、発光ダイオード2oが点灯保持される。同時
にI2L回路A6からF/F41にリセツト信号が伝
送されF/F41の記憶を解除する。このように
して信号入力段のスイツチ1をセツトすると記憶
回路4によつて記憶される。このような状態のと
きに主電源が遮断されたとすると補助電流源回路
7からインジエクタ電流がF/F41〜4oのI2L
素子に供給され記憶が保持される。しかし、長時
間主電源が遮断されると、当然コンデンサ16の
容量が不足して記憶回路4のメモリーは消失され
る。そして、主電源が復帰されると主電源投入時
に補助電流源回路7のコンデンサ16の充電電荷
が完全に放電している場合は、電源電圧VCCから
表示灯21及びレベルシフト回路8を介してコン
デンサ16に充電電流が流れる為にスイツチ11
の接点間が略短絡状態となつてスイツチ11の接
点が疑似的にオン状態となり、信号入力段のスイ
ツチは予め定められた条件に基づき初期状態が設
定される。
When the switch 1 o is pressed, the switch drive circuit is activated and the light emitting diode 2 o is kept lit. At the same time, a reset signal is transmitted from the I 2 L circuit A 6 to the F/F 4 1 to release the memory of the F/F 4 1 . When the switch 1 of the signal input stage is set in this way, it is stored in the memory circuit 4. If the main power supply is cut off in such a state, the injector current from the auxiliary current source circuit 7 will be I 2 L of F/F4 1 to 4 o.
It is supplied to the element and the memory is retained. However, if the main power supply is cut off for a long period of time, the capacitor 16 will naturally have insufficient capacity and the memory of the storage circuit 4 will be erased. Then, when the main power is restored, if the charge in the capacitor 16 of the auxiliary current source circuit 7 is completely discharged when the main power is turned on, the voltage is transferred from the power supply voltage V CC through the indicator light 2 1 and the level shift circuit 8. Since the charging current flows to the capacitor 16, the switch 1 1
The contacts of the switch 11 are brought into a substantially short-circuited state, and the contacts of the switch 11 are pseudo-on, and the switch at the signal input stage is set to its initial state based on predetermined conditions.

尚、レベルシフト回路8は、表示灯21とスイ
ツチ11の接続点17の電位をレベルシフトする
機能を有するものであり、接続点17の電位を補
助電流電回路7のコンデンサ16の充電時の端子
間電圧の電位に近づけ、コンデンサ16の充電電
位が低下した際に、電源電圧VCCを表示灯21等を
介してコンデンサ16に印加する機能を果たすも
のであり、種々の公知の回路によつて形成し得
る。
The level shift circuit 8 has a function of level shifting the potential at the connection point 17 between the indicator lamp 2 1 and the switch 1 1 , and changes the potential at the connection point 17 to the level at which the capacitor 16 of the auxiliary current circuit 7 is charged. The function is to apply the power supply voltage V CC to the capacitor 16 through the indicator light 2 1 etc. when the charging potential of the capacitor 16 decreases, and it is similar to the potential of the voltage between the terminals of the capacitor 16. It can be formed by

無論、第4図の実施例に限定されることなく所
定の電流増幅度を得たい場合はI2L素子を数段に
接続したり、公知の種々の方法がなされる。
Of course, the present invention is not limited to the embodiment shown in FIG. 4, and if it is desired to obtain a predetermined current amplification degree, various known methods such as connecting I 2 L elements in several stages may be used.

上述のように本考案のスイツチ回路は補助電流
源回路7の充電回路部の電位を監視する回路系を
有し、放電状態にコンデンサ16があるときは、
予め定められた所定のスイツチが疑似的にオン状
態に設定される。或いは、記憶回路が作動してい
るときはその記憶に基づきスイツチが復帰され
る。従つて、主電源投入時或いは復帰時に不安定
な動作状態となることがなく、安定したスイツチ
回路を簡便な回路によつて提供できる利点を有し
ている。
As mentioned above, the switch circuit of the present invention has a circuit system that monitors the potential of the charging circuit section of the auxiliary current source circuit 7, and when the capacitor 16 is in a discharged state,
A predetermined switch is set to a pseudo-on state. Alternatively, when the memory circuit is operating, the switch is reset based on the memory. Therefore, there is no possibility of unstable operation when the main power is turned on or restored, and there is an advantage that a stable switch circuit can be provided by a simple circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係るスイツチ回路のブロツク
図、第2図はI2L素子の記号を示す図であり、第
3図はその等価回路図、第4図が本考案のスイツ
チ回路の一実施例を示す回路図である。 1,11〜1o:スイツチ、2,21〜2o:表示
灯、3,31〜3o:検出回路、4:記憶回路、4
〜4o:フリツプ・フロツプ、5,51〜5o:電
子スイツチ、6:電流源回路、7:補助電流源回
路、8:レベルシフト回路、9,91〜9o:駆動
回路、10:電圧源、11,13:インジエクタ
抵抗、12,14:ダイオード、15:抵抗、1
6:コンデンサ、18:信号伝送回路、A1
A10:I2L素子、T1〜T9:トランジスタ。
Fig. 1 is a block diagram of a switch circuit according to the present invention, Fig. 2 is a diagram showing the symbol of an I 2 L element, Fig. 3 is an equivalent circuit diagram thereof, and Fig. 4 is a diagram of a switch circuit according to the present invention. FIG. 2 is a circuit diagram showing an example. 1, 1 1 ~ 1 o : Switch, 2, 2 1 ~ 2 o : Indicator light, 3, 3 1 ~ 3 o : Detection circuit, 4: Memory circuit, 4
1 to 4 o : flip-flop, 5, 5 1 to 5 o : electronic switch, 6: current source circuit, 7: auxiliary current source circuit, 8: level shift circuit, 9, 9 1 to 9 o : drive circuit, 10: Voltage source, 11, 13: Injector resistance, 12, 14: Diode, 15: Resistor, 1
6: Capacitor, 18: Signal transmission circuit, A 1 ~
A10 : I2L element, T1 to T9 : transistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 表示灯と一対となつた自己復帰型の接点を有す
るスイツチが複数個配列された信号入力段と、該
信号入力段からの信号をパルスに変換するI2L素
子を含む検出回路と、前記スイツチの接点の数に
対応するI2L素子からなるフリツプ・フロツプで
構成され、該検出回路からのパルス信号を記憶す
る記憶回路と、該記憶回路からの信号に基づいて
複数の信号の内の一つの信号を選択する電子スイ
ツチを作動させると共に、前記表示灯の一つを点
灯する駆動回路と、前記検出回路と記憶回路に含
まれる各I2L素子にインジエクタ電流を注入する
電流源回路と、該電流源回路から充電電流が供給
されると共に、主電源遮断時にフリツプ・フロツ
プで構成された該記憶回路にインジエクタ電流を
注入する抵抗とコンデサを含む補助電流源回路
と、該補助電流源回路と該電流源回路との接続点
にダイオードのカソードが接続され、該ダイオー
ドのアノードと前記スイツチの所定の接点と表示
灯との接続点間に接続されたレベルシフト回路と
を具え、主電源遮断時、該補助電流源回路からイ
ンジエクタ電流を該記憶回路のフリツプ・フロツ
プに供給してラツチ状態を保持し、主電源復帰時
に該記憶回路のラツチ状態に応じて遮断前の状態
に復帰させると共に、該補助電流源回路のコンデ
ンサが放電状態にある場合は、該補助電流源回路
の該コンデンサに該レベルシフト回路を介して充
電電流が供給されることによつて前記所定のスイ
ツチの接点端子間を短絡状態とすることを特徴と
するスイツチ回路。
a signal input stage in which a plurality of switches each having a self-resetting contact paired with an indicator lamp are arranged; a detection circuit including an I 2 L element that converts a signal from the signal input stage into a pulse; It is composed of a flip-flop consisting of I 2 L elements corresponding to the number of contacts, and includes a memory circuit that stores the pulse signal from the detection circuit, and a memory circuit that stores one of the plurality of signals based on the signal from the memory circuit. a drive circuit that operates an electronic switch that selects one signal and lights one of the indicator lights; a current source circuit that injects an injector current into each I 2 L element included in the detection circuit and storage circuit; A charging current is supplied from the current source circuit, and an auxiliary current source circuit includes a resistor and a capacitor that injects an injector current into the storage circuit configured with a flip-flop when the main power supply is cut off; The cathode of a diode is connected to the connection point with the current source circuit, and the level shift circuit is connected between the anode of the diode and the connection point between a predetermined contact point of the switch and the indicator light, and when the main power is cut off, , the injector current is supplied from the auxiliary current source circuit to the flip-flop of the memory circuit to maintain the latch state, and when the main power is restored, the memory circuit is returned to the state before the cut-off according to the latch state of the memory circuit. When the capacitor of the auxiliary current source circuit is in a discharged state, a charging current is supplied to the capacitor of the auxiliary current source circuit via the level shift circuit, thereby shorting the contact terminals of the predetermined switch. A switch circuit characterized by a state.
JP15181182U 1982-10-06 1982-10-06 switch circuit Granted JPS5955826U (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP15181182U JPS5955826U (en) 1982-10-06 1982-10-06 switch circuit
US06/537,825 US4633444A (en) 1982-10-06 1983-09-30 Switch circuit provided with means for setting up the initial condition thereof
DE19833336447 DE3336447A1 (en) 1982-10-06 1983-10-06 SWITCHING UNIT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15181182U JPS5955826U (en) 1982-10-06 1982-10-06 switch circuit

Publications (2)

Publication Number Publication Date
JPS5955826U JPS5955826U (en) 1984-04-12
JPH0334805Y2 true JPH0334805Y2 (en) 1991-07-24

Family

ID=33307414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15181182U Granted JPS5955826U (en) 1982-10-06 1982-10-06 switch circuit

Country Status (1)

Country Link
JP (1) JPS5955826U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6059615A (en) * 1983-09-09 1985-04-06 松下電器産業株式会社 Switch circuit

Also Published As

Publication number Publication date
JPS5955826U (en) 1984-04-12

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