JPH0326682Y2 - - Google Patents

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Publication number
JPH0326682Y2
JPH0326682Y2 JP502883U JP502883U JPH0326682Y2 JP H0326682 Y2 JPH0326682 Y2 JP H0326682Y2 JP 502883 U JP502883 U JP 502883U JP 502883 U JP502883 U JP 502883U JP H0326682 Y2 JPH0326682 Y2 JP H0326682Y2
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JP
Japan
Prior art keywords
circuit
switch
current source
memory
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP502883U
Other languages
Japanese (ja)
Other versions
JPS59111330U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP502883U priority Critical patent/JPS59111330U/en
Priority to US06/537,825 priority patent/US4633444A/en
Priority to DE19833336447 priority patent/DE3336447A1/en
Publication of JPS59111330U publication Critical patent/JPS59111330U/en
Application granted granted Critical
Publication of JPH0326682Y2 publication Critical patent/JPH0326682Y2/ja
Granted legal-status Critical Current

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  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Description

【考案の詳細な説明】 本考案は手動スイツチからの信号をスイツチ駆
動回路を介し電子スイツチ(アナログ・スイツチ
等)に伝達して開閉動作をさせるスイツチ回路に
関し、殊に主電源投入時スイツチの初期状態を設
定する機能を具えたスイツチ回路に係る。
[Detailed description of the invention] The present invention relates to a switch circuit that transmits a signal from a manual switch to an electronic switch (analog switch, etc.) via a switch drive circuit to open/close the switch. It relates to a switch circuit that has a function to set the state.

自動復帰形の接点を具えるスイツチの作動を記
憶して所定の電子スイツチを開閉するようになさ
れたスイツチ回路では、主電源遮断時であつても
スイツチの動作を記憶回路に保持する補助電流源
回路を具えている。しかし、長時間主電源が遮断
された場合は、補助電流源回路の容量が不足して
記憶回路の記憶が消去される可能性があり、記憶
が消去された場合は主電源復帰時に不安定な設定
条件となる欠点がある。
In a switch circuit that stores the operation of a switch with an automatic reset type contact and opens or closes a predetermined electronic switch, an auxiliary current source is used to maintain the switch operation in the memory circuit even when the main power is cut off. It has a circuit. However, if the main power is cut off for a long time, the capacity of the auxiliary current source circuit may become insufficient and the memory in the memory circuit may be erased. If the memory is erased, the memory may become unstable when the main power is restored. There is a drawback that is a setting condition.

本考案は上述の如き欠点を解消するもので、そ
の主な目的は主電源投入時に補助電流源回路の能
力が不充分なときは(記憶消去時)予め定められ
たスイツチをオンとして初期状態を設定する機能
を具えたスイツチ回路を提供するにある。
The present invention is intended to eliminate the above-mentioned drawbacks, and its main purpose is to turn on a predetermined switch when the auxiliary current source circuit is insufficient in capacity when the main power is turned on (when erasing memory) to restore the initial state. The purpose of the present invention is to provide a switch circuit with a setting function.

また、補助電流源回路に含まれる充電回路の充
電々位が高電位のときは記憶回路の設定条件によ
つてスイツチを作動させるスイツチ回路を提供す
るにある。
Another object of the present invention is to provide a switch circuit that operates a switch according to a setting condition of a memory circuit when the charging voltage of a charging circuit included in the auxiliary current source circuit is at a high potential.

本考案のスイツチ回路は、複数の表示灯と対に
接続され自動復帰形の接点を有するスイツチが設
けられた信号入力段と、該信号入力段からの信号
をパルスに変換する検出回路と該検出回路からの
信号を記憶する記憶回路と、該記憶回路からの信
号に基づいて所定の表示灯を点灯保持する駆動回
路と、該記憶回路の信号に基づいて作動する電子
スイツチと、前記検出回路と記憶回路に電流を供
給する電流源回路と、該電流源回路から充電電流
が供給され、主電源遮断時に該記憶回路に電流を
供給するコンデンサを含む補助電流源回路と、該
信号入力段の所定スイツチの接点間に並列接続さ
れたコンデンサとを具え、主電源投入時に該電流
源回路から充電々流が該コンデンサに供給される
ことによつて所定のスイツチの接点間を短絡して
初期状態を設定するものである。
The switch circuit of the present invention includes a signal input stage provided with a switch connected in pairs to a plurality of indicator lights and having an automatic return type contact, a detection circuit that converts a signal from the signal input stage into a pulse, and a detection circuit that converts a signal from the signal input stage into a pulse. A memory circuit that stores signals from the circuit, a drive circuit that keeps a predetermined indicator light turned on based on the signal from the memory circuit, an electronic switch that operates based on the signal of the memory circuit, and the detection circuit. a current source circuit that supplies current to the storage circuit; an auxiliary current source circuit that is supplied with charging current from the current source circuit and includes a capacitor that supplies current to the storage circuit when the main power supply is cut off; and a predetermined portion of the signal input stage. A capacitor is connected in parallel between the contacts of the switch, and when the main power is turned on, a charging current is supplied from the current source circuit to the capacitor, thereby shorting the contacts of a predetermined switch and establishing an initial state. This is what you set.

以下、本考案に係るスイツチ回路に就いて第1
図乃至第4図に基づき説明する。
Below, the first part of the switch circuit according to the present invention will be explained.
This will be explained based on FIGS. 4 to 4.

第1図はスイツチ回路のブロツク図である。信
号入力段は自己復帰型の接点を有するスイツチ1
と表示灯2から形成されている。検出回路3、記
憶回路4及び駆動回路9はスイツチ駆動回路部で
ある。また、スイツチ1と表示灯2との接続点1
7と接地間にはコンデンサ8が接続され、コンデ
ンサ8の一端が抵抗14を介して電流源回路6と
補助電流源回路7に接続されている。検出回路3
はスイツチ1からの信号をパルスに変換して記憶
回路4に伝達され記憶される。更に信号は伝達さ
れ、電子スイツチ5を開閉すると共に駆動回路9
に信号を伝達し表示灯2の内の一つを点灯保持さ
せる。また、検出回路3の一部と記憶回路4がI2
L素子で形成されており、それらのI2L素子に電
流源回路6から抵抗11、ダイオード12並びに
抵抗13を介しインジエクタ電流が注入されてい
る。主電源投入時は補助電流源回路7に充電々流
が抵抗15を介しコンデンサ16に流れ込んでい
る。
FIG. 1 is a block diagram of a switch circuit. The signal input stage is a switch 1 with a self-returning contact.
and an indicator light 2. The detection circuit 3, memory circuit 4, and drive circuit 9 are a switch drive circuit section. Also, connection point 1 between switch 1 and indicator light 2
A capacitor 8 is connected between the capacitor 7 and the ground, and one end of the capacitor 8 is connected to the current source circuit 6 and the auxiliary current source circuit 7 via a resistor 14. Detection circuit 3
converts the signal from switch 1 into a pulse, which is transmitted to storage circuit 4 and stored. Furthermore, the signal is transmitted to open and close the electronic switch 5 and also to the drive circuit 9.
A signal is transmitted to the indicator light 2 to cause one of the indicator lights 2 to remain lit. Also, a part of the detection circuit 3 and the storage circuit 4 are I 2
The injector current is injected into these I 2 L elements from a current source circuit 6 through a resistor 11, a diode 12, and a resistor 13. When the main power is turned on, a charging current flows into the auxiliary current source circuit 7 through the resistor 15 and into the capacitor 16.

さて、主電源遮断時は補助電流源回路7から記
憶回路4を形成するI2L回路にインジエクタ電流
が注入され記憶を保持している。しかし、補助電
流源回路7の容量が所定のレベル以下となると、
記憶回路4の記憶は消去される。主電源投入時に
記憶回路が消去された状態のときは電流源回路6
から抵抗14を介しコンデンサ8に充電々流が流
れ込み、信号入力段の所定のスイツチ1の接点間
が疑似的に短絡されオン状態となる。このように
して、信号入力段のスイツチ1は予め定められた
状態(初期状態)に設定される。無論、表示灯
2、電子スイツチ5、記憶回路4がこの初期条件
に沿つて作動する。そして、コンデンサ8が充電
されると接続点17の電位は高電位となり、信号
入力段のスイツチ1が任意に設定できる状態とな
る。信号入力段の他のスイツチ1をオンとする
と、そのスイツチに対応する表示灯2が点灯する
と共に、主電源投入時にオン状態にあつたスイツ
チ1は消灯する。そして、この新たに設定された
条件が記憶回路4によつて記憶される。また、こ
の状態で主電源が遮断されると補助電流源回路7
から記憶回路4に電流が注入され、記憶が保持さ
れる。そして、スイツチ1の設定条件を記憶して
いる状態で主電源が復帰するとその設定条件に基
づいて表示灯2、電子スイツチ5が作動する。
Now, when the main power supply is cut off, an injector current is injected from the auxiliary current source circuit 7 into the I 2 L circuit forming the memory circuit 4 to maintain the memory. However, when the capacity of the auxiliary current source circuit 7 falls below a predetermined level,
The memory in the memory circuit 4 is erased. If the memory circuit is erased when the main power is turned on, the current source circuit 6
A charging current flows into the capacitor 8 through the resistor 14, and the contacts of a predetermined switch 1 in the signal input stage are pseudo short-circuited and turned on. In this way, switch 1 at the signal input stage is set to a predetermined state (initial state). Of course, the indicator light 2, electronic switch 5, and memory circuit 4 operate according to this initial condition. When the capacitor 8 is charged, the potential at the connection point 17 becomes a high potential, and the switch 1 at the signal input stage can be set arbitrarily. When another switch 1 in the signal input stage is turned on, the indicator light 2 corresponding to that switch lights up, and the switch 1 that was in the on state when the main power was turned on goes out. This newly set condition is then stored in the storage circuit 4. In addition, if the main power supply is cut off in this state, the auxiliary current source circuit 7
A current is injected into the memory circuit 4 from then on, and the memory is retained. When the main power is restored while the setting conditions of the switch 1 are stored, the indicator lamp 2 and the electronic switch 5 are activated based on the setting conditions.

第4図は本考案のスイツチ回路の一実施例であ
る。尚、I2L素子の記号を第2図に示し、その等
価回路を第3図に記した。Iはインジエクタ端子
である。第4図に於て、信号入力段は複数の自己
復帰型の接点を有するスイツチ11〜1oと発光ダ
イオート21〜2oが夫々直列接続されている。検
出回路31はトランジスタT1〜T3とI2L素子A1
により形成され、検出回路3oも同様な構成とな
つている。記憶回路41はI2L素子A2,A3からな
るフリツプ・フロツプ(以下F/Fと略す。)か
ら形成され、F/F4oも同様な構成となつてい
る。18は信号伝送回路であり、I2L素子A4の出
力端子の一つは電子スイツチ51へ、他の出力端
子はI2L素子A5を介し駆動回路91のトランジス
タT7のベースに接続されている。I2L素子A9
同様な接続となつている。電子スイツチ51〜5o
はアナログ・スイツチ等であり、a,nは信号源
である。
FIG. 4 shows an embodiment of the switch circuit of the present invention. The symbol of the I 2 L element is shown in FIG. 2, and its equivalent circuit is shown in FIG. I is an injector terminal. In FIG. 4, the signal input stage includes switches 1 1 to 1 o having a plurality of self-resetting contacts and light emitting diodes 2 1 to 2 o , which are connected in series. The detection circuit 31 is formed by transistors T1 to T3 , an I2L element A1, etc., and the detection circuit 3o has a similar configuration. The memory circuit 4 1 is formed from a flip-flop (hereinafter abbreviated as F/F) consisting of I 2 L elements A 2 and A 3 , and the F/F 4 o has a similar structure. 18 is a signal transmission circuit, one of the output terminals of the I 2 L element A 4 is connected to the electronic switch 5 1 , and the other output terminal is connected to the base of the transistor T 7 of the drive circuit 9 1 via the I 2 L element A 5 . It is connected to the. I 2 L element A 9 is also connected in a similar manner. Electronic switch 5 1 ~ 5 o
is an analog switch or the like, and a and n are signal sources.

スイツチ回路を形成するI2L素子は電流源回路
6からインジエクタ電流を供給されている。その
構成は電圧源回路10及びインジエクタ抵抗11
とダイオード12並びにインジエクタ抵抗13か
ら形成されている。インジエクタ抵抗11の他端
は記憶回路4を形成するI2L素子A2,A3…A7
A8にインジエクタ端子に接続されると共に補助
電流源回路7に接続される。その接続点19は抵
抗14を介してコンデンサ8に接続される。そし
て、コンデンサ8の両端はスイツチ11の端子に
夫々接続される。また、補助電流源回路7は抵抗
15、電圧源16から、形成されている。電圧源
16はコンデンサで形成する。
The I 2 L element forming the switch circuit is supplied with an injector current from the current source circuit 6. Its configuration is a voltage source circuit 10 and an injector resistor 11.
, a diode 12 and an injector resistor 13. The other end of the injector resistor 11 is connected to I 2 L elements A 2 , A 3 ...A 7 , which form the memory circuit 4.
A 8 is connected to the injector terminal and also to the auxiliary current source circuit 7. The connection point 19 is connected to the capacitor 8 via the resistor 14. Both ends of the capacitor 8 are connected to the terminals of the switch 11 , respectively. Further, the auxiliary current source circuit 7 is formed from a resistor 15 and a voltage source 16. Voltage source 16 is formed by a capacitor.

さて、このスイツチ回路の主電源を投入する。
補助電流源回路7は放電された状態となつている
ので補助電流源回路7の入出力端子19の電位は
略零電位となつている。従つて、記憶回路4は記
憶を消去された状態にあり、電流源回路6からコ
ンデンサ8に充電々流が流れる。また、通常補助
電流源回路7はコンデンサと抵抗から形成されて
おり、コンデンサ8の充電と同時に充電が開始さ
れる。その充電速度はコンデンサ8の方が早く行
なわれる必要がある。このように主電源投入と同
時にコンデンサ8に充電々流が流れる為にスイツ
チ11は短絡状態となり、スイツチオン信号が伝
送され、検出回路31のトランジスタT1〜T3がオ
フとなる。そして、I2L素子A1の入力端子の電位
は高電位(Hレベル)となるので出力端子はLレ
ベルとなると同時にF/F4oをリセツトする。
また、順次I2L素子A4,A5が作動し、トランジ
スタT7がオンとなつて駆動回路91が作動し、発
光ダイオード21は点灯状態を保持する。また、
駆動回路91の動作に基づき検出回路31のI2L素
子A1の出力端子はLレベルからHレベルに反転
する。このようにして、予め定められた設定状態
に入力段のスイツチが設定される。
Now, turn on the main power to this switch circuit.
Since the auxiliary current source circuit 7 is in a discharged state, the potential of the input/output terminal 19 of the auxiliary current source circuit 7 is approximately zero potential. Therefore, the memory circuit 4 is in a state where the memory has been erased, and a charging current flows from the current source circuit 6 to the capacitor 8. Further, the auxiliary current source circuit 7 is usually formed from a capacitor and a resistor, and charging is started at the same time as the capacitor 8 is charged. The capacitor 8 needs to be charged faster. As described above, since a charging current flows through the capacitor 8 at the same time as the main power is turned on, the switch 11 becomes short-circuited, a switch-on signal is transmitted, and the transistors T1 to T3 of the detection circuit 31 are turned off. Then, since the potential of the input terminal of the I 2 L element A 1 becomes a high potential (H level), the output terminal becomes L level and at the same time resets the F/F 4 o .
Furthermore, the I 2 L elements A 4 and A 5 are activated in sequence, the transistor T 7 is turned on, the drive circuit 9 1 is activated, and the light emitting diode 2 1 is maintained in a lighting state. Also,
Based on the operation of the drive circuit 9 1 , the output terminal of the I 2 L element A 1 of the detection circuit 3 1 is inverted from L level to H level. In this way, the input stage switch is set to a predetermined setting state.

次に、この設定された状態で他のスイツチ1o
を押すとスイツチ駆動回路が作動し、発光ダイオ
ード2oが点灯保持される。同時にI2L回路A6
らF/F41にリセツト信号が伝送されF/F41
の記憶を解除する。このようにして信号入力段の
スイツチ1をセツトすると記憶回路4によつて記
憶される。また、このような状態のときに主電源
が遮断されたとすると補助電流源回路7からイン
ジエクタ電流がF/F41〜4oのI2L素子に供給
され記憶が保持される。しかし、長時間主電源が
遮断されると、補助電流源回路7の容量が不足し
て記憶回路4のメモリーは消去される。そして、
主電源が復帰されると主電源投入時と同様にコン
デンサ8に充電々流が流れ、スイツチ11の接点
が疑似的にオン状態となり、信号入力段のスイツ
チは予め定められた条件に基づき初期状態が設定
される。
Next, with this setting, other switches 1 o
When is pressed, the switch drive circuit is activated and the light emitting diode 2o is kept lit. At the same time, a reset signal is transmitted from I2L circuit A6 to F/ F41 .
Cancel the memory of. When the switch 1 of the signal input stage is set in this way, it is stored in the memory circuit 4. Further, if the main power supply is cut off in such a state, the injector current is supplied from the auxiliary current source circuit 7 to the I 2 L elements of F/Fs 4 1 to 4 o , and the memory is retained. However, if the main power supply is cut off for a long time, the capacity of the auxiliary current source circuit 7 becomes insufficient and the memory of the storage circuit 4 is erased. and,
When the main power is restored, a charging current flows through the capacitor 8 in the same way as when the main power is turned on, the contacts of switch 11 are pseudo-on, and the signal input stage switch is initialized based on predetermined conditions. The state is set.

無論、第4図の実施例に限定されることなく所
定の電流増幅度を得たい場合はI2L素子を数段に
接続したり、公知の種々の方法がなされる。また
スイツチ1はトランジスタ・スイツチであつても
良い。
Of course, the present invention is not limited to the embodiment shown in FIG. 4, and if it is desired to obtain a predetermined current amplification degree, I 2 L elements may be connected in several stages, or various known methods may be used. Further, the switch 1 may be a transistor switch.

上述のように本考案のスイツチ回路は予め定め
られたスイツチにコンデンサを付加することによ
り、主電源投入時にそのコンデンサに充電々流を
流し込んでスイツチの端子間を短絡させて、疑似
的に所定のスイツチをオン状態として初期状態を
設定するものである。記憶回路が作動状態にあれ
ば、記憶された設定条件でスイツチ回路が復帰す
る。従つて、主電源投入時或いは復帰時に不安定
な動作状態となることがなく、安定した信頼性の
高いスイツチ回路を簡便な回路によつて提供する
ことができる利点を有している。
As mentioned above, the switch circuit of the present invention adds a capacitor to a predetermined switch, and when the main power is turned on, a charging current flows into the capacitor to short-circuit the terminals of the switch, thereby creating a pseudo-predetermined signal. This is to set the initial state by turning on the switch. If the memory circuit is in an operating state, the switch circuit is restored under the memorized setting conditions. Therefore, there is no possibility of unstable operation when the main power is turned on or restored, and there is an advantage that a stable and highly reliable switch circuit can be provided by a simple circuit.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係るスイツチ回路のブロツク
図、第2図はI2L素子の記号を示す図であり、第
3図はその等価回路図、第4図が本考案のスイツ
チ回路の一実施例を示す回路図である。 1……スイツチ、2……表示灯、3……検出回
路、4……記憶回路、5……電子スイツチ、6…
…電流源回路、7……補助電流源回路、8……コ
ンデンサ、9……駆動回路、10……電圧源、1
1,13……インジエクタ抵抗、A1〜A10……I2
L素子。
Fig. 1 is a block diagram of a switch circuit according to the present invention, Fig. 2 is a diagram showing the symbol of an I 2 L element, Fig. 3 is an equivalent circuit diagram thereof, and Fig. 4 is a diagram of a switch circuit according to the present invention. FIG. 2 is a circuit diagram showing an example. 1... Switch, 2... Indicator light, 3... Detection circuit, 4... Memory circuit, 5... Electronic switch, 6...
...Current source circuit, 7...Auxiliary current source circuit, 8...Capacitor, 9...Drive circuit, 10...Voltage source, 1
1, 13...Injector resistance, A1 ~ A10 ... I2
L element.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数の表示灯2と対に接続され、自動復帰形の接
点を有するスイツチ1が設けられた信号入力段
と、該信号入力段からの信号をパルスに変換する
検出回路3と、該検出回路からの信号を記憶する
記憶回路4と、該記憶回路からの信号に基づいて
所定の表示灯を点灯保持する駆動回路9と、該記
憶回路の信号に基づいて作動する電子スイツチ5
と、前記検出回路と記憶回路に電流を供給する電
流源回路6と、該電流源回路から充電電流が供給
され、主電源遮断時に該記憶回路に電流を供給す
るコンデンサを含む補助電流源回路7と、該信号
入力段の所定スイツチの接点間に並列接続された
コンデンサ8とを具え、主電源投入時に電流源回
路6からコンデンサ8に充電々流が供給されるこ
とによつて該信号入力段の所定のスイツチの接点
間を短絡して初期状態を設定することを特徴とす
るスイツチ回路。
A signal input stage connected in pairs to a plurality of indicator lights 2 and provided with a switch 1 having an automatic return type contact; a detection circuit 3 for converting a signal from the signal input stage into a pulse; a memory circuit 4 that stores signals from the memory circuit; a drive circuit 9 that keeps a predetermined indicator light lit based on the signal from the memory circuit; and an electronic switch 5 that operates based on the signal from the memory circuit.
, a current source circuit 6 that supplies current to the detection circuit and the memory circuit, and an auxiliary current source circuit 7 that includes a capacitor that is supplied with charging current from the current source circuit and supplies current to the memory circuit when the main power supply is cut off. and a capacitor 8 connected in parallel between the contacts of a predetermined switch of the signal input stage. A switch circuit characterized in that an initial state is set by short-circuiting the contacts of a predetermined switch.
JP502883U 1982-10-06 1983-01-18 switch circuit Granted JPS59111330U (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP502883U JPS59111330U (en) 1983-01-18 1983-01-18 switch circuit
US06/537,825 US4633444A (en) 1982-10-06 1983-09-30 Switch circuit provided with means for setting up the initial condition thereof
DE19833336447 DE3336447A1 (en) 1982-10-06 1983-10-06 SWITCHING UNIT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP502883U JPS59111330U (en) 1983-01-18 1983-01-18 switch circuit

Publications (2)

Publication Number Publication Date
JPS59111330U JPS59111330U (en) 1984-07-27
JPH0326682Y2 true JPH0326682Y2 (en) 1991-06-10

Family

ID=30136620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP502883U Granted JPS59111330U (en) 1982-10-06 1983-01-18 switch circuit

Country Status (1)

Country Link
JP (1) JPS59111330U (en)

Also Published As

Publication number Publication date
JPS59111330U (en) 1984-07-27

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