JPH0334799Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a key code generation circuit for an electronic musical instrument that divides a large number of switches into a plurality of blocks, scans each block, and generates and outputs a key code corresponding to a key switch that is in an on state through a simple procedure. It is something.

Conventionally, in electronic musical instruments having many switches (hereinafter referred to as keyswitches) such as a keyboard switch, tone selection switch, volume selection switch, etc., the on/off state of each key switch has been detected by wiring each key switch. However, this method is uneconomical and complicated because it requires a lot of wiring.
In recent years, organ systems using digital technology have been proposed, and key switch on/off signals are time-division multiplexed by arranging key switches in row lines and column lines of a matrix circuit and sequentially scanning all the key switches one by one. However, in this method, all the key switches are sequentially scanned, resulting in uneven time lag due to the on/off operation of the key switches and the timing of scanning. In order to reduce this time difference, it was necessary to increase the scanning speed. In addition, since all the key switches are scanned regardless of the number of key switches in use, the scanning time is determined by the number of all the key switches, and the time lag between key switch on/off operation and detection becomes large. To reduce this lag, it was necessary to increase the scanning speed. Various scanning methods have been proposed to improve this point, but for example, all the key switches are arranged in row lines and column lines of a matrix circuit, and signals are applied to all row lines at the same time. In this method, the included row lines and column lines are sequentially scanned one by one to detect an on-state key switch. However, this method detects the row line and column line twice, so to speak, the state of the key switch is sampled twice. If the state of the key switch changes between two samplings, it is possible that an unnecessary key switch will be detected, time will be wasted, or in some cases, an erroneous detection will occur.

An object of the present invention is to provide a key code generation circuit for an electronic musical instrument that generates and outputs a key code corresponding to an on-state key switch in a short time without sampling the key switch multiple times.

In order to achieve the above object, the key code generation circuit of the electronic musical instrument of the present invention includes a matrix circuit that divides a matrix key switch into blocks of multiple lines and sequentially applies a block code to each block for scanning, and a matrix circuit that scans a matrix key switch by sequentially applying a block code to each block. key switch is 1
means for temporarily stopping the scanning of a block when there is one or more keyswitches; and a means for parallel-to-serial converting a signal indicating an on state according to the priority given to the key switch in the block and outputting the signal corresponding to the on state key switch in the block. a shift register circuit that sequentially generates bit codes corresponding to the on-state key switches in the block; and means for detecting that all the bit codes corresponding to the on-state key switches in the block have been generated, and stopping processing of the remaining off-state key switches and moving to scanning of the next block. The bit code from the shift register circuit and the corresponding block code are combined and output as a key code.

The present invention will be described in detail below with reference to examples.

FIG. 1 is a schematic explanatory diagram of an embodiment of the present invention.
In the figure, a key switch matrix 1 has a plurality of key switches arranged in, for example, n rows and m columns. The row lines are block lines and the column lines are bit lines. The block decoder 2 follows the block code from the block counter 3 and
A signal is applied to one of the block lines of the book. Of a group of m key switches arranged on a designated block line and forming one block, the key switches in the on state output key-on signals to the respective bit lines. Clock φ from clock generator 4 is applied to logic gate 5. Logic gate 5 supplies clock φ to block counter 3 when there is no key-on signal on the m bit lines from key switch matrix circuit 1. When the clock φ is input, the block counter 3 repeatedly counts and outputs in the order of 1, 2, 3, 4, . . . , n. Furthermore, if there is a key-on signal on one or more of the m bit lines from the key switch matrix circuit 1, the application of the next clock φ to the block counter 3 is temporarily stopped. Then, the key-on signals in the block from the key switch matrix circuit 1 are input in parallel to the shift register and written therein, and then output in series to sequentially output the key codes corresponding to the on-state key switches in the block. When the key-on signals of all bits have been output as bit codes, the logic gate 5 applies the clock φ to the block counter 3. Then, a key code consisting of a block code and a bit code corresponding to the on-state key switch is outputted through the logic gate 5.

FIG. 2 is a detailed explanatory diagram of the embodiment of FIG. 1.
Figures 4a to 4m are time charts showing the operation.

In FIG. 2, the key switch matrix circuit 1 has n=m=8. In the key switch matrix circuit 1, the intersection of the block line and the bit line indicated by a white circle is composed of a key switch and a diode, as shown enlarged in the drawing circle 30. Since the diodes form an OR gate, there are 8
It can be replaced with an input OR gate. The logic gate 5 is constituted by a combination of a gate circuit including a shift register 16 which inputs the on-state key switch bits of each block in parallel and shifts them in series, and a bit counter 18 which provides the timing of the bit code, which is the essential part of the present invention. Ru. That is, 8-bit line parallel signals from the key switch matrix circuit 1 are input in parallel to the shift register 16,
Switching and parallel-to-serial conversion are performed using a P/S signal from an AND gate 15, which will be described later, and a serial signal is output using a clock from a clock generator 4.

In the shift register 16, for example, as shown in the circuit example shown in FIG. 3, _P1 to _P8 input parallel inputs from the bit lines of the key switch matrix 1 to eight data selectors SEL connected in cascade, and output the P/S signal. When is at H level, selects _P1 to _P8 , and when is at L level, selects the previous stage DEF output. Note that the series input terminal is connected to ground (low level).

Next, in order to control block scanning depending on whether or not there is an on-state key switch signal on the bit line, each branch is branched from the middle of the 8-bit line and inputted to the OR circuit 10, and when there is no on-state key switch signal in a certain block, a low The AND gate 12 is opened via the OR gate 11 by the inverted level output signal, and the clock φ from the clock generator 4 is applied to the block counter 3 to increment the count, and then to the next block scan via the block decoder 2. Move. If the block has a key switch in the on state, the block scanning is temporarily stopped by the high H level output of the OR gate 10. Then, the H level output is transferred to a D-type flip-flop.
By applying the inverted signal of the Q output to the D terminal of the DFF 13 and inputting the output of the OR gate 10 to the AND gate 15, a P/S signal delayed by one clock from the H level output of the OR gate 10 is sent to the shift register 16. is applied to perform the above-mentioned series-to-parallel switching. At the same time, the bit counter 18 is reset by the H level output of the OR gate 10, and the AND gate 17 is opened, and a timing signal corresponding to the bit code of the bit line is generated using the clock φ from the clock generator 4, and is sent to the AND gate _202. and the serial output from the shift register 16 to output a bit code. On the other hand, the output of block counter 3 at that time is
Same shift register 16 put in AND gate 20 ₁
It performs a logical product with the serial output from and outputs a block code. The combination of these block codes and bit codes provides a key code corresponding to the key switch in the on state.

Furthermore, in this embodiment, when the bit codes input in parallel to the shift register 16 are shifted and output in series, after the final bit of the H level bits corresponding to the key switch in the on state is output, the remaining low level bits are left unused. Because it is necessary
When this is detected, the block counter 3 is immediately incremented to move on to the next block scan. Therefore, the parallel bit output of the shift register 16 is input to the NOR gate 19, and when all the bits are at the L level, the H level output is passed along with the Q output of the DFF 13 to the AND gate 14 to increment the block counter 3. In this way, the number of clocks required for one round of block scanning of the key switch matrix circuit 1 can be reduced, and the key code detection time can be shortened.

FIG. 4 assumes that, in the embodiment of FIG. 2, only the key switches corresponding to the third and fifth bits of the fifth block and the sixth bit of the seventh block are in the on state (indicated by black circles in FIG. 2). The following is a time chart for when this happens.

Now, as the block counter 3 counts, the block decoder 2 turns on the key switch matrix circuit 1.
H level signals are applied to the block lines 1, 2, 3, and 4 in this order. Since there is no key switch in the on state among the key switches from the first block to the fourth block, the OR gate 10 is at the L level, and the OR gate 10 is at the L level.
Gate 11 is inverted and at H level, AND
Gate 12 is open. Then, the fourth clock _φ4 is applied to the block counter 3 via the AND gate 12, and the count value of the block counter 3 (hereinafter referred to as block code) is set to "5", and the block decoder 2 sends an H level signal to the fifth block line. [Figure 4 a, b]. In the fifth block, the key switches for the third and fifth bits are in the on state, so the bit lines for the third and fifth bits go to H level, and the OR gate 10 goes to H level (FIG. 4c). At this time, the DFF 13 is delayed by one clock, and its Q output is at the L level (FIG. 4f), and therefore the output of the OR gate 15 is at the H level (FIG. 4h). The output is L level [Fig. 4 d], therefore AND gate 1
2 is closed [Fig. 4e]. From the next clock _φ5 , no clock is applied to the block counter 3, and the block code maintains the state of "5". Clock _φ5 is connected to shift register 1 via AND gate 15.
After applying the P/S signal to the key switch matrix circuit 6 and writing the 8-bit line parallel signal from the key switch matrix circuit 1, the ON signal bit is output as a serial signal by the clocks φ ₅ to _{φ 10} [Fig. 4 i] . and
Bit counter 18 at H level of OR gate 10
is reset, and the output of AND gate 17 [4th
A timing signal is applied from the bit counter 18 and a bit code is taken out from the AND gate ₂₀₂ [Fig. 4k]. Next, the output of the NOR gate 19, which inputs each bit of the shift register 16, outputs an H level after the clock _φ10 detects that all bit codes are 0 [Fig. 4l], and the AND gate 14, the OR gate 11, and the The block counter 3 is incremented through the gate 12 [FIG. 4g, d, e], and the sixth block is scanned with the clock _φ11 . Since there is no key switch in the ON state in the 6th block, the scanning of the 7th block is started at clock φ ₁₂ through the same procedure as φ ₁ to φ ₄ described above, and the 6th bit corresponding to the key switch in the ON state is scanned. The same procedure as for block 5 is followed. Since there is no key switch in the on state in the eighth block, the same procedure as φ ₁ to φ ₄ is followed. The number of clocks in one scanning cycle of all blocks is 21 as shown in the figure.
Used individually. The output code 20 of FIG. 4m is a combination of the block code of FIG. 4b and the bit code of FIG. 4k.

In this embodiment, the number of clocks used in one scanning cycle of each block is 21 as described above, but generally, the number of clocks used for one scanning cycle of each block is 21 (the bit value of the on-state key switch with the largest bit value + 1) for each block with an on-state key switch. It is expressed as the result of adding and then adding (number of blocks).

FIG. 5 is an explanatory diagram showing the configuration of another embodiment of the present invention. FIGS. 6a to 6l are time charts showing the operation.

5 differs from FIG. 2 in that a NOR circuit 19 is specially provided to reduce the number of clocks used in one block scanning cycle to detect the key code corresponding to the key switch in the on state.
to send this output signal to block counter 3.
The AND gate 14 is omitted, and instead, the fourth bit indicating the output of the final bit of the bit counter 18 is used as one input of the AND gate 11. As a result, scanning moves to the next block after all 8 bits of the key code corresponding to the on-state key switch inputted in parallel to the shift register 16 have been output. Therefore, in this case, the number of clocks for one scanning cycle is 24 as shown in FIG. Generally, the number of clocks is the sum of (number of blocks with on-state key switches) x 8 and (number of blocks).

The time chart in Figure 6 is gAND from Figure 4.
The gate 14 and the lNOR gate 19 are removed, and a fourth bit 14' of a g-bit counter is added in their place. Further, the shift period of the fifth block and the seventh block each requires eight clocks, and scanning is advanced to the next block by the fourth bit 14' of the bit counter corresponding to each final bit. Other details are the same as in FIG. 4.

Although the number of clocks per scanning period is greater than that of the embodiment shown in FIG. 2, the structure is clearly simplified.

As explained above, according to the present invention, a large number of key switches are divided into a plurality of blocks, each block is sequentially scanned, and when one or more key switches in the block are in the on state, scanning of the block is temporarily stopped. Then, they are inputted in parallel to a parallel-to-serial conversion circuit such as a shift register, outputted in series, and outputted a key code corresponding to an on-state key switch. When all of these are generated, the scanning of the next block is started. With this configuration, all the key switches can be scanned with an extremely small number of clocks, and the key code detection and generation time can be significantly shortened. Furthermore, the detection time is determined in relation to the key switch in the on state and the number of blocks, and unnecessary key switch scanning can be avoided as much as possible, thereby eliminating wasted time.

[Brief explanation of the drawing]

FIG. 1 is a schematic explanatory diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a specific circuit example of the main part of the embodiment of FIG. Figure a~
m is a time chart showing the operation of the embodiment of FIG. 2, FIG. 5 is an explanatory diagram showing the configuration of another embodiment of the present invention, and FIGS. 6 a to l show the operation of the embodiment of FIG. 5. This is a time chart. In the figure, 1 is the key switch matrix circuit, 2 is the block decoder, and 3 is the key switch matrix circuit.
4 is a block counter, 4 is a clock generator, 5 is a logic gate, 16 is a shift register, and 18 is a bit counter.

Claims (1)

[Claims for Utility Model Registration] Matrix circuits 1 to 4 that divide a matrix key switch into blocks of multiple lines and sequentially give a block code to each block for scanning, and one key switch that is in an on state in a certain block.
means 10 to 14 for temporarily stopping the scanning of a block when there is one or more keys; Shift register circuits 15 and 16 sequentially generate bit codes corresponding to the key switches, detect that all bit codes corresponding to the on-state key switches in the block have been generated, stop processing of the remaining off-state key switches, and start the next one. 1. A key code generation circuit for an electronic musical instrument, comprising means 14 and 19 for moving to block scanning, and for outputting a combination of a bit code from the shift register circuit and a corresponding block code as a key code.