JPH0334724A - Cmos prescaler - Google Patents

Abstract

PURPOSE:To eliminate the need for an inverter and to attain a high speed operation by connecting a signal between a 2N-th and a (2n+1)th flip-flops via a CMOS transfer gate whose on/off is controlled by a mode switching signal. CONSTITUTION:A signal between a 2N-th and a (2n+1)th flip-flops (FFs 2, 3 in this embodiment) is connected via a CMOS transfer gate whose on/off is controlled by a mode switching signal. That is, a terminal T1 of a TG1 is connected to a terminal Tc, a terminal T2 is connected to a terminal Td, a mode switching signal input terminal TM is connected to a gate to a p- channel transistor(TR) and a gate of an n-channel TR via an inverter IV 7. Moreover, TRs 1, 2 are provided, the drain of the TR 1 is connected to a terminal Td, the source is connected to ground and the gate is connected to the terminal TM, the drain of the TR 2 are connected to the terminal Td, the source is connected to ground and the gate is connected to the terminal TRST. Thus, the time when a signal outputted from a FF transmitted to the input terminal Td is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS prescaler with high speed and low power consumption.

[Conventional technology]

Generally, in various frequency synthesizers, etc., a CMOS prescaler that performs 1/(2N) and 1/(2N+1) frequency division is used, which allows the circuit to be converted into a digital IC, reduces power consumption, and eliminates the need for adjustment. It is used as a vessel. In particular, a CMOS prescaler using a dynamic circuit is important as a variable frequency divider for high frequencies because it can divide higher frequencies with lower power consumption than a prescaler using a static circuit.

FIG. 2(a) shows a CMOS prescaler circuit that performs frequency division by 1/4.115, as an example of a conventionally used dynamic CMOS prescaler with set/reset. This circuit consists of two two-way NOR circuit N0
Three CMOS with set/reset equipped with R1, N0R2, one inverter circuit IV2, an external clock input terminal, and a clock input terminal with an opposite phase of the external clock.
Dynasty flip-flop FFI, FF2. FF3
This is a variable frequency divider that has a basic configuration of 1/4.115 and switches the frequency division by 1/4.115 using a signal M at a mode switching terminal TM. In addition, in the circuit shown in FIG. 2 (al), the reset terminal R3T is set to FFI, F
F2. It is connected to the reset terminal of FF3, and FFlFF2. This circuit is connected to the set terminal of FF3 and has a function that allows the initial state to be set externally. Figure 2 (bl is Closoku Pulse CP
is a circuit diagram showing a dual-phase signal generation circuit that inputs clock pulses CLK and CLK, IV4 is an inverter. FlifbufurosopFFlFF2. F
F3 is a well-known set/reset dynamic flip-flop as shown in FIG. 3, which maintains the inversion of the signal at the input terminal when the external clock is input one cycle, and when the signal is input one cycle before the external clock. It is a single-phase output flip-flop that has the function of outputting the same signal as the input signal to the output terminal, and has the function of being able to be initialized by inputting a set/reset signal. In FIG. 3, Ql and Q3 are transfer gates, Q2 and Q4 are transistors, and IV5. IV6 is an inverter.

The operation of the circuit shown in FIG. 2 will be explained using positive logic.

When the mode switching signal M is rlJ, the initial state of each flip-flop is set by the signal R3T from the terminal TR5T.
Terminal signals a, b, 'c, represented by d, Te, Tf,
The states of c', d, e, and f are as shown in the initial values in Table 1,
It is assumed that each flip-flop holds an inverted value of the signal at its output terminal by a transfer gate Q3 (see FIG. 3).

Here, "1" represents a potential equal to or slightly lower than the positive potential, and "0" represents a potential equal to or slightly higher than the ground potential. Here, when a one-cycle clock is input from the outside, the Frisopflo knob FF1. FF2. FF3 performs the above-mentioned operation, and if the signal at the input terminal is rOJ, "1" is stored internally.
hold.

Also, if the signal held one cycle ago is "1",
The inverted "0", that is, the signal input manually one cycle before, is output to the output terminal. Similar operation is “1” as rOJ,
This holds true even if rOJ is read as "1". Therefore, after the initial state, the signals at the output terminals of each flip-flop after one cycle are b=rlJ, c=rOJ, and e=rOj, and the signals at the input terminals are a=rlJ, c'=rlJ. Become. d is always kept at "0" since M=rlJ.

This is state 1. From state 1 to state 2 every clock IJil#A by the operation of similar flip-flops.
, the signal value of each terminal changes from state 2 to state 3 and from state 3 to state 4. State M4 is the same as the initial state,
Therefore, from now on, this circuit repeats the same operation every four clock cycles to perform the 1/4 frequency division operation.

Next, a case where the mode switching signal M is "0" will be explained. The initial state of each flip-flop is determined by the signal R3T from the terminal TR3T, and the signals a and b in FIG.
, c, c', d, e, and f have the initial values shown in Table 2, and each flip-flop holds the inverted value of the signal at its output terminal by the transfer gate Q3. Here, when a one-cycle clock is input from the outside,
Frisopfrosob FFI, FF2. FF3 performs the above operation, and if the signal at the input terminal is rOJ, internal r
Hold lJ. Further, if the signal held one cycle ago is "1", the inverted rOJ, that is, the signal input one cycle ago, is outputted to the output terminal. A similar operation can be achieved by reading "1" as "O" and rOJ as rlJ. Therefore, the signals at the output terminals after one cycle of each Frinobuflow knob are b=rlJ, c=rOJ, and e=rOJ, and the signals at the input terminals are a=rlJ and C=``1''. d becomes "0" by the NOR logic between C' and M of N0R2. This is the shape Ml. Through the operation of a similar flip-flop, the No. 43 value of each terminal changes from state 1 to state B2, from state 2 to state 3, from state M3 to state 4, and from state 4 to state 5 every cycle of the clock. . The state B5 is the same as the initial state, and therefore, this circuit cyclically repeats the same operation every five clock cycles from now on, performing a frequency division operation by 115.

[Problem to be solved by the invention]

The conventional prescaler has been explained above, but the upper limit of the maximum operating frequency at which this prescaler can perform frequency division operation is determined by FF2-Tc-
This is the delay in the path IV2-Tc'-NOR2-Td. After clock input: Flip-flop FF2 has a delay t FF! The output signal is sent to the inverter IV via the terminal Tc.
2.

After a delay of t+vz, inverter IV2 transmits the inverted signal of the input signal to N0R2 via terminal Tc/. N0R2 transmits the inverted signal of the input signal to the terminal Td after a delay of tMo1t□. Division operation is possible only in a frequency band where the sum of these delays T is shorter than one period of the external clock, and the maximum operating frequency f is T tWFt + t IV2 + tN
It is expressed as Oll. Therefore, the conventional prescaler is
Even if the delay of the frequency divider is made small, IV2. Since it has to pass through the N0R2 circuit, it has the disadvantage that it cannot operate at a higher speed than the delay of these circuits.

The present invention was made in view of these points, and its purpose is to provide a high-speed C with low power consumption.
The purpose of the present invention is to provide a MOS prescaler.

[Means to solve the problem]

In order to achieve such an object, the present invention provides (2N+1
1/(2N) and 1/(2N+
1) In the frequency dividing CMOS prescaler, the signal connection between the 2Nth and 2N+1st flip-flops is performed via a CMo3I-transfer gate whose on/off is controlled by a mode switching signal, and the source is the power source and the drain is the The 1st. a second Mo3I-transistor;
By connecting a mode switching signal input terminal to the gate of the OS transistor and connecting a reset signal input terminal to the gate of the second Mo3 transistor, on/off of each Mo3 transistor is controlled.

[Effect]

The CMOS prescaler according to the present invention is faster than the conventional one because it does not require an inverter.

〔Example〕

Figure 1 is a circuit diagram showing a CMOS dynamic prescaler with a new configuration that is equipped with a circuit to eliminate the drawbacks of conventional circuits and enables division of frequencies higher than conventional ones. Parts or equivalent parts are given the same reference numerals.

This circuit is based on IV2. The circuit portion formed by N0R2 is replaced by a transfer gate TG1 formed by p-channel and n-channel Mo3 transistors.
, terminal T of TGl (transfer game)
1 is connected to the terminal Tc, the terminal T2 is connected to the terminal Td, and the mode switching signal input terminal TM is connected to the gate of the p-channel transistor and the gate of the n-channel I-transistor via the inverter IV7. Furthermore, transistors TRI and TR2 are provided, the transistor TRI has a drain connected to the terminal Td, a source grounded, and a gate connected to the terminal TM, and the transistor TR2 has a drain connected to the terminal Td, and a source grounded. , whose gates are connected to terminal TRST. transistor T
RI is a reset transistor for always maintaining the output signal of FF3, that is, the signal e, at "0" when M is "1", and the transistor TR2 is a reset transistor for maintaining the output signal of FF3, that is, the signal e, at "0".
This is a current transistor for initializing the signal d of FF3 with the R3T signal when rOJ is rOJ. The logical operation of this circuit is exactly the same as the circuit shown in Figure 2, and the signal M is
When the signal M is rOJ, the frequency is divided by 1/4, and when the signal M is rOJ, it is 11
Perform frequency division by 5.

A particular advantage of this circuit is that the time it takes for the signal output from FF2 to be transmitted to the input terminal Td of FF3 is short. In other words, the delay t F from FF2 after the clock input
The signal C output from F1Z to terminal Tc passes through transfer gate TGI and is delayed by t.

Since it is later transmitted to the terminal Td, the upper limit of the high operating frequency that can be operated by this circuit is determined by FF2-T.
c-N0RI-Ta or FF3-Te-N0RI-T
is the delay in the path of a.

Considering the same as the case of the circuit of FIG. 2, the maximum operating frequency f' of the prescaler of FIG. 1 is T t,,z +tNOR.

・(2) t FF: I + t HORI [Effect of the invention] As explained above, the present invention provides the 2N-th and 2N+1
The signal connection between the first and second 79717071 is made through a CMOS transfer gate whose on/off is controlled by a mode switching signal, and the source is connected to the power supply and the drain is connected to the input terminal of the 2N+1th flip-flop. Second
A mode switching signal input terminal is connected to the gate of the first MOS transistor, and a reset signal input terminal is connected to the gate of the second MOS transistor to control on/off of each MOS transistor. This eliminates the need for an inverter, which was required in the past, and eliminates the delay time for the inverter, resulting in the effect of enabling high-speed operation.

[Brief explanation of drawings]

FIG. 1(a) is a circuit diagram showing an embodiment of a CMOS prescaler according to the present invention, FIG. 1(b) is a circuit diagram showing a dual-phase signal generation circuit, and FIG. 2 (al indicates a conventional CMOS prescaler). Circuit diagram, Fig. 2 (bl is a circuit diagram showing a dual-phase signal generation circuit, Fig. 3 is a circuit diagram showing an example of a flip-flop.FFI, FF2.FF3...Flip-flop, N0
R1, N0R2...NOR circuit, IVI~IV7...
・Inverter, TGl...Transfer gate, TR
1, TR2-transistor, 7'a, Tb, Tc, Td
, Te, TR3T, TM one terminal.

Claims (1)

[Claims] 1/(2N) and 1/
In a (2N+1) frequency division CMOS prescaler, a CMO that controls ON/OFF of the signal connection between the 2Nth and 2N+1th flip-flops using a mode switching signal.
The first and second MOS transistors are connected through an S transfer gate, and have their sources connected to a power source and their drains connected to the input terminal of a 2N+1 flip-flop,
By connecting the mode switching signal input terminal to the gate of the first MOS transistor and connecting the reset signal input terminal to the gate of the second MOS transistor, each MOS
A CMOS prescaler characterized by controlling on/off of a transistor.