JPH0334310U

JPH0334310U -

Info

Publication number: JPH0334310U
Application number: JP9392389U
Authority: JP
Priority date: 1989-08-11
Filing date: 1989-08-11
Publication date: 1991-04-04

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を示す回路図、第２
図は本考案の他の実施例を示す回路図、第３図は
本考案の更に他の実施例を示す回路図、第４図、
第５図、第６図は従来の多周波数発振回路図であ
る。図中、３０……ＩＣ回路、３１，３２……発振
回路を示す。 Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is a circuit diagram showing another embodiment of the present invention, FIG. 3 is a circuit diagram showing still another embodiment of the present invention, and FIG.
FIGS. 5 and 6 are conventional multi-frequency oscillation circuit diagrams. In the figure, 30 shows an IC circuit, and 31, 32 shows an oscillation circuit.

Claims

[Scope of utility model registration request]

a plurality of logic circuit groups each having at least two or more input terminals;
Two or more crystal oscillation circuits are formed by connecting a crystal oscillator and a resistor between one input terminal and output terminal of a logic circuit forming a group, and grounding the input and output terminals with a suitable capacitor. , characterized in that a sine wave is output from an input terminal of the logic circuit, and at the same time, the first logic circuit forming the crystal oscillation circuit is formed by a logic circuit forming a second group in the logic circuit group. A multi-frequency crystal oscillation circuit, characterized in that one of the crystal oscillation circuits is configured to enter an oscillation state by controlling the logic value of the other input terminal of the logic circuit of the group.