JPH0334208B2 - - Google Patents
Info
- Publication number
- JPH0334208B2 JPH0334208B2 JP61015385A JP1538586A JPH0334208B2 JP H0334208 B2 JPH0334208 B2 JP H0334208B2 JP 61015385 A JP61015385 A JP 61015385A JP 1538586 A JP1538586 A JP 1538586A JP H0334208 B2 JPH0334208 B2 JP H0334208B2
- Authority
- JP
- Japan
- Prior art keywords
- sample
- electrode
- substrate electrode
- film
- bias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 23
- 230000005684 electric field Effects 0.000 claims description 4
- 239000010408 film Substances 0.000 description 26
- 238000005516 engineering process Methods 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 239000010453 quartz Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Description
〔産業上の利用分野〕
本発明は、プラズマ中において試料の置かれた
基板電極に高周波電界を印加して成膜あるいはエ
ツチングを行うプラズマ処理装置に関するもので
ある。
〔従来の技術〕
LSIの微細化、高密度化を実現するために、各
種のプラズマ応用技術が開発されている。膜を形
成する装置では、プラズマCVD装置、スパツタ
装置、ECR(電子サイクロトロン共鳴)装置等が
これに該当する。最近、これらの成膜を行う装置
において試料を置く基板に高周波電圧を印加し、
成膜と同時にエツチングを行うバイアス印加技術
が注目を集めている。なかでもバイアススパツタ
技術(C.Y.Ting:「Study of planarized
sputter−deposited SiO2」J.Vac.Sci.、
Technol.、15、May/June 1978、pp1105〜
1112)とバイアスECR技術(K.Machida and
H.Oikawa:「New Planarization Techology
Using Bias−ECR Plasma Deposition」
Extended Abstracts of Confarence on
SSDM、Tokyo、1985、pp329−332)が注目さ
れている。これらの方法は、半導体基板上に電極
や配線が形成された凹凸のある表面上に絶縁膜を
平坦に形成したり、配線を引き出すために絶縁膜
上に形成されたコンタクトホール内に金属等を埋
め込んだりすることを容易に行うことができる。
このため、これらの技術は、今後の超LSI製作の
最重要技術の一つになると考えられている。
第6図は従来のバイアススパツタ装置を示す概
略側断面図である。1は成膜およびエチツングを
行う成膜室であり、排気系2を介して真空ポンプ
と接続されている。3はスパツタガスを導入する
ガス導入機構であり、15はそのバルブである。
ターゲツト4と基板電極5の周囲は成膜室1と電
気的に接続されたシールド板8,9によつて囲わ
れている。成膜室1は接地されており、ターゲツ
ト4はRF整合器10およびRF電源12を介し
て、基板電極5はRF整合器11およびRF電源1
3を介してそれぞれ接地されている。本装置を動
作させるには、まず、薄膜を堆積させたい試料1
4を基板電極5上にセツトする。ついでバルブ1
5を開いてスパツタガスを成膜室1内に所定の圧
力になるように導入する。その後、RF電源12
を「オン」すれば、ターゲツト4にRF電力が印
加されてプラズマが発生し、このプラズマにより
ターゲツト4がスパツタされて試料14上に所望
の薄膜が堆積される。一方、RF電源11を「オ
ン」すれば、基板電極5にRF電力が印加されて
試料14がスパツタエツチングされる。
第7図は従来のバイアスECR装置を示す概略
側断面図である。21はRF等のバイアス電源、
22は基板電極、23はプラズマ発生室、24は
成膜室、25,26はガス導入機構、27は石英
板である。この装置では、先ず、プラズマ発生室
23にガス導入機構25から活性あるいは不活性
ガスを導入し、マイクロ波等を使つてイオンを生
成する。そしてこのイオンをマグネツトコイル2
9による磁界により成膜室24に輸送し、基板電
極22上に置かれた試料28に対して膜堆積を行
う。なお、この場合、成膜室24に設けられたガ
ス導入機構26から他のガス等を供給して膜形成
を行つてもよい。この装置の場合も、上述したバ
イアススパツタ装置の場合と同様、基板電極22
にRF電圧を印加することにより試料28をイオ
ンによりエツチングする。
〔発明が解決しようとする問題点〕
ところが、第6図に示すようなバイアススパツ
タ装置において、ターゲツト4として石英板を用
い、試料14としてSiウエハ上にA1配線を含ん
だ半導体素子を搭載したものを用いたときに、A
1配線の一部に大きな変形、ひどい場合には溶断
が生じることがあつた。また、同装置において、
ターゲツト4として同じく石英板を、また、試料
14としてSiウエハ上に膜厚200Åのゲート酸化
膜が形成されている多結晶SiゲートMOSキヤパ
シタを搭載したものを用い、ターゲツト4に
3.5KWのRF電界を印加してSiO2を1.5μm堆積し
た後、基板電極5に0.6KWのRF電界を印加して
エツチングを行つたときには、表1に示すように
ゲート面積が大きくなるにつれてゲート酸化膜が
破壊されてゲートリーク歩留まりが大幅に低下す
るという問題があつた。
[Industrial Application Field] The present invention relates to a plasma processing apparatus that performs film formation or etching by applying a high frequency electric field to a substrate electrode on which a sample is placed in plasma. [Prior Art] Various plasma application technologies have been developed to realize miniaturization and higher density of LSIs. Examples of devices that form films include plasma CVD devices, sputtering devices, and ECR (electron cyclotron resonance) devices. Recently, high-frequency voltage is applied to the substrate on which the sample is placed in these film-forming devices.
Bias application technology that performs etching at the same time as film formation is attracting attention. Among them, bias sputtering technology (CYTing: ``Study of planarized''
sputter−deposited SiO 2 ” J.Vac.Sci.,
Technol., 15, May/June 1978, pp1105~
1112) and bias ECR technology (K. Machida and
H.Oikawa: “New Planarization Technology
Using Bias−ECR Plasma Deposition”
Extended Abstracts of Conference on
SSDM, Tokyo, 1985, pp329-332) is attracting attention. These methods involve forming a flat insulating film on the uneven surface of a semiconductor substrate on which electrodes and wiring are formed, or depositing metal, etc. into contact holes formed on the insulating film to draw out the wiring. It can be easily embedded.
For this reason, these technologies are considered to be one of the most important technologies for future VLSI production. FIG. 6 is a schematic side sectional view showing a conventional bias sputtering device. Reference numeral 1 denotes a film forming chamber in which film forming and etching are performed, and is connected to a vacuum pump via an exhaust system 2. 3 is a gas introduction mechanism for introducing sputter gas, and 15 is a valve thereof.
The target 4 and the substrate electrode 5 are surrounded by shield plates 8 and 9 electrically connected to the film forming chamber 1. The film forming chamber 1 is grounded, the target 4 is connected to the RF matching box 10 and the RF power source 12, and the substrate electrode 5 is connected to the RF matching box 11 and the RF power source 1.
3 and are respectively grounded. To operate this device, first 1
4 is set on the substrate electrode 5. Then valve 1
5 is opened and sputter gas is introduced into the film forming chamber 1 to a predetermined pressure. After that, RF power supply 12
When turned on, RF power is applied to the target 4 to generate plasma, which sputters the target 4 to deposit a desired thin film on the sample 14. On the other hand, when the RF power source 11 is turned on, RF power is applied to the substrate electrode 5 and the sample 14 is sputter etched. FIG. 7 is a schematic side sectional view showing a conventional bias ECR device. 21 is a bias power supply such as RF,
22 is a substrate electrode, 23 is a plasma generation chamber, 24 is a film forming chamber, 25 and 26 are gas introduction mechanisms, and 27 is a quartz plate. In this device, first, active or inert gas is introduced into the plasma generation chamber 23 from the gas introduction mechanism 25, and ions are generated using microwaves or the like. Then, these ions are transferred to magnet coil 2.
The sample 28 is transported to the film forming chamber 24 by the magnetic field generated by the sample 9 , and a film is deposited on the sample 28 placed on the substrate electrode 22 . Note that in this case, film formation may be performed by supplying other gases or the like from the gas introduction mechanism 26 provided in the film forming chamber 24. In this device, as in the case of the bias sputter device described above, the substrate electrode 22
By applying an RF voltage to the sample 28, the sample 28 is etched by ions. [Problems to be Solved by the Invention] However, in a bias sputtering apparatus as shown in FIG. 6, a quartz plate is used as the target 4, and a semiconductor element including A1 wiring is mounted on a Si wafer as the sample 14. When using something, A
Part of one wiring was severely deformed, and in severe cases, it was blown out. In addition, in the same device,
A quartz plate was used as the target 4, and a polycrystalline Si gate MOS capacitor with a gate oxide film of 200 Å thick formed on a Si wafer was used as the sample 14.
After depositing 1.5 μm of SiO 2 by applying a 3.5 KW RF electric field, when etching was performed by applying a 0.6 KW RF electric field to the substrate electrode 5, as shown in Table 1, as the gate area became larger, the gate There was a problem that the oxide film was destroyed and the gate leakage yield decreased significantly.
本発明プラズマ処理装置は上記問題点に鑑みて
なされたものであり、基板電極と電気的に絶縁さ
れた電極を試料の外周部近傍に配置したものであ
る。
〔作用〕
異常放電によるサージ等が、試料外周部近傍に
配置された電極に吸収される。また、この電極の
存在により試料表面の局所的電位変動が抑制さ
れ、試料表面の電位が一定に保たれ、さらに、磁
力線等に起因した局所的に高いイオン、電子分布
が試料表面においてはほぼ均一になる。
〔実施例〕
以下、実施例と共に本発明を詳細に説明する。
第1図は本発明をバイアススパツタ装置に適用
した場合の一実施例を示す概略側断面図であり、
第6図のバイアススパツタ装置と同一の構成部分
には同一の符号を付して詳細な説明を省略する。
本実施例の装置では基板電極5の周囲に試料1
4を取り囲むように電極16が設けられており、
この点が第6図に示す従来装置と相違する。この
電極16は、底面中央部が開口した有底円筒形状
を為し、倒立した状態で基板電極5に覆い被さつ
ている。電極16の開口部16′は試料14より
も広く、電極16は上方から見たときに試料14
が開口16′の内側に納まるように配置されてい
る。また、電極16は絶縁子17によつて成膜室
1と電気的に絶縁されており、スイツチ18およ
び可変電圧源19を介して接地されている。本実
施例では電極16の材料としてMoが用いられて
いる。
このような構成において、ターゲツト4として
石英板を用い、試料14としてSiウエハ上にA1
配線を含んだ半導体素子を搭載したものを用いて
成膜を行つた。すなわち、第6図に示す従来装置
と同様に、まず、薄膜を堆積させたい試料14を
基板電極5上にセツトする。ついでバルブ15を
開いてスパツタガスを成膜室1内に所定の圧力に
なるように導入する。その後、RF電源12を
「オン」してRF電力をターゲツト4に印加してプ
ラズマを発生させ、ターゲツト4をスパツタして
試料14上に膜堆積を行う。このような膜堆積を
行いながら、一方においてRF電源11を「オン」
して基板電極5にRF電力を印加することにより
試料14をスパツタエツチングし、所望の膜形成
を行うのである。このとき、スイツチ18の開閉
状態に係わらずA1配線の溶断は全く見られなか
つた。すなわち、電極16を電気的に浮かせてプ
ラズマ電位とした場合も、電極16に0〜数V程
度の電圧を印加した場合も従来のようなA1配線
の溶断は全く見られなかつた。
つぎに、スイツチ18を開放した状態におい
て、試料としてSiウエハ上に膜厚100Åのゲート
酸化膜が形成されている多結晶SiゲートMOSキ
ヤパシタを搭載したものを用い、ターゲツト4に
3.5KWのRF電力を印加して、1.5μm厚のSiO2を
堆積した後、基板電極5に0.6KWのRF電力を印
加してエツチングを行つた場合のゲート歩留まり
を表2に示す。
The plasma processing apparatus of the present invention has been developed in view of the above-mentioned problems, and includes an electrode that is electrically insulated from the substrate electrode and arranged near the outer periphery of the sample. [Operation] Surges caused by abnormal discharge are absorbed by the electrodes placed near the outer periphery of the sample. In addition, the presence of this electrode suppresses local potential fluctuations on the sample surface, keeping the sample surface potential constant, and furthermore, the locally high ion and electron distribution caused by magnetic field lines is almost uniform on the sample surface. become. [Example] Hereinafter, the present invention will be described in detail with reference to Examples. FIG. 1 is a schematic side sectional view showing an embodiment of the present invention applied to a bias sputtering device.
Components that are the same as those of the bias sputtering device shown in FIG. 6 are given the same reference numerals and detailed explanations will be omitted. In the apparatus of this embodiment, a sample 1 is placed around the substrate electrode 5.
An electrode 16 is provided so as to surround 4,
This point is different from the conventional device shown in FIG. This electrode 16 has a bottomed cylindrical shape with an opening at the center of the bottom surface, and covers the substrate electrode 5 in an inverted state. The opening 16' of the electrode 16 is wider than the sample 14, and the electrode 16 is larger than the sample 14 when viewed from above.
is arranged so as to fit inside the opening 16'. Further, the electrode 16 is electrically insulated from the film forming chamber 1 by an insulator 17, and is grounded via a switch 18 and a variable voltage source 19. In this embodiment, Mo is used as the material for the electrode 16. In this configuration, a quartz plate is used as the target 4, and A1 is placed on the Si wafer as the sample 14.
Film formation was performed using a device equipped with a semiconductor element including wiring. That is, as in the conventional apparatus shown in FIG. 6, first, a sample 14 on which a thin film is to be deposited is set on the substrate electrode 5. Then, the valve 15 is opened to introduce sputter gas into the film forming chamber 1 to a predetermined pressure. Thereafter, the RF power source 12 is turned on, RF power is applied to the target 4 to generate plasma, and the target 4 is sputtered to deposit a film on the sample 14. While performing such film deposition, on the other hand, the RF power supply 11 is turned on.
By applying RF power to the substrate electrode 5, the sample 14 is sputter etched to form a desired film. At this time, no melting of the A1 wiring was observed regardless of whether the switch 18 was open or closed. That is, neither when the electrode 16 was electrically floated to a plasma potential nor when a voltage of about 0 to several volts was applied to the electrode 16, the A1 wiring was not fused as in the conventional case. Next, with the switch 18 open, a polycrystalline Si gate MOS capacitor with a gate oxide film of 100 Å thick formed on a Si wafer is used as a sample, and a sample is placed on the target 4.
Table 2 shows the gate yield when RF power of 3.5 KW was applied to deposit SiO 2 to a thickness of 1.5 μm, and then etching was performed by applying RF power of 0.6 KW to the substrate electrode 5.
以上説明したように本発明のプラズマ処理装置
によれば、試料外周部近傍に配置された電極に異
常放電によるサージ等が吸収され、また、この電
極の存在により試料表面の局所的電位変動が抑制
されて試料表面の電位が一定に保たれ、さらに、
磁力線等に起因した局所的に高いイオン、電子分
布は試料表面においてはほぼ均一化する。そのた
め、試料の置かれた基板電極への印加電力に係わ
らず、試料に発生するダメージを大幅に低減する
ことができる。その結果、ダメージによる歩留ま
りの悪さが問題となつていたバイアススパツタ技
術やバイアスECR技術を実用段階に引き上げる
ことができる。また、これらのバイアス印加技術
は膜堆積とエツチングを同時に行うため相対的膜
堆積速度が小さくなり、スループツトが低下する
というもう一つの実用上の大きな問題があつた
が、本発明により大きな電力を印加することが可
能となりスループツトの点でも大幅に改善するこ
とができる。
As explained above, according to the plasma processing apparatus of the present invention, surges caused by abnormal discharge are absorbed by the electrode placed near the outer periphery of the sample, and local potential fluctuations on the sample surface are suppressed by the presence of this electrode. The potential on the sample surface is kept constant, and
The locally high distribution of ions and electrons caused by lines of magnetic force becomes almost uniform on the sample surface. Therefore, regardless of the power applied to the substrate electrode on which the sample is placed, damage to the sample can be significantly reduced. As a result, bias sputtering technology and bias ECR technology, which had problems with poor yields due to damage, can be brought to a practical stage. In addition, these bias application techniques perform film deposition and etching at the same time, resulting in a low relative film deposition rate and a reduction in throughput, which is another major practical problem. This makes it possible to significantly improve throughput.
第1図は本発明をバイアススパツタ装置に適用
した場合の一実施例を示す概略側断面図、第2図
は本発明をバイアスECR装置に適用した場合の
一実施例を示す概略側断面図、第3図は基板電極
22に印加したRF電力とゲートリーク歩留まり
の関係を示すグラフ、第4図および第5図は電極
30または16の一例を示す平面図、第6図は従
来のバイアススパツタ装置を示す概略側断面図、
第7図は従来のバイアスECR装置を示す概略側
断面図である。
5,22……基板電極、13,21……RF電
源、14,28……試料、16,30……電極。
FIG. 1 is a schematic side sectional view showing an embodiment in which the present invention is applied to a bias sputtering device, and FIG. 2 is a schematic side sectional view showing an embodiment in which the present invention is applied to a bias ECR device. , FIG. 3 is a graph showing the relationship between the RF power applied to the substrate electrode 22 and the gate leakage yield, FIGS. 4 and 5 are plan views showing an example of the electrode 30 or 16, and FIG. 6 is a graph showing a conventional bias spacing. a schematic side sectional view showing the ivy device;
FIG. 7 is a schematic side sectional view showing a conventional bias ECR device. 5, 22... Substrate electrode, 13, 21... RF power supply, 14, 28... Sample, 16, 30... Electrode.
Claims (1)
印加し該基板電極上に置かれた試料の成膜あるい
はエツチングを行うプラズマ処理装置において、
前記基板電極と電気的に絶縁された電極を前記試
料の外周部近傍に配置したことを特徴とするプラ
ズマ処理装置。1. In a plasma processing apparatus that applies a high frequency electric field to a substrate electrode in plasma and forms a film or etches a sample placed on the substrate electrode,
A plasma processing apparatus characterized in that an electrode electrically insulated from the substrate electrode is arranged near the outer periphery of the sample.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1538586A JPS62173723A (en) | 1986-01-27 | 1986-01-27 | Plasma treater |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1538586A JPS62173723A (en) | 1986-01-27 | 1986-01-27 | Plasma treater |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62173723A JPS62173723A (en) | 1987-07-30 |
JPH0334208B2 true JPH0334208B2 (en) | 1991-05-21 |
Family
ID=11887277
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1538586A Granted JPS62173723A (en) | 1986-01-27 | 1986-01-27 | Plasma treater |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62173723A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3247491B2 (en) * | 1993-05-19 | 2002-01-15 | 東京エレクトロン株式会社 | Plasma processing equipment |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57150943U (en) * | 1981-03-18 | 1982-09-22 |
-
1986
- 1986-01-27 JP JP1538586A patent/JPS62173723A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS62173723A (en) | 1987-07-30 |
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