JPH0334197A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a switching noise at an output buffer circuit by forming the output buffer circuit by arranging two-divided MOSFETs between an output terminal and power supply and between the output terminal and grounding respectively. CONSTITUTION:A first and a second MOSFETs 1,2 are installed between the output terminal and the power supply Vcc, and are driven by AND gates 5,6 respectively. Besides, a third and a fourth MOSFETs 3,4 are installed between the output terminal and the grounding, and are driven by NOR gates 7,8 respectively. At time T after the change of an address signal at the time of usual read-out, the MOSFETs 6,8 become non-conductive always, and the MOSFET 1 becomes conductive, and the MOSFET 3 becomes non-conductive. When an internal data signal is 'L', the MOSFET 1 becomes non-condutive, and the MOSFET 3 becomes conductive. Accordingly, since the operation of a circuit by invalid data at time T is limited by the MOSFETs 1,3, the generation of the noise is reduced by half.

Description

[Detailed description of the invention]

(*Field of industrial application) This invention relates to an output buffer circuit for a semiconductor integrated circuit and a T device. [Prior art] Fig. 4 is a circuit diagram of an output buffer circuit for a conventional semiconductor integrated circuit device. , In the figure, (1) is the output terminal and the voltage !+1
P channel/I/MOSFE connected to 1 (Vcc)
T, (3) is an N-channel MO8FET connected between the output terminal and ground (GND), (5) is a P-channel MO
NAND game that drives 8FET11)), +7)
is a NOR gate that drives the N-channel MO8FET 13). Next, the operation will be explained using an EPROM. For normal reading of EFROM, Vcc = 5V and the output control signals oe and oe double signals are 'H' and 'H', respectively.
When the internal data signal is low, the output of the NAND gate (5) becomes 4L#, and the output of the NOR gate (7) also becomes 4L#, so the P-channel MO8FET11) becomes conductive and the N-channel MO8FET13) becomes non-conductive and sand appears at the output terminal. Also, when the internal data signal is 41L#, the output of the NAND gate (5) becomes city,
Since the output of the NOR gate (7) also becomes 1W, the P-channel MO8FET 11) becomes non-conductive, and the N-channel MO8FET 11) becomes non-conductive.
3FET+31 becomes conductive and %L# appears at the output terminal. When the output control signals oe and oe are respectively 4L#♂W, the internal data signal is 'H#,
In either 'L', the output of the NAND gate (5) is 'Uta'
, the output of NOR gate (7) is 4L#, so P channel MO8FET II) and N channel MO8FET1
31 are both non-conductive, and the output terminal is in a floating state, that is, a high impedance state. The EPROM has 8 or 16 of the above-mentioned output buffer circuits, and all output buffer circuits must operate stably and at high speed during normal Vcc=5V operation. Also, the internal data signal is a signal of 'L' and 'F(' determined by the sense amplifier, but invalid data is output during the period until the sense amplifier senses and outputs the correct data when the address changes. This became a noise source in the output puff 71 circuit.Since the sense amplifier is configured to detect minute fluctuations in potential in order to achieve high-speed operation, there is a risk of malfunction due to noise. Moreover, since the output buffer circuit has to drive another device with the output signal, the transistor size becomes large, and this causes large switching noise due to the output charging/discharging current, contribution current, etc. when the output buffer circuit is operating. [Problems to be Solved by the Invention] Since the output buffer circuit of a conventional EPROM is configured as described above, invalid data is output during the period after an address change until correct data is sensed, and this is output to the output buffer. This has the problem of causing switching noise in the circuit, interfering with the stable operation of the sense amplifier, and generally delaying the access time.This invention was made to solve the above problems. , reduces switching noise in the output buffer 4-way after address change, and provides stable operation.
The purpose is to obtain an output buffer circuit for PROM. [Means for Solving the Problems] The output buffer circuit of the EP ROM according to the present invention divides the MOSFET between the output terminal and the power supply into two to form a first and second MOSFET, and divides the MOSFET between the output terminal and the ground into two.
T is also divided by 2 to make the third and fourth MOSFETs, and during the sense amplifier operation period after the address change, only one of the divided MOSFETs is operated, and after data judgment by the sense amplifier, both of the divided 5 MOSFETs are operated. It is designed to operate a MOSFET.

[Effect]

The output buffer circuit according to the present invention reduces the capacity by adjusting the size of the output buffer during the sense amplifier operation period after an address change, thereby reducing switching noise in the output buffer. [Embodiment 1] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, 11) and (2) are the output terminal and the power supply (Vc
c) first and second MOSFETs connected between +3
: and +4) are the third and fourth MOSFETs connected between the output terminal and ground (GND), 15) and 16) are the N MOSFETs that drive MO8FETs 11) and (2), respectively.
AND gate, 17) and +81 are each MO3F
This is the output of the NOR gate that connects ET131 and ET143. FIG. 2 is a circuit diagram showing an embodiment of the ATDT path and address buffer section in FIG.
Ai is an external address signal, ce is a chip enable signal, at, ai are internal address signals, the ATDT path uses the internal address signal at as an input signal, atd, atd
is used as the output signal. Next, the operation will be explained. The ATDT path shown in FIG. 2 outputs atd and atd signals as shown in FIG. 3 in response to input of an external address signal Ai. That is, after the external address signal Ai changes at
The d signal outputs the signal for the time tvUT, and the atd signal outputs 1L# for the time T. Here, time T is the operating period of the sense amplifier. From the above, in Figure 1, during normal readout, that is, o
When the e and oe double signals are ')F and 'L', respectively,
Is the llj atd signal at time T after the change in the 71' response signal M? , atd signal is 1L#, so the output of the NAND gate (6) is 10 whether the internal data signal is low or low, and the second MOSFET is always non-conductive. (8) is the internal data signal
In either 'H' or 'L', the output becomes wL, #, and the fourth MOSFET is always non-conducting.On the other hand, at
d, NAND gate to which atd signal is not input (
5), the NOR gates (7) each output '''L#, the first MOSFET III is conductive, and the third MOSFET
FET (3) becomes non-conductive 4, and when the internal data signal is 4L', NAND gate (5) and NOR gate (
7) outputs ■′ respectively, @1 MOSFET II
) is non-conductive, and the third MOSFET (3) is conductive. Therefore, during the time T, the operation of the output buffer circuit based on the output data is performed only in the first and third MOSFETs, and therefore, the generation of switching noise in the output buffer circuit is different from that in the conventional case. Also, after 1 hour T, the atd signal becomes 'L' and the atd signal becomes jF, so the NAND gate +6) outputs the same signal as the NAND gate (5), and the NOR gate (8) outputs the same signal as the NAND gate (5).
Outputs the same signal as OR gate (7). That is, when the internal data signal is ")P", the first and second MOSFs
Both ETIII and t2+ become conductive, and both the third and fourth MOSFETs 13) and +41 become non-conductive, and ■t appears at the output terminal. Internal data signal is 4
When L#, the first and second MOSFET III, 1
21 are both non-conducting 1 hero, 3rd and 4th Mo5pE
Tt3+. 14) are both conductive, and 4L appears at the output terminal. As mentioned above, when the sense amplifier is open/open, +4 T
During this period, the MOSFET is only active, so the switching noise caused by the output buffer circuit can be reduced.
The operation of the sense amplifier is stabilized and delays in access time can be prevented. In the above embodiment, the case of switching noise of an output buffer circuit of an EDROM has been described, but the present invention has similar effects in a conductive musical instrument circuit device. [Effects of the Invention] As described above, according to the present invention, switching noise in the output buffer circuit can be reduced because the capacity of the output buffer circuit is used during the sense amplifier operation period after an address change. This has the effect of providing an EDROM capable of stable read operations.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention.A conductive musical instrument circuit f!
A circuit diagram of the output buffer circuit of the helmet, Figure 2 is a circuit block diagram that generates the ATDT signal in Figure 1, and Figure 3 is a circuit diagram of the circuit that generates the ATDT signal in Figure 1.
The external address signal and atd in the figure. A waveform diagram of the atd signal and data output. FIG. 4 is a circuit diagram of an output buffer circuit of a conventional semiconductor integrated circuit device. In the figure, (1) is the first MOSFET, (2) is the second MOSFET, and (13) is the third (7) MOSFET.
ET, 14) is the fourth MOSFET, +5) and 16)
is a NAND gate) +71 and (8) are a NOR gate. In addition, in the figures, the same reference numerals are the same, and X indicates corresponding parts.

Claims (1)

[Claims] A first output buffer has an ATD circuit that detects a change in address input and generates a pulse for a predetermined time, and is made up of first and second MOSFETs connected between an output terminal and a power supply; the third and fourth M connected between
In the second output buffer made of an OSFET, the ATD circuit outputs a control signal for the data judgment time in the sense amplifier after detecting an address transition (change), invalidates (inactivates) the second output buffer, and After outputting the signal, enable (activate) the first and second output buffers.
A semiconductor integrated circuit device characterized by: