JPH0334117U - - Google Patents
Info
- Publication number
- JPH0334117U JPH0334117U JP9465389U JP9465389U JPH0334117U JP H0334117 U JPH0334117 U JP H0334117U JP 9465389 U JP9465389 U JP 9465389U JP 9465389 U JP9465389 U JP 9465389U JP H0334117 U JPH0334117 U JP H0334117U
- Authority
- JP
- Japan
- Prior art keywords
- rectifier circuit
- circuit
- capacitor
- diode
- disconnecting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 238000004804 winding Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Dc-Dc Converters (AREA)
- Rectifiers (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Description
第１図は本考案の実施例の回路図、第２図は従
来のチヨーク・インプツト整流用ＦＥＴドロツパ
・バイアス回路を示す回路図である。
１……電源、２……電源スイツチ、３，１１，
１２，１３……コンデンサ、４，１０……ＦＥＴ
、５……トランス、６〜８……ダイオード、９…
…コイル、１４……寄生容量、１５〜１９……抵
抗器、２０……シヤントレギユレーター、２１…
…負荷。
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional choke input rectifier FET dropper bias circuit. 1...Power supply, 2...Power switch, 3,11,
12, 13... Capacitor, 4, 10... FET
, 5...Transformer, 6-8...Diode, 9...
... Coil, 14 ... Parasitic capacitance, 15-19 ... Resistor, 20 ... Shunt regulator, 21 ...
…load.
Claims (1)
ツチング回路を接続してあるトランスの２次側巻
線に、ダイオード及びコンデンサを直列接続した
第１の整流回路と、ダイオード及びチヨーク・イ
ンプツト回路を縦続接続した第２の整流回路と、
ゲートに前記第１の整流回路の出力電圧を抵抗器
を介して接続されているとともに負荷出力電圧に
応答して出力制御回路が発生する制御電圧を与え
られているドロツパ用ＦＥＴのソース及びドレイ
ン間とを、順次に縦続接続した構成を有し、且つ
前記第１の整流回路の前記コンデンサに放電用抵
抗器を並列接続してあることを特徴とするチヨー
ク・インプツト整流用ＦＥＴドロツパー・バイア
ス回路。 A first rectifier circuit in which a diode and a capacitor are connected in series to the secondary winding of a transformer whose primary winding is connected to a switching circuit having a switch for disconnecting and disconnecting the power, and a diode and input circuit. a second rectifier circuit connected in cascade;
Between the source and drain of a dropper FET, the gate of which is connected to the output voltage of the first rectifier circuit via a resistor, and which is supplied with a control voltage generated by an output control circuit in response to a load output voltage. and a discharge resistor is connected in parallel to the capacitor of the first rectifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9465389U JPH0334117U (en) | 1989-08-10 | 1989-08-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9465389U JPH0334117U (en) | 1989-08-10 | 1989-08-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0334117U true JPH0334117U (en) | 1991-04-03 |
Family
ID=31643972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9465389U Pending JPH0334117U (en) | 1989-08-10 | 1989-08-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0334117U (en) |
-
1989
- 1989-08-10 JP JP9465389U patent/JPH0334117U/ja active Pending
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