JPH0332805B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a reset control circuit for a microprocessor that switches between two systems of oscillation clocks.

BACKGROUND ART Conventionally, in a microprocessor, a reset is applied before the power supply voltage becomes a constant voltage to prevent program progress from malfunctioning when the power supply voltage becomes lower than the constant voltage.
For this purpose, a constant voltage detection circuit is connected to the reset terminal to set the lower limit voltage for operation (for example, Japanese Patent Application Laid-Open No. 55-53717).

On the other hand, in conventional microprocessors,
A high-speed clock and a low-speed clock switching device is provided. For example, during standby, the high-speed clock used in normal use is switched to a low-speed clock to reduce power consumption, and during normal use, the high-speed clock is switched back to the previous high-speed clock. (for example, Japanese Patent Laid-Open No. 59-5328).

Problems to be Solved by the Invention Even in a processor that switches between two systems of clocks, such as the conventional example described above, there is only one reset terminal, and only one lower limit voltage value for operation can be set.

In such a configuration, even if the lower operating voltage limits that can be tolerated when using a fast clock and the lower operating voltage limits that can be tolerated when using a slower clock are different, the lower operating voltage limit that can be tolerated by one or the other (often , the problem is that it is only possible to set the operating lower limit voltage that is allowable for high-speed clocks.

SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a reset control device that has a simple configuration and can set the lower limit power supply voltage for high-speed clock operation and the lower limit power supply voltage for low-speed clock operation.

Means for Solving the Problems The present invention provides a clock switching device that outputs a clock switching signal indicating the use status of a high-speed clock and a low-speed clock, and a first clock switching device that is effective only when the high-speed clock is used by controlling the clock switching signal. A reset terminal is provided, and a second reset terminal is enabled regardless of the clock used. The first reset terminal is connected to an operating lower limit voltage detection circuit during high-speed operation, and the second reset terminal is connected to a lower limit voltage detection circuit during low-speed operation. This is a reset control device characterized in that a lower operating limit voltage detection circuit is connected to the reset control device.

Effects of the present invention With the above configuration, if the operating lower limit voltage during high-speed operation is higher than the operating lower limit voltage during low-speed operation, when the power supply voltage becomes lower than the lower limit voltage during high-speed operation, the high-speed clock is used. The operating lower limit voltage detection circuit applies a reset signal to the first reset terminal to reset the processor, but when a low-speed clock is used, the first reset terminal is disabled under the control of the clock switching signal and the processor is not reset. . Furthermore, when the low speed clock is used, when the power supply voltage becomes lower than the lower limit voltage for low speed operation, the lower limit voltage detection circuit for low speed operation applies a reset signal to the second reset terminal, and the processor is reset.

Embodiment FIG. 1 shows a block diagram of an embodiment of the microprocessor reset control circuit of the present invention.

In FIG. 1, 1 is a reset terminal A, 2 is a reset terminal B, 3 is a NOT gate that inverts the output of the reset terminal A1, 4 is a clock switching control section that outputs a high-speed clock or low-speed clock switching signal C, and 5 inputs the input signal of the reset terminal B2 and the output c of the clock switching control section 4.
NOR gate, 6 is a NOR gate whose inputs are the output of the above NOT gate 3 and the output of the above NOR gate 5, 7 is the reset input of the output of the above NOR gate 6, and when the input d is "L", the reset sequence of the processor is executed. 8 is a 3.5V detection circuit whose output is connected to the reset terminal A1, and 9 is a 4.5V detection circuit whose output is connected to the reset terminal B2. The power supply voltage shall normally be used at 5.0V.

The operation of the reset circuit of this embodiment constructed as described above will be explained below.

The clock switching control section 4 generates a switching signal C between a high speed clock and a low speed clock.The clock switching signal C becomes "L" when the high speed clock is used.
Becomes "H" when low speed clock is used. Therefore, when a high-speed clock is used, that is, when the clock switching signal is "L", when the reset terminal B2 becomes "L",
The output of NOR gate 5 becomes “H”, so
Since the output of the NOR gate 6 becomes "L", the processor is reset by the reset sequence generating section 7. However, when a low-speed clock is used, the clock switching signal C becomes "H", so even if the reset terminal B2 becomes "L", the processor is not reset.

On the other hand, when reset terminal A1 becomes "L",
The output of NOT gate 3 becomes “H”, so
Since the output of NOR gate 6 becomes "L", the processor is reset regardless of the clock used.

The 3.5V detection circuit 8 outputs "L" when the power supply voltage is less than 3.5V, and outputs "H" when the power supply voltage is 3.5V or more.
Output. In addition, the 4.5V detection circuit 9 outputs "L" when the power supply voltage becomes less than 4.5V,
Outputs “H” when the voltage is 4.5V or higher.

It is assumed that when the processor is reset, the high-speed clock is selected.

FIG. 2 shows a timing chart for changes in power supply voltage when a high speed clock is used.

In the figure, a shows the state of the reset terminal A1, b shows the state of the reset terminal B, c shows the clock switching signal output from the clock switching control section 4, and d shows the state of the input to the reset sequence generating section 7.

When the power supply voltage is lower than 4.5V, the input b of the reset terminal B2 is "L", and when the high-speed clock is used, the clock switching signal C is "L", so the processor is reset and the power supply voltage becomes 4.5V or higher. If so, the reset is released and high-speed operation is performed. In other words, during high-speed clock oscillation, the power supply voltage
It is reset when it becomes less than 4.5V.

FIG. 3 shows a timing chart for changes in power supply voltage when switching to a low speed clock.

The signal names in the figure are the same as in FIG. 2.

During a power-on reset, the high speed clock is selected so that the processor is in a reset sequence when the supply voltage is less than 4.5V. When the power supply voltage exceeds 4.5V, both reset signals a and b become "H", so that high-speed clock operation is performed. Next, when the clock is switched and a low-speed clock is used by a command, the clock switching signal C becomes "H" and the state of the reset terminal B2 becomes invalid with respect to the reset. Therefore, at this time, the reset is performed depending on the state of the reset terminal A1. That is, if a slow clock is used, a reset is performed when the power supply voltage falls below 3.5V.

As described above, according to this embodiment, there are provided the reset terminal B2, which is valid only when the clock switching signal is "L", that is, when the high-speed clock is in use, and the reset terminal A1, which is valid regardless of the clock being used.
Connect a 4.5V detection circuit to reset terminal B2,
By connecting a 3.5V detection circuit to reset terminal A1, the power supply voltage can be reduced when using a high-speed clock.
When the power supply voltage becomes less than 4.5V, it is reset to ensure a reset in the event of a power failure during high-speed operation.When using a low-speed clock, that is, in power save mode, it is reset when the power supply voltage becomes less than 3.5V to ensure low-speed operation. Sometimes it is possible to provide a margin for power supply fluctuations.

In addition, in this example, the lower limit voltage for operation when the system clock is set to a high speed clock is 4.5V, and the lower limit voltage for operation when set to a low speed clock is set to 3.5V, but these voltages are not limited to these values. It is not necessary to set the value according to the situation of the system.

Effects of the Invention As described above, according to the present invention, the lower limit power supply voltage when using a high-speed clock and the lower limit power supply voltage when using a low-speed clock can be set with an extremely simple circuit configuration. The practical effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a reset control device according to an embodiment of the present invention, FIG. 2 is an operational waveform diagram for changes in power supply voltage when using a high-speed clock of the same embodiment, and FIG. 3 is a diagram of a high-speed clock of the same embodiment. FIG. 4 is an operation waveform diagram for changes in power supply voltage when switching from a low-speed clock to a low-speed clock. 1...Reset terminal A, 2...Reset terminal B, 4...Clock switching control section.

Claims (1)

[Claims] 1. A clock switching circuit that outputs a clock switching signal that indicates the use status of the high-speed clock and low-speed clock, and a first reset terminal that is enabled only when the high-speed clock is used under the control of the clock switching signal mentioned above, and is effective regardless of the clock used. 1. A reset control circuit comprising a second reset terminal.