JPH0332426U - - Google Patents
Info
- Publication number
- JPH0332426U JPH0332426U JP1989091422U JP9142289U JPH0332426U JP H0332426 U JPH0332426 U JP H0332426U JP 1989091422 U JP1989091422 U JP 1989091422U JP 9142289 U JP9142289 U JP 9142289U JP H0332426 U JPH0332426 U JP H0332426U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- tape carrier
- substrate
- mounting structure
- inner lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Landscapes
- Wire Bonding (AREA)
Description
第１図本考案のチツプ実装構造を示す側面図、
第２図ａ，ｂはテープキヤリヤチツプの製造工程
を示す図、第３図ａ，ｂは従来例を示す側面図で
ある。 図において、１……テープキヤリヤチツプ、２
……インナーリード、２ａ……屈曲部、３……チ
ツプ、４……基板である。
第２図ａ，ｂはテープキヤリヤチツプの製造工程
を示す図、第３図ａ，ｂは従来例を示す側面図で
ある。 図において、１……テープキヤリヤチツプ、２
……インナーリード、２ａ……屈曲部、３……チ
ツプ、４……基板である。
Claims (1)
- 【実用新案登録請求の範囲】 屈曲して形成したインナーリード２にチツプ３
をボンデイングして成るテープキヤリヤチツプ１
を有し、 該テープキヤリヤ１を基板４上にフエイスアツ
プで実装したことを特徴とするチツプ実装構造。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989091422U JPH0332426U (ja) | 1989-08-04 | 1989-08-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989091422U JPH0332426U (ja) | 1989-08-04 | 1989-08-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0332426U true JPH0332426U (ja) | 1991-03-29 |
Family
ID=31640906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989091422U Pending JPH0332426U (ja) | 1989-08-04 | 1989-08-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332426U (ja) |
-
1989
- 1989-08-04 JP JP1989091422U patent/JPH0332426U/ja active Pending