JPH0332403U - - Google Patents
Info
- Publication number
- JPH0332403U JPH0332403U JP9235889U JP9235889U JPH0332403U JP H0332403 U JPH0332403 U JP H0332403U JP 9235889 U JP9235889 U JP 9235889U JP 9235889 U JP9235889 U JP 9235889U JP H0332403 U JPH0332403 U JP H0332403U
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- chip
- network
- opposing edge
- terminal electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims description 4
- 238000009966 trimming Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Description
第１図は本考案の実施例に係るチツプＲネツト
ワークの平面図、第２図は本考案の他の実施例の
チツプＲネツトワークの平面図、第３図は従来例
のチツプＲネツトワークの平面図、第４図は第３
図のＡ−Ａ′線に沿う断面図、第５図および第６
図はチツプＲネツトワークの製造工程の説明に供
する図である。
１……チツプＲネツトワーク、２……絶縁基板
、３ａ〜３ｄ，４ａ〜４ｄ……端子電極、５ａ〜
５ｄ……抵抗膜、６ａ〜６ｄ……トリミング溝、
７，８……凹溝、９……保護膜。
Fig. 1 is a plan view of a Chip R network according to an embodiment of the present invention, Fig. 2 is a plan view of a Chip R network of another embodiment of the present invention, and Fig. 3 is a plan view of a Chip R network of a conventional example. The plan view of Fig. 4 is the 3rd
Cross-sectional views taken along line A-A' in the figure, Figures 5 and 6.
The figure is a diagram used to explain the manufacturing process of the Chip R network. 1...Chip R network, 2...Insulating substrate, 3a-3d, 4a-4d...Terminal electrode, 5a-
5d...Resistive film, 6a-6d...Trimming groove,
7, 8...concave groove, 9...protective film.
Claims (1)
れ複数箇の端子電極が形成され、これらの端子電
極に接続されるとともに絶縁基板の他方の対向す
る端縁に沿う方向に複数箇の抵抗膜が形成され、
これらの抵抗膜にはそれぞれトリミング溝が形成
されてなるチツプＲネツトワークにおいて、 絶縁基板の他方の対向する端縁側に位置してい
る抵抗膜のトリミング溝をその端縁側とは反対側
の位置に形成したことを特徴とするチツプＲネツ
トワーク。[Claims for Utility Model Registration] A plurality of terminal electrodes are formed on one opposing edge of a rectangular insulating substrate, and connected to these terminal electrodes, and along the other opposing edge of the insulating substrate. Multiple resistive films are formed in the direction,
In a chip R network in which trimming grooves are formed in each of these resistive films, the trimming groove of the resistive film located on the other opposing edge side of the insulating substrate is placed at a position opposite to that edge side. The Chip R network is characterized by the fact that it has been formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9235889U JPH0332403U (en) | 1989-08-04 | 1989-08-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9235889U JPH0332403U (en) | 1989-08-04 | 1989-08-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0332403U true JPH0332403U (en) | 1991-03-29 |
Family
ID=31641793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9235889U Pending JPH0332403U (en) | 1989-08-04 | 1989-08-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0332403U (en) |
-
1989
- 1989-08-04 JP JP9235889U patent/JPH0332403U/ja active Pending
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