JPH0332284A - Signal processing method for solid-state image pickup device - Google Patents

Signal processing method for solid-state image pickup device

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Publication number
JPH0332284A
JPH0332284A JP1167595A JP16759589A JPH0332284A JP H0332284 A JPH0332284 A JP H0332284A JP 1167595 A JP1167595 A JP 1167595A JP 16759589 A JP16759589 A JP 16759589A JP H0332284 A JPH0332284 A JP H0332284A
Authority
JP
Japan
Prior art keywords
signal
section
voltage
solid
control gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1167595A
Other languages
Japanese (ja)
Inventor
Noriyasu Oonishi
徳靖 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1167595A priority Critical patent/JPH0332284A/en
Publication of JPH0332284A publication Critical patent/JPH0332284A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To use a solid-state image pickup device to a place, where the quantity of incident light is small, by separately reading an output voltage, for which a dark time output is superimposed to a signal voltage, and the dark time output of an electric charge accumulating part and subtracting the latter from the former in the internal part of a microcomputer. CONSTITUTION:A first control gate 6 is provided to transfer a signal charge to electric charge accumulating parts 5a-5n and a second control gate 10 is provided to directly discharge the signal charge to electric charge exhaustion drain parts 9a-9n in each photosensitive picture element of a solid-state image pickup device 1. In the first signal reading, a voltage more than a threshold voltage is applied to the first control gate 6 and the gate 6 is set in a conductive state. Then, the signal voltage and dark time output are read. In the second signal reading, the voltage more than the threshold voltage is applied to the second control gate 10 and the gate 10 is set in the conductive state. Then, the dark time output voltages of the electric charge accumulating parts 5a-5n are read. Thus, an object with illuminance lower than the conventional illuminance can be picked up on the solid-state image pickup device 1.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は固体撮像装置を用いたすべCの装置首、−1
えばカメうの自動焦点装置の固体撮像装置の信号処理方
法K関するものである。
[Detailed Description of the Invention] [Industrial Application Field] This invention is a system for all C devices using a solid-state imaging device, -1
For example, it relates to a signal processing method K for a solid-state imaging device of an automatic focusing device.

〔従来の技術〕[Conventional technology]

第5図は従来のたとえはカメラの自動焦点装置の固体撮
(象装置の概略と信号処理部と演俸処+11j Al1
の塵続を示す説明図で、図において、(1)は固体%1
象装置、(2)は固体撮1象渇Rt1)の出力を人力と
する信号処理部、(3)は信号処理部(2)の1b力を
入力とする演算処理部であり、固体撮11!装置(1)
は次のように構成される。(4a)〜(4n)は入射光
酸に応じた光電荷を発生する基板上に配列された複数の
画素、(5a)〜(5n)は画素(4a)〜(4n)で
発生rる信号電荷を蓄積する電荷蓄積部、(6)は画素
(4a)〜(4n)の複数の画素の信号電荷を対応する
電荷蓄積部(5a)〜(5n)に流入するのを制御する
制御ゲート、(7a)〜(7n)は電荷蓄積部(5a)
〜(5n)の信号電荷を排出する電荷排出ドレイン部、
(8a)〜(8n)は電荷蓄積部〔5a)〜(5n)の
信号電荷を対応する電荷排出ドレイン部(7a)〜(7
n)に流入するのを制御する電荷排出用ゲート、 ti
llは電荷蓄積部(5a)〜(5n)で一定期間蓄積さ
れた信号電荷を転送する転送部、(1zは電荷蓄積部(
5a)〜(5n)の信号電荷を転送部[111に流入す
るのを制御するトランスファーゲート、(横は転送部(
11)より転送されてくる信号電荷を電圧信号に変換す
る出力部である。信号処理部(2)は固体撮慮装縛(1
)の出力を入力とし、(伸は出力信号の無信号時直流電
巴をある直流電圧哨にするクランプ回路、(囚はサンプ
ルホールド回路、(10はA/D変換回路である。演算
処理部(3)は、信号処理部(2)の出力を入力とし、
(1つはマイコン部、(1印は記憶部である。第6図は
n型仄板内のP型拡散層内に形成された第5図のVl−
W線における断面図を示r0次に動作について説明する
Figure 5 is an example of a conventional solid-state camera autofocus device (outline of the device, signal processing unit, and operations department +11j Al1).
This is an explanatory diagram showing the dust sequence of
(2) is a signal processing unit that uses the output of the solid-state camera 1 (Rt1) as human power; (3) is an arithmetic processing unit that receives the 1b power of the signal processing unit (2) as input; ! Device (1)
is constructed as follows. (4a) to (4n) are a plurality of pixels arranged on a substrate that generate photocharges according to incident photoacid, and (5a) to (5n) are signals generated by pixels (4a) to (4n). A charge storage unit that stores charges; (6) a control gate that controls the signal charges of a plurality of pixels (4a) to (4n) to flow into the corresponding charge storage units (5a) to (5n); (7a) to (7n) are charge storage parts (5a)
a charge discharge drain section for discharging signal charges of ~(5n);
(8a) to (8n) are charge discharge drain parts (7a) to (7
n) a gate for discharging charges to control the inflow into ti;
ll is a transfer unit that transfers signal charges accumulated for a certain period in charge accumulation units (5a) to (5n), (1z is a charge accumulation unit (
Transfer gates that control the flow of signal charges 5a) to (5n) into the transfer section [111;
11) This is an output unit that converts the signal charge transferred from the output unit into a voltage signal. The signal processing section (2) has a solid-state camera mounting (1
) is input, (input is a clamp circuit that sets the DC voltage to a certain DC voltage when there is no signal of the output signal, (10 is a sample and hold circuit, (10 is an A/D conversion circuit, and (10 is an A/D conversion circuit. 3) takes the output of the signal processing unit (2) as input,
(One is the microcomputer part, (1 mark is the memory part. Figure 6 shows the Vl-
A cross-sectional view taken along the W line is shown below, and the operation will be described next.

感光画素(4a)〜(4n)で発生した信号電荷は各画
素に対応する電荷蓄積部(5a)〜(5n)に蓄積され
る。
Signal charges generated in the photosensitive pixels (4a) to (4n) are accumulated in charge storage sections (5a) to (5n) corresponding to each pixel.

制御ゲート(6)にはしきい端電圧以上の直流醜圧が加
えられる。電荷蓄積部(5a)〜(5n)”K蓄積され
る電荷蓄積部は第7図に示すタイミングチャートの蓄積
時間Tintと入射光酸と暗電流で決まる。入射光酸が
多いときには蓄積時間Tintを短かくし、入射光酸が
少ないときには蓄積時間Ti ntを長くし入射光酸に
対して広いダイナミックレンジをt%るように、モニタ
ー手段(第5図には示していない)を用いて蓄積時間T
intを稠整しCいる。タイミング上4で電荷蓄積g(
5a)〜(5n)に蓄積されていた信号電荷の転送部(
11)への流入が完rし、期間tliで各電荷蓄積部(
5a)〜(5n)に蓄積されていたイ言号電曲の転送が
開始される。転送される信号電荷は転送部tll)の最
終に設けられている出力部(131で電圧信号に変換さ
れ、各電荷蓄積部(5a)〜(5n)に蓄積されていた
信号電荷を順次、対応する信号電圧に変換する(以下、
出力部X13)の1b力電圧を時系列出力電圧と呼ぶ)
。この時系列出力電圧は信号処理部(2)でクランプ回
路(14)とサンプルホールド回路(151を経゛C1
いわゆるH]関2@サンプル回+13(SDA)を経た
後A/D変換され、演算処理部(3)のマイコン部(1
つに入力され、記憶部1181 VC−時保峙される。
A direct current voltage higher than the threshold voltage is applied to the control gate (6). Charge storage section (5a) to (5n) The charge storage section in which K is accumulated is determined by the accumulation time Tint in the timing chart shown in Fig. 7, the incident photoacid, and the dark current.When there is a large amount of incident photoacid, the accumulation time Tint is A monitoring means (not shown in FIG. 5) is used to adjust the accumulation time T so that the accumulation time T is short and when the amount of incident photoacid is small, the accumulation time T is lengthened to provide a wide dynamic range t% with respect to the incident photoacid.
Clean up int. Charge accumulation g(
The signal charge transfer section (5a) to (5n)
11) is completed, and in the period tli, each charge storage unit (
The transfer of the i-word electric music stored in 5a) to (5n) is started. The signal charge to be transferred is converted into a voltage signal by the output section (131) provided at the end of the transfer section tll), and the signal charge stored in each charge storage section (5a) to (5n) is sequentially transferred to the output section (131). Convert to signal voltage (hereinafter,
The 1b output voltage of the output section X13) is called the time-series output voltage)
. This time series output voltage is passed through a clamp circuit (14) and a sample hold circuit (151) in the signal processing section (2) to C1.
After passing through the so-called H] Seki 2@sample times + 13 (SDA), it is A/D converted and then sent to the microcomputer section (1) of the arithmetic processing section (3).
The data is input to the storage unit 1181 and stored in the VC-Jibo storage unit.

以上のような信号読み出しを数向くリペした後、マイコ
ン部(17)で数回の読み出しの平均値を演算し、感光
画素(4a)〜(4n)の九眼の相対分布を求めていた
After repeating the above signal readout several times, the microcomputer unit (17) calculates the average value of the several readouts to obtain the nine-eye relative distribution of the photosensitive pixels (4a) to (4n).

〔発明が解決しようとする課題1 第8図(atに典型的な時系列信号電圧を示す。入射光
酸が少ないときには、蓄積時+’+i Tintを長く
せねばならず、その結果、光酸に対応する信号電圧に暗
電流に対応する信号電圧と同等レベルの暗時出力が@資
され第81’Hblに示すように暗時出力は各1lI1
1茗出力trjにはらついているために感光画素の光1
+布に対応しなくなる。また、このときの暗時出力のほ
とんどは、電荷蓄積部で発生する暗時出力である従来の
固体撮は装「8の信号処理方法では上記の暗時出力を補
償するような構成ではないので、入射光酸が少ないとき
、すなわち暗いm、写体を固体+@酸装置に写したとき
のS/N比が悪いので、正禰な被写体の光咀分布を検出
rることかできないなどの問題県があった。
[Problem to be Solved by the Invention 1 Figure 8 (at) shows a typical time-series signal voltage. When the amount of incident photoacid is small, +'+i Tint must be lengthened during accumulation, and as a result, the photoacid The signal voltage corresponding to the dark current has the same level of dark output as the signal voltage corresponding to the dark current. As shown in No. 81'Hbl, the dark output is
1.The light of the photosensitive pixel is 1 because the output trj is fluctuating.
+ It is no longer compatible with cloth. In addition, most of the dark output at this time is the dark output generated in the charge storage section.The conventional solid-state camera is not configured to compensate for the dark output with the signal processing method described in section 8. , When there is little incident photoacid, that is, when it is dark, the S/N ratio is poor when photographing the subject on a solid + @ acid device, so it is impossible to detect the exact light distribution of the subject. There was a problem prefecture.

この発明は上記のような間1頂点を解消するためになさ
れたもので、従来と同一の入肘光醗時のS州北を改屏で
きるとともに、従来よりも入射光酸の少ないところまで
内体撮1象疲1・冒を使用できる同体撮像装置の信号処
理方法を碍ることを目的とする。
This invention was made in order to eliminate the above-mentioned gap, and it is possible to change the S state north at the same time as before, and also to reduce the amount of incident photoacid to a place where there is less incident photoacid than before. The purpose of this invention is to improve a signal processing method for a body image pickup device that can use body image sensors.

〔課題を解決rるための手段〕[Means for solving problems]

この発明に係る固体撮I3!装置l譚の信号処理部唐は
、固体礒1象裟置の各感光画素に信号電荷を電荷蓄積部
に転送する第1の制+i[l]ゲートと直接電性排出ド
レイン部へ排出する第2の制御ゲートを設け、第1四目
のイ言号読み出しでは第1の1目1仰ゲートにしきい値
電圧以上の電圧を加え導通伏蝦にし信号電圧と暗時出力
を続みIB L、第2回目の信号読み出しでは第2の制
呻ゲートにしきい哨電圧以上の電圧を加え4橿伏傅にし
覗荷蓄債部の暗時出力電圧を、1売み出すようにしたも
のである。
Solid-state imaging I3 according to this invention! The signal processing section of the device includes a first control gate that transfers the signal charge to the charge storage section for each photosensitive pixel of the solid-state sensor, and a second gate that directly discharges the signal charge to the charge discharge drain section. 2 control gates are provided, and when reading the 1st and 4th A word, a voltage higher than the threshold voltage is applied to the 1st 1st and 1st raised gates to make them conductive, and the signal voltage and dark output continue. In the second signal readout, a voltage higher than the threshold voltage is applied to the second suppressing gate so that the output voltage during the dark period of the storage unit increases by 1.

〔作用〕[Effect]

この発明における固体撮画装置の信号処理3広は、信号
電圧に暗時出力が暇畳された出力電圧と電荷蓄積部の暗
時出力が別々に読み出され、マイコン内部で前者から後
者を差し引くことにより、暗時出力を少なくした信号出
力を得る。
In the signal processing of the solid-state imaging device according to the present invention, the output voltage obtained by adding the dark output to the signal voltage and the dark output of the charge storage section are read out separately, and the latter is subtracted from the former within the microcomputer. By doing so, a signal output with reduced dark time output is obtained.

〔実施例] 吸ド、この発明の一実施−1を図について説明rる。第
1図において、(9a)〜(9n)は感光画素(4a)
〜〔4n)の隣りに設けた第2の電荷排出ドレイン部、
Oωは感光画素(4a)〜(4n)で発生する信号電荷
の第2の電荷排出用ドレイン部の流入を制岬する第2の
制御ゲートで、第2の電排出ドレイン部(9a)〜(9
n)および第2の制御ゲート(10)を設けた以外は前
記従来のものとその構成は変わらない。たたし、(6)
の制御ゲートは第1の制御ゲート、(7a)〜(7n)
の電尚排出用ドレイン部は第1の電荷排出用ドレイン部
とする。第2図はn型基板内のP型拡赦層内に形成され
た第1図の[1−II線における断面図、第3図は第1
図で構[戊される各ゲートに人力されるクロック電圧の
タイミングチャートを示し、図において、(alは転送
部α1)に入力される転居部クロック電圧、tblは第
1の1bII御ゲート(6)に入力されるクロック電圧
、tc)は第2の制御ゲート(101に人力されるクロ
ック電圧、(diはクリアゲート(8a)〜(8n)に
人力されるクリアゲートクロック、(e)はトランスフ
ァゲート(12)に入力されるトランスファーゲートク
ロノクで、(flは各タイミングを示す。
[Example] One embodiment of the present invention-1 will be explained with reference to the drawings. In FIG. 1, (9a) to (9n) are photosensitive pixels (4a)
~ [4n) a second charge discharging drain section provided next to the
Oω is a second control gate that restricts the inflow of signal charges generated in the photosensitive pixels (4a) to (4n) into the second charge discharge drain section; 9
The configuration is the same as the conventional one except for the provision of the second control gate (10) and the second control gate (10). Tatashi, (6)
The control gates are the first control gates, (7a) to (7n)
The charge discharging drain section is the first charge discharging drain section. Figure 2 is a cross-sectional view taken along the [1-II line] of Figure 1 formed in the P-type amended layer in the n-type substrate, and Figure 3 is a cross-sectional view of the
The figure shows a timing chart of the clock voltage manually applied to each gate to be omitted. In the figure, (al is the transfer unit clock voltage input to the transfer unit ), tc) is the clock voltage manually input to the second control gate (101), (di is the clear gate clock manually input to the clear gates (8a) to (8n), and (e) is the transfer gate clock voltage input manually to the second control gate (101). In the transfer gate clock input to the gate (12), (fl indicates each timing.

次に動作について説明する。第3図fflのタイミング
チャートで示す1回目の信号読み出しのt3の期間Cは
第1の制呻ゲート(6)にはしきい#電圧以上の電圧が
加えられ、第2の制御ゲートtlo)にはしきい哨電圧
以ドの4圧が加えられるので、i!尚蓄積部(5a)〜
(5n)のi番目には次(1)式に示すような信号電荷
Qsig+filが蓄積される。
Next, the operation will be explained. During period C of t3 of the first signal readout shown in the timing chart of FIG. Since four voltages above the threshold voltage are applied, i! Furthermore, the storage section (5a) ~
A signal charge Qsig+fil as shown in the following equation (1) is accumulated in the i-th cell of (5n).

Qsig +I il = Qphoto d it 
+ Qdarkp Dlfil + Qdarkstl
(i) −il)ここで、Qphoto+(ilは1番
目の感光画素(41)で入射光醋に対応して発生する光
信号電荷、Qdarkp D 、I i)はl溶目の感
光画素(41)で入射光駿に関係なく発生する暗電流に
よる暗出力電荷、Qdarkst +(i)はi番目の
電荷蓄積部(51)でへ肘光喰に関係なく発生する暗電
流による暗出力電荷である。各電荷蓄積部(5a )〜
(5n )で蓄積された電荷 Qsig+filは転送
部fullで転送され出力部(131で電圧信号に変換
される。
Qsig +Iil = Qphoto d it
+ Qdarkp Dlfil + Qdarkstl
(i) -il) Here, Qphoto+(il is the optical signal charge generated in response to the incident light at the first photosensitive pixel (41), Qdarkp D, Ii) is the photosensitive pixel (41) at the first photosensitive pixel (41), ) is the dark output charge due to the dark current generated regardless of the incident light, and Qdarkst + (i) is the dark output charge due to the dark current generated regardless of the incident light at the i-th charge storage section (51). . Each charge storage section (5a) ~
The charge Qsig+fil accumulated at (5n) is transferred at the transfer section full and converted into a voltage signal at the output section (131).

Qsig+Iilに対応する信号電圧Vsigt(il
はVsig山1= Vphotottil+ Vdar
kpD1til+ Vdarkstl(il ・−−−
i21となる。Vsigt(i) 、 Vphotot
[il t VdarkpDltil 、 Vdark
stt(ilはQsigt(il + Qphotol
til 、 QdarkpD山1 、 Qdarkst
l(il に比例する電圧である。第4図(alに出力
部(131の出力における電FJF、波形の一部と、そ
のとき(7) Vsigt(il 、 Vphotol
?tl、■arkpD、(i) +■arkst+fi
)の典型的な割合を示す。この図で示されるように各感
光画素(4a)〜(4n)で発生する暗出力電圧■ar
kpp1fil (i = a 〜n )よりも各電荷
蓄積部(5a)〜(5n)で発生する暗出力電、圧Vd
arkstt(il(i=a−n)の方が一般的に[賄
いレベルにある。各電荷蓄積部(5a)〜(5n)の蓄
積電荷に対応する信号電圧Vsigt(ilは信号処理
部(2)に入力され、相関2乗サンプリング回路とA/
D変換され演算処理部(3)のマイコン部(閉に入力さ
れた後、−1,1記憶部0印に保持される。第2図ff
+のタイミングチャートで示す2回目の信号読み出しの
17の期間では第1の制岬ゲート(6)にはしきい値電
圧以ドの電圧が加えられ、第2の制御ゲート(1ωには
しきい値電圧以上の電尚が加えられるので、各感光画素
部(4a)〜(4n)で発生する光信号電荷Qphot
o2(ilおよび暗出力電荷QdarkpD2filは
第2の電荷排出用ドレイン部(9a )〜(9n)に排
出する。その結果、電荷蓄積部(5a)〜(5n)のi
番目には次(3)式に示されるような信号電荷Qsig
2(ilが蓄積される。
The signal voltage Vsigt(il
is Vsig mountain 1 = Vphotottil + Vdar
kpD1til+ Vdarkstl(il ・---
It will be i21. Vsigt(i), Vphotot
[il t VdarkpDltil, Vdark
stt(il is Qsigt(il + Qphotol
til, QdarkpD mountain 1, Qdarkst
It is a voltage proportional to l (il. Figure 4 shows a part of the waveform of the voltage FJF at the output of the output section (131) and (7) Vsigt (il, Vphotol).
? tl, ■arkpD, (i) +■arkst+fi
). As shown in this figure, the dark output voltage ■ar generated in each photosensitive pixel (4a) to (4n)
The dark output voltage and voltage Vd generated in each charge storage section (5a) to (5n) from kpp1fil (i = a to n)
arkstt(il (i=a-n) is generally at a sufficient level. The signal voltage Vsigt(il is the signal voltage Vsigt(il) corresponding to the accumulated charge of each charge storage section (5a) to (5n) ), and the correlation square sampling circuit and A/
After being converted into D and input to the microcomputer section (closed) of the arithmetic processing section (3), it is held at -1,1 storage section 0 mark. Fig. 2 ff
During period 17 of the second signal readout shown in the + timing chart, a voltage equal to or higher than the threshold voltage is applied to the first control gate (6), and a voltage equal to or higher than the threshold voltage is applied to the second control gate (1ω). Since a voltage higher than the value voltage is applied, the optical signal charge Qphoto generated in each photosensitive pixel portion (4a) to (4n)
o2(il and dark output charge QdarkpD2fil are discharged to the second charge discharging drain parts (9a) to (9n). As a result, i of the charge storage parts (5a) to (5n)
The signal charge Qsig as shown in the following equation (3) is
2(il is accumulated.

Qsig2fi) = Qdarkst2(il   
  −(31ここでQdarkst2(ilはil目の
電荷、4’!:積部(51)で入射光醗に関係なく発生
する暗電流による暗出力電荷である。この信号電荷Qs
ig2filは、転送部(11)で転送され出力部(1
3)で重臣(苦吟に変換される。Qsig2filに対
応する信号電圧Vsig2+ilは、Vsig2(il
 = Vdarkst2fil       −(4)
となる。第4図(b)に1n力部(131の出力におけ
る電圧波形の一部とそのときのVsig2(it 、 
Vdarkst2(itの典型的な割合を示す。ただし
、第2図+f+の期間t3およびt7の蓄積時間Tin
t+およびTint2はTintl = Tint2−
−   t5)とするので、 VdarksT、fil= Vdarkst2fi) 
 (i=a−n) −= t61となる。簡(4)式で
示される信号電圧Vsig2(i)は信号処理部(2)
に入力され、相間2乗サンプリング回路とA/D変換回
路と経た後、演算処理部(3)のマイコン部t17)に
入力され前述のいったん記1意部(潮に保持されている
1回目の信号読み出しの信号電圧Vsig+(ilから
2回目の信号読み出しの信号電圧Vsigz(itを差
し引くことをマイコン部(I7)内で行い、その結果、
電荷蓄積部(5a)〜(5n)における暗出力電圧■a
rksT1fit(= Vdarks・r2(i) )
  を除去した次(7)式に示すような信号電圧Vsi
gがマイコン内部(17)で演算される。
Qsig2fi) = Qdarkst2(il
-(31 Here, Qdarkst2(il is the il-th charge, 4'!: is the dark output charge due to the dark current generated in the product part (51) regardless of the incident light. This signal charge Qs
ig2fil is transferred by the transfer unit (11) and output to the output unit (1
3), the signal voltage Vsig2+il corresponding to Qsig2fil is converted to Vsig2(il
= Vdarkst2fil - (4)
becomes. FIG. 4(b) shows a part of the voltage waveform at the output of the 1n power section (131) and Vsig2(it,
Vdarkst2(it shows a typical ratio of Vdarkst2(it). However, the accumulation time Tin of periods t3 and t7 of
t+ and Tint2 are Tintl = Tint2−
- t5), so VdarksT, fil= Vdarkst2fi)
(i=a−n) −=t61. The signal voltage Vsig2(i) shown by the simple equation (4) is
After passing through the phase-to-phase square sampling circuit and the A/D conversion circuit, it is input to the microcomputer section t17 of the arithmetic processing section (3) and is inputted to the above-mentioned once-input section (the first The signal voltage Vsigz(it) for the second signal readout is subtracted from the signal voltage Vsig+(il for the signal readout) in the microcomputer unit (I7), and as a result,
Dark output voltage ■a in charge storage sections (5a) to (5n)
rksT1fit (= Vdarks・r2(i))
The signal voltage Vsi as shown in the following equation (7) after removing
g is calculated inside the microcomputer (17).

Vsig = Vsig+ −Vsig2 = Vph
otol (il+■arkpo、(il +Vdar
ksT、 fil −VdarksT2fit =Vp
hoto+fil + VdarkpD、fit −f
7)前(2)式で示される信号出力Vsig+(i)の
各電圧Vphoto山)、 VdarkpD、fit 
、 Vdarkst山)の、IJ、11合が第4図fc
lであるとき、以上のような信号処理をもってすれば、
前(7)式の信号出力は、第4図fd)のようになり、
信号出力Vsig(nlに対して、雑冴1戊分が低減さ
れる。
Vsig = Vsig+ -Vsig2 = Vph
otol (il+■arkpo, (il +Vdar
ksT, fil −VdarksT2fit =Vp
hot+fil + VdarkpD, fit -f
7) Signal output Vsig + (i) voltage Vphoto peak), VdarkpD, fit shown in the previous formula (2)
, Mt. Vdarkst), IJ, 11th station is shown in Figure 4 fc
l, and with the above signal processing, we get
The signal output of the previous equation (7) is as shown in Figure 4 fd),
For the signal output Vsig(nl), one part of noise is reduced.

なお、上記実施例では1回目の信号1恍み出しては第1
の制御ゲート(6)をしきい値電圧以上とし第2の制御
デー1− tlo)をしきい値電圧以ドにし、その後、
2回目の信号、涜み出しでは第1の制御ゲート(6)を
しきい偵電圧以ドとし、第2の制御ゲートtlD)をし
きい値電圧以上にした場合を示したが、1回目と2回目
の信号、売み出しを逆にしても燈しつかえなく、また、
1回目と2回目の信号読み出しを複数回くり返し行って
も差しつかえない。
In addition, in the above embodiment, when the first signal 1 is output, the first signal is
Set the control gate (6) of
In the second signal detection, the case where the first control gate (6) was set to the threshold voltage or higher and the second control gate (tld) was set to the threshold voltage or higher was shown. At the second traffic light, even if I reversed the direction, the light still wouldn't turn on, and again,
There is no problem even if the first and second signal readings are repeated multiple times.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、電荷蓄積部で発生する
帷片;戊分Vdarf<st fn)を信号出力より各
1lilI素ごとにキャンセルできるようにしたので、
従来よりもS/N比が向上し、その結果、従来よりも低
照度の被写体を固体撮像装置に厚すことができ、かつ各
画素ごとに雑音成分をキャンセルしているので、コント
ラストの少ない゛低照度の被写体を写しても従来よりも
ノイズの少ない絵が再現できる。
As described above, according to the present invention, since the band (Vdarf<st fn) generated in the charge storage section can be canceled for each lilI element from the signal output,
The S/N ratio is better than before, and as a result, it is possible to capture objects with lower illuminance on the solid-state imaging device than before, and since the noise component is canceled for each pixel, it is possible to capture images with less contrast. Even when photographing subjects in low light, images with less noise than before can be reproduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による幅体撮像装置の概略
と信号処理部と演算処理部の接続を示す説明図、第2図
は第1図のII −n 緑における飼えばn型基板内の
P型拡牧層内に形成された断面図、第3図は第1図の固
体撮像袋d部に入力される信号のタイミングチャート、
第4図(a)は第3図(f)のタイミングt4LU降に
出力部より出力される波形図、図(blは第3図tfl
のタイミングチヤートに出力部より出力される波形図、
図fc)は図fa)の信号出力の成分比を示す表の図、
図(dlは維ぎ成分をキャンセルしこ後の信号出力の[
戊か比を示す表の図、第5図は従来の固体撮[象装圃の
概略と信号処理部と演算処理部の接続を示す説明図、第
6図は第5図の■■線における例えばn型基板内のD型
拡赦同内に形成されたlfr面図、第7図は第5図の固
体撮像装置に人力される各信号のタイミングチャート、
第8図fa)は第5図に示される出力部より出力される
信号波形図、図fb)は[](atで示される信号波形
の信号成分を示す波形図である。 図において(1)は固体撮像装置、(2)は信号処Ji
I!部、(3)は演算処理部、(4a)〜(4n)は感
光画素部、(5a)〜(5n)は電鍔蓄積部、(6)は
第1の制御デート、(7a)〜(7n)は第1の電荷排
出ドレイン部、(9a)〜(9n)は第2の電荷排出ド
レイン部、(I(ト)は第2の制(財)ゲート、(11
)は転送部、(13は出力部、(17)はマイコン部、
(18)は記憶部を示す。 なお、図中、同一符号は同一、又は(I当部分を示す。
FIG. 1 is an explanatory diagram showing an outline of a wide body imaging device according to an embodiment of the present invention and connections between a signal processing section and an arithmetic processing section, and FIG. 2 is an n-type board in the II-n green shown in FIG. 3 is a timing chart of the signal input to the solid-state imaging bag d section of FIG. 1,
FIG. 4(a) is a waveform diagram output from the output section at timing t4LU of FIG. 3(f).
The waveform diagram output from the output section is shown in the timing chart of
Figure fc) is a table showing the component ratio of the signal output of Figure fa),
Figure (dl is the signal output after canceling the maintenance component [
Figure 5 is an explanatory diagram showing the outline of the conventional solid-state imaging system and the connections between the signal processing section and the arithmetic processing section. For example, FIG. 7 is a timing chart of each signal manually input to the solid-state imaging device of FIG. 5,
Fig. 8 fa) is a signal waveform diagram output from the output section shown in Fig. 5, and Fig. fb) is a waveform diagram showing signal components of the signal waveform indicated by [](at. is a solid-state imaging device, (2) is a signal processing Ji
I! (3) is an arithmetic processing unit, (4a) to (4n) are photosensitive pixel units, (5a) to (5n) are electric charge storage units, (6) is a first control date, (7a) to ( 7n) is the first charge discharging drain part, (9a) to (9n) are the second charge discharging drain parts, (I(T) is the second control gate, (11)
) is the transfer section, (13 is the output section, (17) is the microcomputer section,
(18) indicates a storage section. In addition, in the figures, the same reference numerals indicate the same parts or (I).

Claims (1)

【特許請求の範囲】[Claims] 基板上に配列した複数の画素の各々において光電変換を
行ない入射光量に応じた光電荷を発生する感光画素部と
、この感光画素部で発生する信号電荷を一時的に蓄積す
る電荷蓄積部と、前記感光画素部から電荷蓄積部への信
号電荷の流入を制御する第1の制御ゲートと、前記電荷
蓄積部に蓄えられる信号電荷を排出する第1の電荷排出
ドレイン部と、前記感光画素部で発生する信号電荷を排
出する第2の電荷排出ドレイン部と、前記感光画素部か
ら第2の電荷排出ドレイン部への信号電荷の流入を制御
する第2の制御ゲートと、前記電荷蓄積部で一定期間蓄
積された信号電荷を転送する転送部と、前記転送部で転
送される信号電荷を電圧信号に変換する出力部とを備え
た固体撮像装置と、前記出力部の信号を処理する信号処
理部と、前記信号処理部の入射光量に応じた時系列信号
を演算処理するマイコン部と、前記演算処理結果を記憶
する記憶部を備えた固体撮像装置の信号処理方法におい
て、数回の時系列信号の読み出しを行なう際、第1回目
の読み出し時には第1の制御ゲートに前記感光画素部か
ら電荷蓄積部へ電荷を流入させるしきい値電圧以上の第
1の制御電圧を加え、第2回目の読み出し時には第2の
制御ゲートに第2の制御電圧を加え、この第1回目、第
2回目の読み出しの操作を数回くり返したことを特徴と
する固体撮像装置の信号処理方法。
a photosensitive pixel section that performs photoelectric conversion in each of the plurality of pixels arranged on the substrate and generates photocharges according to the amount of incident light; a charge storage section that temporarily accumulates signal charges generated in the photosensitive pixel section; a first control gate that controls the inflow of signal charges from the photosensitive pixel section to the charge storage section; a first charge discharge drain section that discharges the signal charges stored in the charge storage section; a second charge discharge drain section that discharges generated signal charges; a second control gate that controls the inflow of signal charges from the photosensitive pixel section to the second charge discharge drain section; A solid-state imaging device including a transfer section that transfers signal charges accumulated over a period of time, an output section that converts the signal charges transferred by the transfer section into a voltage signal, and a signal processing section that processes the signal of the output section. In a signal processing method for a solid-state imaging device, the signal processing method for a solid-state imaging device includes a microcomputer unit that performs arithmetic processing on a time-series signal according to the amount of incident light of the signal processing unit, and a storage unit that stores the result of the arithmetic processing. When performing readout, a first control voltage equal to or higher than a threshold voltage that causes charges to flow from the photosensitive pixel section to the charge storage section is applied to the first control gate during the first readout, and the second control voltage is applied to the first control gate. A signal processing method for a solid-state imaging device, characterized in that a second control voltage is sometimes applied to a second control gate, and the first and second read operations are repeated several times.
JP1167595A 1989-06-29 1989-06-29 Signal processing method for solid-state image pickup device Pending JPH0332284A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1167595A JPH0332284A (en) 1989-06-29 1989-06-29 Signal processing method for solid-state image pickup device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1167595A JPH0332284A (en) 1989-06-29 1989-06-29 Signal processing method for solid-state image pickup device

Publications (1)

Publication Number Publication Date
JPH0332284A true JPH0332284A (en) 1991-02-12

Family

ID=15852678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1167595A Pending JPH0332284A (en) 1989-06-29 1989-06-29 Signal processing method for solid-state image pickup device

Country Status (1)

Country Link
JP (1) JPH0332284A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003010288A (en) * 2001-06-27 2003-01-14 Unitech Tokyo:Kk Managing apparatus for administrating drug

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003010288A (en) * 2001-06-27 2003-01-14 Unitech Tokyo:Kk Managing apparatus for administrating drug
JP4685280B2 (en) * 2001-06-27 2011-05-18 エーザイ・アール・アンド・ディー・マネジメント株式会社 Drug dose management device

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