JPH0332272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital time axis correction device that corrects fluctuations in the time axis of a reproduced video signal from a recording/playback device, and particularly relates to a technique for clearing the vertical period of a write address for a memory included therein. .

One method of recording television video signals on magnetic tape is to wrap the magnetic tape around a cylinder (drum) containing a rotating head and run it, leaving a diagonal recording trace of the video signal on the tape (as shown in Figure 1). There is a helical scanning video tape recorder device that forms a video track), and it has come to be widely used not only for consumer use but also as a professional device for industrial and broadcasting purposes.

In the case of this helical scanning video tape recorder device, it is common to record one field or multiple fields of video signals on one video track, and the rotating head is used to vertically synchronize the input video signal to be recorded. It is designed to rotate in synchronization with the signal. Since there are many devices in which one field of video signal is recorded on one video track, this case will be described below, but the present invention records one field of video signal on one video track. Needless to say, this is not limited to the case.

When one field of video signals is recorded on one video track, as shown in Figure 1, the rotary head is set so that the vertical blanking section is located at the end of each video track (the edge of the tape). controlled.
This control is performed by controlling the rotation of the rotary head by comparing the phase of a tachometer signal generated by detecting the rotational phase of the rotary head with a vertical synchronizing signal of the input video signal. Therefore, during recording, the vertical synchronization signal of the input video signal and the tachometer signal always have a constant phase relationship.

If one main video recording/reproducing rotary head is attached to the rotary body on which the rotary head is attached (so-called one-head system), the video track is formed by only one rotary head. , a small portion of the video signal is missing from the top end of the tape to the bottom end of the tape. However, in cases where two or more main video recording/playback rotary heads are mounted on a rotating body (in the case of a so-called 2-head system, etc.)
After one rotating head finishes scanning the tape,
For example, just before exiting from the top of the tape, the next head enters from the bottom of the tape, and the top of the video track and the bottom of the next video track overlap and record the same signal. In some cases, it may be done. In this case, no missing portion of the video signal occurs.

When reproducing a recorded video signal, the rotary head is controlled to rotate at a fixed number of revolutions, such as by rotating in synchronization with a synchronization signal sent from a reference synchronization signal generator or other reference signals. Ru.
Also, the phase of tape travel, such that the rotating head tracks directly over the video track, is controlled, for example, by controlling the rotation of a capstan that drives the tape.

Now, if only the running of the tape were to be stopped during playback, the rotary head would repeatedly scan the same part of the tape in the direction of arrow A, drawing a trajectory as shown by straight line PQ' in Figure 1, for example. Become.
This means that when the tape is running steadily in the direction of arrow B in Figure 1, the rotary head that was scanning the previous video track finishes its run and passes point Q', and the next rotary head scans the previous video track. passes point P and begins scanning, and the tape is being scanned once by the video tape while the rotary head is scanning the tape once.
As the track advances by one pitch, the rotating head moves to P.
During one scan of the tape from point to point Q, point Q actually moves to point Q', and one video track from point P to point Q is formed on the tape. will be done. When the tape stops running at this point, the rotating head also moves from point P.
While the tape is scanned toward point Q', the tape does not move, so the tape is similarly scanned from point P to point Q'. Therefore, in this case, the rotary head that was scanning directly above the video track at point P gradually falls off the track, then gradually moves onto the next track, and at point Q' it moves onto the next track. It will scan directly above.

The width of the video track is, for example, 180 μm, and the gap between the tracks (guard band) is often selected to be approximately 2:1, for example, 90 μm. Therefore, as the rotary head falls off the track, the signal-to-noise ratio (S/N) of the signal deteriorates, and beat disturbance occurs while the rotary head is scanning over two tracks.

However, as shown in Figure 1, if the phases of the horizontal synchronizing signals _S Even when running in the opposite direction (direction) or in the opposite direction, the image can be monitored on the video monitor even if there is a noise band due to beat interference. This is called static or slow-motion playback, and is convenient for finding the start and end points of necessary scenes when organizing a program. The ability to easily perform such still or slow motion playback is one of the features of a helical scanning video tape recorder device that records one field or multiple fields of video signals on one video track.

Furthermore, if a digital time base corrector equipped with an instantaneous lock type clock regenerator is used, the program on the tape can be viewed as an image even during fast forwarding or rewinding.

When the tape is run in the opposite direction at the same speed as when running normally, the point Q'' moves to the point Q' while the rotary head scans from point P to point Q in Figure 1. The rotating head will apparently scan from point P to point Q'' on the tape.

In the case of static playback (playing the tape stationary to obtain a still image), the rotating head scans the tape from point P to point Q', but in the case of steady playback, it scans from point P to point Q. Compared to the case shown in FIG. 1, the scanning length is shorter by 1.5H (horizontal synchronization period). For convenience of explanation, the video track width and angle are exaggerated in Figure 1.
The number of horizontal synchronization signals in the video track of the book is also much smaller than in the actual case, but in the actual device, the number of horizontal synchronization signals is 2.5H less in the case of static playback than in the case of steady playback. Often designed. In this case, if you run the tape in the opposite direction at the same speed as when it is running normally,
5H less.

However, since the rotating head always rotates at a constant speed, the time it takes to scan the tape from point P to point Q is equal to the time it takes to scan the tape from point P to point Q' or from point P to point Q''. If the number of horizontal synchronization periods that are played while the rotating head scans the tape once is reduced, one horizontal synchronization period becomes longer by that amount. When the number of horizontal synchronization periods increases (which occurs when the tape runs in the forward direction at a speed higher than the normal running speed), one horizontal synchronization period becomes shorter.

When playing in a stationary state, slow motion, fast forwarding, or rewinding, the length of the horizontal synchronization period changes considerably. A video signal with a changed horizontal synchronization period is normally processed into a regular video signal by a digital time base corrector (timebase collector).

A system diagram of this type of digital time axis correction device is shown in FIG. The input video signal 11 is converted into an 8- to 10-bit digital signal by an A/D converter 12 using, for example, a clock that is four times or three times as large as the color subcarrier, and is written into a memory 13. On the other hand, a synchronization separation circuit 17 separates a synchronization signal 18 and a burst signal 19 from the input video signal 11. A write clock generation circuit 22 generates a write clock 20 and a write address/clear pulse 21 from the synchronization signal 18 and the burst signal 19.
writing to is controlled. At the same time, write clock 2
0 is also used as the conversion clock for A/D converter 12.

On the other hand, based on the reference video signal or synchronization signal 23, the read clock generation circuit 24 generates the read clock 26 and the read address/clear pulse 26.
occurs. The read clock 26 has the same frequency as the write clock 20, e.g.
It has twice the frequency (14.318MHz). Since the reference video signal or synchronization signal 23 is not a signal with time axis fluctuations like the input video signal 11, but is a stable signal, no special measures are required in the circuit 24 for generating the read clock.

This read clock 26 and the read address
The digital video signal read out from the memory 13 by the read address signal derived from the clear pulse 25 is converted into a normal (analog) video signal by the D/A converter 14 and converted into a blanking part and a synchronization signal by the process amplifier circuit 15. After the portion is shaped, it becomes an output video signal 16. In this case, the output video signal 16 is the reference video signal or the synchronization signal 2.
3 and is stabilized, and all time axis fluctuations are removed.

The memory 13 includes a group of memory cells, a write address counter that receives the aforementioned write clock 20 and write address clear pulse 21 to generate a write address for the memory cell, and further receives the aforementioned read clock 26 and read address clear pulse to generate a write address for the memory cell. The input digital video signal is stored in the memory cell specified by the write address, and read from the memory cell specified by the read address. In the case of the time axis correction device, since the write clock 20 has the same time axis fluctuation as that of the input video signal, the write address also has the same time axis fluctuation, and as a result, the input digital video signal is fixed on the memory cell and read out using a read address based on a stable read clock, thereby removing time axis fluctuations included in the video signal.

However, conventional time axis correction devices of this type generally have a small memory capacity, and are not able to adequately cope with large increases and decreases in the horizontal period and large changes in the horizontal synchronization period that occur when special playback is performed. . In other words, the write/read address structure for memory cells in the memory 13 is circular, but if a read address and a write address are overtaken or overtaken, the input/output relationship will be reversed, causing an inconvenience. occurs. In normal playback, the average frequency of the write clock and read clock is the same, so unless the time axis fluctuation is extremely large or the write address and read address are close, Although it is unlikely that such overtaking or being overtaken will occur, in the case of special playback, as mentioned above, the number of horizontal synchronization periods during the vertical synchronization period may change significantly, or the frequency of the write clock may change. As the vehicle changes, such overtaking or being overtaken becomes more likely to occur, and it becomes more likely to occur if the memory capacity is small.

The purpose of the present invention is to develop a digital digital camera that can sufficiently cope with cases where the number of horizontal synchronization periods included in the vertical synchronization period or the horizontal synchronization period changes significantly, such as when playing in a stationary, slow motion, fast forward, or rewind state. The object of the present invention is to obtain a time axis correction device.

In the present invention, the memory capacity is made large enough to have multiple lines (10 lines or more), and a clear pulse for the write address that is surely vertically synchronized is prepared, so that the write address is in the vertical synchronization phase on the time axis. A time axis correction device that clears the write address counter so that it becomes the center of the correction range can be obtained.

In the embodiment of the present invention, in the configuration shown in FIG. 2, the memory 13 has a capacity of 10 lines or more, and the write address clear pulse 21 has horizontal and vertical write address clear pulses, and this vertical synchronization The write address clear pulse clears the address counter in the memory 13 so that the write address is at the center of the correction range.

Next, the configuration of the write clock generating circuit 22 shown in FIG. 2 according to the present invention will be explained. Third
The figure shows the configuration of this write clock generation circuit, in which the horizontal synchronizing signal 18 and the output of the control oscillator 38 are passed through a 1/2 step-down circuit 39, and then passed through a phase comparator 4.
0, and by feeding back to the controlled oscillator 38 through the error mixer 41, an output signal of the controlled oscillator 38 having a frequency twice the horizontal synchronizing frequency locked to the input horizontal synchronizing signal 18 is obtained.

On the other hand, the horizontal synchronizing signal 18 is delayed by approximately 1H in a 1H (line) delay circuit 47 and then compared in phase with the input horizontal synchronizing signal 18 in a phase comparator circuit 48 . In this way, the frequency change of the input horizontal synchronizing signal 18 can be detected as the output signal of the phase comparison circuit 48. By error mixing 41 the output signal of the phase comparator 48 with the output signal of the phase comparator 40, the lock range with respect to changes in the input horizontal synchronization period of the controlled oscillator 38 can be made wider. In this case, if the controlled oscillator 38 is constructed of a one-shot multivibrator as shown in FIG. 4, it can be made into a circuit substantially the same as the 1H delay circuit 47. With this configuration, it is possible to obtain a wide lock range with respect to changes in the input horizontal synchronization period with extremely stability including temperature characteristics.

The one-shot multivibrator shown in Figure 4 is a monolithic IC.
For example, it is called the product name 96S02 and has trigger inputs 51 and 52, a resistor _R1 and a capacitor C inserted between it and the power supply (V+), and a resistor inserted between it and the control signal input 53. The signal delayed by the amount determined by the time constant of the device R etc. is the output signal (Q).
54. In this case, by directly connecting the output signal 54 to the input 51 or 52, it is possible to construct an oscillator whose period is approximately equal to the signal delay amount of this one-shot multivibrator. By changing the voltage applied to the control signal input 53, the signal delay amount of this one-shot multivibrator can be changed, and therefore, when an oscillator is configured, its oscillation frequency can be changed or controlled.

Returning to Figure 3, the output of the controlled oscillator 38 is halved.
The down-down signal 39 is further down-downed to 1/2 by a line flip-flop 42. The output signal 43 of this line flip-flop 42 has a frequency that is half that of the horizontal synchronization signal, and has a digital time error corresponding to the fact that the color subcarrier of the NTSC color video signal is inverted in phase every horizontal synchronization. This is a signal that plays an important role in the correction device. This signal is used for phase alignment of burst signals and memory address control, which will be described later.

In Figure 2, if the capacity of the main memory cell in the memory 13 (this becomes the time error correction amount of the digital time error correction device) is only for 1H line, then the write address/clear pulse should be horizontally synchronized only. However, if there is capacity for multiple lines, a separate address/clear pulse is required to determine which line to write to in order to determine the write phase of the signal. As mentioned above, when playing in a stationary, slow motion, fast forward, or rewind state, the number of horizontal synchronization periods (the number of lines) included in one vertical synchronization period (V), that is, the period in which the rotating head scans the tape once. increases or decreases. Therefore, in order to obtain a regular video signal as an output, if the number of lines is too large in the digital time axis correction device, reduce the number of lines by that amount, and if the number of lines N is too small, increase the number of lines by increasing the vertical blanking period, etc. There is a need. Therefore, the time axis correction range of the digital time axis correction device requires, for example, 10 lines or more. In this case, it is appropriate to clear the vertical write address generating means once every vertical synchronization period at the timing of vertical synchronization so that the write address becomes a value indicating the center address of the time axis correction range. By doing so, the correctable range for each time can be set equally for both correction directions for each vertical synchronization, and it is possible to reliably cope with slow motion and fast-forward special playback.

In FIG. 3, the double horizontal frequency output signal from the controlled oscillator 38 is supplied as a clock to a counter 44, which is counted down to 1/525 to generate an address clear pulse 46 for the write vertical address generation means in the vertical synchronization period. obtain. At the same time, the counter 44 receives a vertical synchronization pulse (not shown) separated from the input video signal 11 obtained by the synchronization separation circuit 17 in FIG. 2 as a reset pulse 45, and thereby also outputs an address clear pulse. do. Therefore, this counter 44 has the ability to memorize the number of lines included in the interval between two pulses of the reset pulse 45 (vertical synchronization period), and even if the reset pulse 45 is missing, The address clear pulse 46 is output by counting a predetermined number of lines included in one immediately preceding vertical synchronization period. As described above, in the present invention, even if the vertical synchronization signal cannot be separated from the input, address clearing can be performed accurately and accurate and stable time base correction operation can be obtained.

The burst signal 19 is supplied to a trigger pulse shaping/selector 31, and is first shaped into pulses. Further, the trigger pulse shaping selector 31 is supplied with the horizontal synchronizing signal 18 and an output signal 43 of a line flip-flop 42 having a frequency 1/2 of the horizontal synchronizing signal. 18
is phase-modulated by a half period of the color subcarrier for each line based on the output signal 43, and one pulse is extracted from the pulse-shaped burst signal based on the output timing. This extracted pulse is used as a trigger pulse 32 to generate an instantaneous lock oscillator 3.
3.

Like the controlled oscillator 38, the instantaneous lock oscillator 33 is a one-shot multivibrator type oscillator, for example, as shown in FIG. Become. A gating circuit 35 can prevent the output 34 of the instantaneous lock oscillator 33 whose input 51 is triggered from being fed back to the input (52 in FIG. 4). The instantaneous lock oscillator 33 oscillates at, for example, three or four times the color subcarrier, and the output signal 34 remains the write clock. This output signal 34
is counted down by a countdown circuit 36 to become a horizontal synchronization period, and its phase is compared with the trigger pulse 32 by a phase comparator 37. Phase comparator 3
7 operates as an oscillation frequency detector for the instantaneous lock oscillator 33, and feeds its output back to the instantaneous lock oscillator 33 as a control signal (53 in Fig. 4).
) to control the oscillation frequency of the instantaneous lock oscillator 33. The output of this phase comparator 37 can also be used in addition to the output of the phase comparator circuit 48.

[Brief explanation of the drawing]

FIG. 1 shows the video on tape of a helical scanning video tape recorder device in which the present invention is implemented.
FIG. 2 is a system diagram of a digital time base correction device, FIG. 3 is a system diagram of a write clock generation circuit according to an embodiment of the present invention, and FIG.
The figure shows an example of a one-shot multivibrator used in an embodiment of the present invention.

Claims (1)

[Claims] 1 A digital time axis correction device that corrects the time axis of a reproduced video signal reproduced by a helical scanning video tape recorder device that records one field of television signals on one video track, and is a memory for storing a playback video signal and having a storage capacity corresponding to a time axis correction range extending over a time period); a write address counter for generating a write address for the memory in synchronization with the playback video signal; a read address counter that generates a read address in synchronization with a reference signal; a clock generating means that generates a first clock signal synchronized with a burst signal in the reproduced video signal and supplies it as a clock to the write address counter; Means for generating a second clock signal having a frequency n times (n: integer) the horizontal synchronization frequency in phase synchronization with the horizontal synchronization signal in the reproduced video signal, and clearing the vertical synchronization signal in the video signal. a vertical clear pulse that is received as a signal, counts the second clock signal, generates a write vertical clear pulse when the value corresponds to a predetermined vertical synchronization period, and outputs it to the write address counter; and a generation counter, the write address counter is reset at the timing of the vertical clear pulse, and the write address is set to an address value approximately corresponding to the center of the time axis correction range. correction device.