JPH0332248B2 - - Google Patents
Info
- Publication number
- JPH0332248B2 JPH0332248B2 JP28577685A JP28577685A JPH0332248B2 JP H0332248 B2 JPH0332248 B2 JP H0332248B2 JP 28577685 A JP28577685 A JP 28577685A JP 28577685 A JP28577685 A JP 28577685A JP H0332248 B2 JPH0332248 B2 JP H0332248B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- shift register
- signal
- b8zs
- data string
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000009826 distribution Methods 0.000 claims description 15
- 238000001514 detection method Methods 0.000 claims description 11
- 238000010586 diagram Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
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- Dc Digital Transmission (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、バイポーラ符号列の零が8個連続す
るブロツクを取り出し、これを別に用意した特殊
な符号パターンに置換するB8ZS符号化回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a B8ZS encoding circuit that extracts a block of eight consecutive zeros from a bipolar code string and replaces it with a special code pattern prepared separately.
第3図にB8ZS符号の変換則を示す。図におい
て、Bはバイポーラ則パルス(前位のパルスと逆
極性のパルス)、Vはバイポーラ則違反パルス
(前位のパルスと同極性のパルス)、0はゼロパル
スを表わす。
Figure 3 shows the conversion rules for B8ZS codes. In the figure, B represents a bipolar law pulse (a pulse with the opposite polarity to the previous pulse), V represents a bipolar rule violation pulse (a pulse with the same polarity as the previous pulse), and 0 represents a zero pulse.
従来、この種のB8ZS符号化回路は、入力デー
タ列を最初に+極性か−極性かに振り分け、その
後、データ列内の0連続信号検出に8ビツトシフ
トレジスタ回路を2回路有し、一方の8ビツトシ
フトレジスタにてVビツト信号の挿入、もう一方
の8ビツトシフトレジスタにてBビツト信号の挿
入を行つていた。 Conventionally, this type of B8ZS encoding circuit first sorts an input data string into + polarity or - polarity, and then has two 8-bit shift register circuits to detect continuous 0 signals in the data string, and one An 8-bit shift register was used to insert a V-bit signal, and the other 8-bit shift register was used to insert a B-bit signal.
上述した従来の方式は、データ列内の0連続信
号の検出を各極性毎に行うので、8ビツトシフト
レジスタ及び0連続検出回路が増加し、回路規模
が増大し、消費電力も増大するという欠点があ
る。
The conventional method described above has the drawbacks of increasing the number of 8-bit shift registers and consecutive 0 detection circuits, increasing the circuit scale and power consumption, since the detection of continuous 0 signals in the data string is performed for each polarity. There is.
本発明の目的は、上述した欠点を除去し、簡単
な回路構成で消費電力の少ないB8ZS符号化回路
を提供することにある。 An object of the present invention is to eliminate the above-mentioned drawbacks and provide a B8ZS encoding circuit with a simple circuit configuration and low power consumption.
本発明によれば、入力データ列をB8ZS符号則
に従つて、符号化するB8ZS符号化回路において、
前記入力データ列を受ける8ビツトシフトレジス
タと、該8ビツトシフトレジスタの各段の出力を
基に、前記入力データ列に含まれる、8個の0連
続からなるブロツクを検出し、かつ前記B8ZS符
号則に従つて論理“1”のバイポーラ則パルスB
及び論理“1”のバイポーラ則違反パルスVを前
記シフトレジスタの所定の段に挿入し、該シフト
レジスタの最終段から変形信号“000VB0VB”
を出力させる検出回路と、該検出回路が8個の0
連続からなるブロツクを検出した時、前記変形信
号“000VB0VB”の内の“0VB0VB”信号の極
性振分けを行う期間を決定する極性振分け期間決
定回路(例えば、計数6のカウンタ)と、該極性
振分け期間決定回路で決定された期間、前記変形
信号“000VB0VB”の内の“0VB0VB”信号の
極性振分けを行う極性振分け回路とを、有するこ
とを特徴とするB8ZS符号化回路が得られる。
According to the present invention, in a B8ZS encoding circuit that encodes an input data string according to the B8ZS coding rule,
Based on the 8-bit shift register that receives the input data string and the output of each stage of the 8-bit shift register, a block consisting of 8 consecutive 0s included in the input data string is detected, and the block consisting of 8 consecutive 0s is detected, and Bipolar law pulse B of logic “1” according to the law
and a bipolar rule violation pulse V of logic "1" is inserted into a predetermined stage of the shift register, and a modified signal "000VB0VB" is output from the final stage of the shift register.
A detection circuit that outputs 0, and a detection circuit that outputs 8 0s.
A polarity distribution period determining circuit (e.g., a counter with a count of 6) that determines the period during which the polarity distribution of the "0VB0VB" signal of the modified signal "000VB0VB" is performed when a block consisting of a continuation is detected; A B8ZS encoding circuit is obtained, comprising a polarity distribution circuit that distributes the polarity of the "0VB0VB" signal of the modified signal "000VB0VB" during the period determined by the determination circuit.
即ち、本発明は、一つの8ビツトシフトレジス
タにより、データ列内の0連続信号を検出し、デ
ータ列内にVビツト信号、Bビツト信号の挿入を
行い、該Vビツト信号及び該Bビツト信号の極性
の振分けを制御するために計数6の簡単なカウン
タを有している。 That is, in the present invention, one 8-bit shift register detects a continuous 0 signal in a data string, inserts a V bit signal and a B bit signal into the data string, and inserts the V bit signal and the B bit signal into the data string. It has a simple counter with a count of 6 to control the polarity distribution.
次に、本発明の実施例について図面を参照して
説明する。
Next, embodiments of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例によるB8ZS符号化
回路である。本符号化回路は、8ビツトシフトレ
ジスタ回路1と、8個の0連続信号を検出する検
出回路2と、計数6のカウンタ回路3と、極性振
分け回路4とを含む。 FIG. 1 shows a B8ZS encoding circuit according to an embodiment of the present invention. This encoding circuit includes an 8-bit shift register circuit 1, a detection circuit 2 for detecting eight continuous 0 signals, a counter circuit 3 with a count of 6, and a polarity distribution circuit 4.
第2図はオールゼロ入力時の本実施例の動作タ
イムチヤートを示している。 FIG. 2 shows an operation time chart of this embodiment when all zero inputs are made.
以下、第2図をも参照して、本実施例の動作を
説明する。初めに8ビツトシフトレジスタ1に入
力されたデータ101は、クロツク102によ
り、8ビツトシフトされ、その出力が103,1
04,105,106,107,108,10
9,110に現われ、データ列の0連続検出回路
2に入力される。例えば、データ列内に8個の0
連続が存在したとすると、信号201にそれを検
出した信号が出力され、その信号201により、
8ビツトシフトレジスタの2段、5段と3段、6
段の入力を強制的に“1”にし、データ列内にV
ビツト、Bビツトを挿入する。更に信号201に
より計数6のカウンタ31をリセツトし、301
を“1”にする。これにより出力302は“0”
となり、NAND回路41は禁止され、NAND回
路42よりクロツク102が選択され、2分周回
路43により、8ビツトシフトされたデータ列1
10の極性振分けが行われ、401,402に出
力される。 The operation of this embodiment will be described below with reference to FIG. 2 as well. The data 101 initially input to the 8-bit shift register 1 is shifted by 8 bits by the clock 102, and the output is 103, 1.
04,105,106,107,108,10
9 and 110, and is input to the data string continuous 0 detection circuit 2. For example, if there are 8 0's in the data string
If continuity exists, a signal that detects it is output as signal 201, and that signal 201 provides
2-stage, 5-stage, 3-stage, and 6-stage 8-bit shift register
The input of the stage is forcibly set to “1”, and the V
Insert bit, B bit. Furthermore, the counter 31 of count 6 is reset by the signal 201, and 301
Set to “1”. This causes the output 302 to be “0”
Therefore, the NAND circuit 41 is prohibited, the clock 102 is selected from the NAND circuit 42, and the data string 1 shifted by 8 bits is generated by the divide-by-2 circuit 43.
10 polarity distributions are performed and output to 401 and 402.
次に、例えば、8個の0連続信号の後に8個の
0連続を含まないデータ列が101に入力したと
すると、カウンタ31が6個のクロツクを計数し
た後、301に“0”を出力し、カウンタ回路3
の入力クロツクを禁止する。0連続検出回路2の
出力201は8個の0連続信号を含まないデータ
列が入力するため、リセツト信号は発生せず、3
02には“1”が出力され、極性振分け回路4は
110のデータ列により決定され、振分けられた
データは401,402に出力される。 Next, for example, if a data string that does not include 8 consecutive 0's is input to 101 after 8 consecutive 0 signals, the counter 31 will output "0" to 301 after counting 6 clocks. and counter circuit 3
input clock is prohibited. Since the output 201 of the 0 consecutive detection circuit 2 receives a data string that does not include 8 consecutive 0 signals, no reset signal is generated and 3
"1" is output to 02, the polarity distribution circuit 4 is determined by the data string 110, and the distributed data is output to 401 and 402.
以上説明したように本発明は、8ビツトシフト
レジスタを1回路のみとし、8個の0連続信号が
入力した時、Vビツト信号、Bビツト信号の極性
振分けを、例えば、計数6の簡単なカウンタ回路
のような極性振分け期間決定回路で決定された期
間、“OVBOVB”の信号の初めのVと最後のB
が同極性、初めのBと二番目のVが同極性となる
ように極性振分け回路により行うことにより、回
路規模の削減及び消費電力の削減ができる効果が
ある。
As explained above, the present invention uses only one circuit of the 8-bit shift register, and when eight continuous 0 signals are input, the polarity distribution of the V bit signal and the B bit signal can be done using a simple counter with a count of 6, for example. During the period determined by the polarity distribution period determination circuit such as a circuit, the first V and the last B of the “OVBOVB” signal
By using a polarity distribution circuit so that the first B and the second V have the same polarity, the circuit size and power consumption can be reduced.
第1図は本発明の一実施例を示すブロツク図、
第2図はオールゼロ入力時の第1図の回路の動作
タイムチヤート、第3図はB8ZS符号則を示した
図である。
1は8ビツトシフトレジスタ、2は8個の0連
続の検出回路、3は計数6のカウンタ回路、4は
データ列の極性振分け回路、101はデータ列入
力、102はクロツク入力、103,104,1
05,106,107,108,109,110
はシフトレジスタ1段目から8段目までの各出
力、201は8個の0連続検出回路の出力、30
1,302は計数6をカウントしたことを示す信
号、401,402は各極性に振分けられたデー
タ列、41,42はNAND回路、43はフリツ
プフロツプ回路。
FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is an operation time chart of the circuit of FIG. 1 when all zeros are input, and FIG. 3 is a diagram showing the B8ZS code rule. 1 is an 8-bit shift register, 2 is a detection circuit for 8 consecutive 0s, 3 is a counter circuit with a count of 6, 4 is a data string polarity distribution circuit, 101 is a data string input, 102 is a clock input, 103, 104, 1
05, 106, 107, 108, 109, 110
are the outputs of the first to eighth stages of the shift register, 201 is the output of eight continuous 0 detection circuits, and 30
1, 302 is a signal indicating that a count of 6 has been counted; 401, 402 are data strings distributed to each polarity; 41, 42 are NAND circuits; and 43 is a flip-flop circuit.
Claims (1)
化するB8ZS符号化回路において、前記入力デー
タ列を受ける8ビツトシフトレジスタと、該8ビ
ツトシフトレジスタの各段の出力を基に、前記入
力データ列に含まれる、8個の0連続からなるブ
ロツクを検出し、かつ前記B8ZS符号則に従つて
論理“1”のバイポーラ則パルスB及び論理
“1”のバイポーラ則違反パルスVを前記シフト
レジスタの所定の段に挿入し、該シフトレジスタ
の最終段から変形信号“000VB0VB”を出力さ
せる検出回路と、該検出回路が8個の0連続から
なるブロツクを検出した時、前記変形信号
“000VB0VB”の内の“0VB0VB”信号の極性振
分けを行う期間を決定する極性振分け期間決定回
路と、該極性振分け期間決定回路で決定された期
間、前記変形信号“000VB0VB”の内の
“0VB0VB”信号の極性振分けを行う極性振分け
回路とを、有することを特徴とするB8ZS符号化
回路。1 In a B8ZS encoding circuit that encodes an input data string according to the B8ZS coding rule, an 8-bit shift register that receives the input data string and the output of each stage of the 8-bit shift register are used to encode the input data. A block consisting of eight consecutive 0s included in the column is detected, and a bipolar law pulse B of logic "1" and a bipolar law violation pulse V of logic "1" are sent to the shift register according to the B8ZS code rule. A detection circuit is inserted into a predetermined stage and outputs a modified signal "000VB0VB" from the final stage of the shift register. When the detection circuit detects a block consisting of eight consecutive 0s, the modified signal "000VB0VB" is output. A polarity distribution period determining circuit that determines the period for polarity distribution of the "0VB0VB" signal in the modified signal "0VB0VB" of the modified signal "000VB0VB" during the period determined by the polarity distribution period determination circuit. A B8ZS encoding circuit characterized by having a polarity distribution circuit that performs the following.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28577685A JPS62145932A (en) | 1985-12-20 | 1985-12-20 | B8zs coding circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28577685A JPS62145932A (en) | 1985-12-20 | 1985-12-20 | B8zs coding circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62145932A JPS62145932A (en) | 1987-06-30 |
JPH0332248B2 true JPH0332248B2 (en) | 1991-05-10 |
Family
ID=17695916
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28577685A Granted JPS62145932A (en) | 1985-12-20 | 1985-12-20 | B8zs coding circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62145932A (en) |
-
1985
- 1985-12-20 JP JP28577685A patent/JPS62145932A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS62145932A (en) | 1987-06-30 |
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