JPH0332248B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a B8ZS encoding circuit that extracts a block of eight consecutive zeros from a bipolar code string and replaces it with a special code pattern prepared separately.

[Conventional technology]

Figure 3 shows the conversion rules for B8ZS codes. In the figure, B represents a bipolar law pulse (a pulse with the opposite polarity to the previous pulse), V represents a bipolar rule violation pulse (a pulse with the same polarity as the previous pulse), and 0 represents a zero pulse.

Conventionally, this type of B8ZS encoding circuit first sorts an input data string into + polarity or - polarity, and then has two 8-bit shift register circuits to detect continuous 0 signals in the data string, and one An 8-bit shift register was used to insert a V-bit signal, and the other 8-bit shift register was used to insert a B-bit signal.

[Problem that the invention seeks to solve]

The conventional method described above has the drawbacks of increasing the number of 8-bit shift registers and consecutive 0 detection circuits, increasing the circuit scale and power consumption, since the detection of continuous 0 signals in the data string is performed for each polarity. There is.

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a B8ZS encoding circuit with a simple circuit configuration and low power consumption.

[Means for solving problems]

According to the present invention, in a B8ZS encoding circuit that encodes an input data string according to the B8ZS coding rule,
Based on the 8-bit shift register that receives the input data string and the output of each stage of the 8-bit shift register, a block consisting of 8 consecutive 0s included in the input data string is detected, and the block consisting of 8 consecutive 0s is detected, and Bipolar law pulse B of logic “1” according to the law
and a bipolar rule violation pulse V of logic "1" is inserted into a predetermined stage of the shift register, and a modified signal "000VB0VB" is output from the final stage of the shift register.
A detection circuit that outputs 0, and a detection circuit that outputs 8 0s.
A polarity distribution period determining circuit (e.g., a counter with a count of 6) that determines the period during which the polarity distribution of the "0VB0VB" signal of the modified signal "000VB0VB" is performed when a block consisting of a continuation is detected; A B8ZS encoding circuit is obtained, comprising a polarity distribution circuit that distributes the polarity of the "0VB0VB" signal of the modified signal "000VB0VB" during the period determined by the determination circuit.

That is, in the present invention, one 8-bit shift register detects a continuous 0 signal in a data string, inserts a V bit signal and a B bit signal into the data string, and inserts the V bit signal and the B bit signal into the data string. It has a simple counter with a count of 6 to control the polarity distribution.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a B8ZS encoding circuit according to an embodiment of the present invention. This encoding circuit includes an 8-bit shift register circuit 1, a detection circuit 2 for detecting eight continuous 0 signals, a counter circuit 3 with a count of 6, and a polarity distribution circuit 4.

FIG. 2 shows an operation time chart of this embodiment when all zero inputs are made.

The operation of this embodiment will be described below with reference to FIG. 2 as well. The data 101 initially input to the 8-bit shift register 1 is shifted by 8 bits by the clock 102, and the output is 103, 1.
04,105,106,107,108,10
9 and 110, and is input to the data string continuous 0 detection circuit 2. For example, if there are 8 0's in the data string
If continuity exists, a signal that detects it is output as signal 201, and that signal 201 provides
2-stage, 5-stage, 3-stage, and 6-stage 8-bit shift register
The input of the stage is forcibly set to “1”, and the V
Insert bit, B bit. Furthermore, the counter 31 of count 6 is reset by the signal 201, and 301
Set to “1”. This causes the output 302 to be “0”
Therefore, the NAND circuit 41 is prohibited, the clock 102 is selected from the NAND circuit 42, and the data string 1 shifted by 8 bits is generated by the divide-by-2 circuit 43.
10 polarity distributions are performed and output to 401 and 402.

Next, for example, if a data string that does not include 8 consecutive 0's is input to 101 after 8 consecutive 0 signals, the counter 31 will output "0" to 301 after counting 6 clocks. and counter circuit 3
input clock is prohibited. Since the output 201 of the 0 consecutive detection circuit 2 receives a data string that does not include 8 consecutive 0 signals, no reset signal is generated and 3
"1" is output to 02, the polarity distribution circuit 4 is determined by the data string 110, and the distributed data is output to 401 and 402.

〔Effect of the invention〕

As explained above, the present invention uses only one circuit of the 8-bit shift register, and when eight continuous 0 signals are input, the polarity distribution of the V bit signal and the B bit signal can be done using a simple counter with a count of 6, for example. During the period determined by the polarity distribution period determination circuit such as a circuit, the first V and the last B of the “OVBOVB” signal
By using a polarity distribution circuit so that the first B and the second V have the same polarity, the circuit size and power consumption can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is an operation time chart of the circuit of FIG. 1 when all zeros are input, and FIG. 3 is a diagram showing the B8ZS code rule. 1 is an 8-bit shift register, 2 is a detection circuit for 8 consecutive 0s, 3 is a counter circuit with a count of 6, 4 is a data string polarity distribution circuit, 101 is a data string input, 102 is a clock input, 103, 104, 1
05, 106, 107, 108, 109, 110
are the outputs of the first to eighth stages of the shift register, 201 is the output of eight continuous 0 detection circuits, and 30
1, 302 is a signal indicating that a count of 6 has been counted; 401, 402 are data strings distributed to each polarity; 41, 42 are NAND circuits; and 43 is a flip-flop circuit.

Claims (1)

[Claims] 1 In a B8ZS encoding circuit that encodes an input data string according to the B8ZS coding rule, an 8-bit shift register that receives the input data string and the output of each stage of the 8-bit shift register are used to encode the input data. A block consisting of eight consecutive 0s included in the column is detected, and a bipolar law pulse B of logic "1" and a bipolar law violation pulse V of logic "1" are sent to the shift register according to the B8ZS code rule. A detection circuit is inserted into a predetermined stage and outputs a modified signal "000VB0VB" from the final stage of the shift register. When the detection circuit detects a block consisting of eight consecutive 0s, the modified signal "000VB0VB" is output. A polarity distribution period determining circuit that determines the period for polarity distribution of the "0VB0VB" signal in the modified signal "0VB0VB" of the modified signal "000VB0VB" during the period determined by the polarity distribution period determination circuit. A B8ZS encoding circuit characterized by having a polarity distribution circuit that performs the following.