JPH0332219A - Phase modulation circuit - Google Patents

Abstract

PURPOSE:To decrease the circuit scale and to reduce the power consumption by allowing a differential pair providing phase information with a modulation signal input with respect to a clock provided with tilted fall to read a pulse at the time of turning on input main data to be set and to latch such a pulse at the time of turning off state is used in common, and outputting a phase modulation signal externally. CONSTITUTION:A differential pair 2 comprising 2 TRs Q5 and Q6 is used to provide phase information while varying the leading position from a tilted clock CK1 whole trailing is tilted. Then a pulse when an input high speed main data D is set is read simultaneously and the on-pulse is latched when the data is reset to apply phase modulation to the main data D. Thus, a level shift circuit which shifts a DC level of an input clock CK2M to the differential pairs Q5, Q6 to a proper value so that the waveform of the clocks CK3M1, CK3M2 having input phase information is not overlapped with the waveform of the input main data D when phase modulation is applied to the main data D is not required. Thus, the circuit scale is decreased and the power consumption is less.

Description

DETAILED DESCRIPTION OF THE INVENTION (Summary) The submarine cable repeater transmits the input high-speed pulse on/off main data D, which is used as a response signal etc. in response to commands from the land station, by low-speed general transmission. To provide a phase modulation circuit with a small circuit scale and low power consumption, regarding a phase modulation circuit that changes the pulse position of the main data by changing the falling position of the clock of the main data D by the modulation signal port of the sub data of a wave burst. For the purpose of is input to one transistor 06, the modulation signal H is input to the other transistor 05, and a constant current I7 is input.
The clock CK, which is differentially driven and given the falling slope, changes the falling position from the slope to have phase information, and inputs the main data D and an appropriate DC potential vl. A reading differential pair 3 consisting of two transistors Q, Q2 that read the on-time pulse of the main data, and two transistors Q that hold the on-time pulse when off.
3. ' [1, two transistors 0゜Q6 that supply a clock with phase information to the holding differential pair 4 consisting of
and a transistor 08.0□ driven by a constant current source 19+rl+ to change the potential of each output of the differential pair 3 for reading. and the holding potential applying unit 5 which determines the input potential of the holding differential pair 4 by shifting the holding potential applying unit 5, and the phase-modulated data D output from the reading and holding differential pairs 3 and 4.

With respect to utl, the potential is shifted as necessary by the transistor QI2 driven by the constant current source Il, and a phase modulation signal is generated. a clock CK which is provided with an output section 6 that outputs at, and whose falling slope is given a slope of 4-J by the falling slope applying section;
The differential pair 2, which has phase information at the modulation signal input -, also reads the on-time pulse of the input main data D and holds the on-time pulse when it is off. Signal. Configure to output ut.

[Industrial application field]

The present invention adds low-speed burst wave sub-data to high-speed on/off main data, which is used, for example, as a response signal for a submarine cable communication repeater to respond to a control command from a land-based monitoring station. This article relates to a phase modulation circuit to be mounted.

[Conventional technique]

A conventional phase modulation circuit inputs main data D of high-speed on/off pulses of, for example, 800 Mb/s, and
The lower part of the side data of the slow carrier burst of Kb/s (b
), the input clock CK of main data D of 800 Mb/s is input to the base of the transistor 0□ whose collector is common, and its emitter is connected to the collector of the constant current source transistor [115]. By charging and discharging the capacitor C between the emitter of Q10 and the ground, the constant current 115 determined by the appropriate DC potential V applied to the base and the resistor RI'S between the emitter and the power supply VEE is applied to the falling edge of the input clock CK. Add a slope. The clock CK, whose falling edge is sloped, is connected to the base of one of the transistors QI6 of the differential pair 0□61ro17, whose respective collectors are grounded by resistors R16 and R, and whose emitters are directly connected. On the other hand, the modulation signal N of the sub-data of the low-speed carrier wave burst of 26 Kb/s is input to the base of Q17, and the collector thereof is connected to the painter bit of differential pair 16+QL7 for constant current source. Appropriate DC potential V given to its base by transistor QIO
4 and the constant current determined by the resistor RIB between its emitter and power supply V4? Driven by Ti, II8. Then, the falling position of the slope of the clock CL, which has been given a slope, is changed by the modulation signal input N, and phase information is applied to both ends of the resistor RL between the collector of the other transistor 17 and the ground. Outputs clock CK12. The clock CKIM with this phase information is the transistor 5. The DC potential is input to the base of the constant current source transistor 0□. A transistor Q19 is driven by a constant current +20 determined by an appropriate DC potential V4 applied to the base of the emitter and a resistor R20 between the emitter and the power source VEE, and a transistor Q21 is driven by a constant current I23 of a constant current source transistor 0°. The diode-connected transistor 022 converts the DC potential to each electrode voltage V I
The IEs are sequentially shifted and a clock CK2M shifted to a necessary potential and given phase information is output.

The clock CK2M is shown in the upper part (a) of Fig. DA.

A differential pair of two transistors 0s, Oh is supplied to the base of one transistor 05, and the other transistor 0
By applying an appropriate DC potential v2 to the base of the constant current source transistor 07, the DC potential ν3 of the base of the constant current source transistor 07 and the emitter
Modulation clocks CK3M1 . Outputs CR2)+2. Then, the differential pair [1s, one transistor 0. In a differential pair of two transistors 01 and 0□, both emitters of which are connected to the collectors of the transistors 01 and 0□, whose respective collectors are connected to the resistor R+ and the resistor R2, one of the transistors 0□ of the differential pair Apply an appropriate DC potential v1 to the base of the other transistor 0. The on-time pulse of high-speed main data D input to the base of is read. At this time, both workers ξ
The DC potential is determined so that the upper part of the clock (J3□) supplied to the output terminal and the lower part of the main data D input to the base of the transistor 0□ do not overlap in waveform.Then, the differential pair Q9.Q.

A differential pair of two transistors 013.04 whose pinpoints are connected to the collector of the other transistor 05 is,
The clock CK3H2 holds the on pulse when the main data 0 is off. and a differential pair for retention. 304, each collector on the output side of the reading differential pair 01o2 is connected to the DC potential ν3 of the base of each transistor 09+QI+, and each resistor Rq=
A constant current determined by R++ is connected to each base of a common collector transistor o8□QIO driven by Iz, and the base potential is 0°, o,. Only the V anus is shuffled l-
The pulse of the main data D when it is off is held. Then, I ordered the differential pair 01 for reading, and the resistor R2 between the collector of the transistor 02 and the ground.
Data DM obtained by phase modulating the main data D with the modulation signal input
However, the constant current source transistor 0. , is input to the base of transistor 0.2 driven by constant current 113 from resistor R13, and its DC potential is input to the VE of transistor 01□.
The configuration is such that the phase modulation signal Dout is shifted by E and outputs the phase modulation signal Dout having the necessary DC potential.

After giving a falling slope to the clock CK of the 1-input main data D in the lower part (1)), it is given phase information by the modulation signal H of the burst wave of low-speed data, and is output as a clock CK2M with 5 phase information. A phase modulation signal is obtained by applying phase modulation using a circuit to perform phase modulation and a clock CK 2M having the phase information. Since the circuit is divided into two circuits, the circuit shown in the upper part (a) that outputs U, there is a problem that the circuit scale becomes large and the power consumption increases. An object of the present invention is to provide a phase modulation circuit with a small circuit scale and low power consumption.

- [Means for solving the problem] This problem consists of two transistors that operate differentially in order to provide phase information to the clock CK of the input main data D.
The differential pair 2 of 5 and 06 is connected to a clock C having the phase information.
Lt also has the function of applying phase modulation to the input main data D, and also serves as a clock CK with conventional phase information.
A potential shift circuit (transistors 019 to 0, 3) that shifts the DC potential of the clock CKIM so as not to overlap the waveform of the input main data D
By omitting the resistors RZo and RZ3), as shown in Figure 1, a falling slope is created by repeatedly charging and discharging the clock CM of the input main data using the constant current 115 and the capacitor C. The applying unit 1 and the clock CK whose falling edge has been given a slope are inputted to one transistor 06, and the modulation signal H is inputted to the other transistor 01, and the circuit is driven by a constant current +7 to generate a differential signal. If the falling position of the clock CK given the falling slope is changed from the slope part to have phase information, then the main data D and an appropriate DC potential vl are input, and when the main data is turned on, Two transistors reading pulses of 0.
A differential pair 3 for reading consisting of a 0° angle, and two transistors 05 . A differential pair 2 consisting of two transistors 05 and 06 that supplies a clock having phase information to a holding differential pair 4 consisting of a
The DC potential of each output of the differential pair 3 for reading is connected to a transistor []e, which is driven by a constant current source 19+ II +.
[]+. and the holding potential applying unit 5 which determines the input potential of the holding differential pair 4 by shifting the holding potential applying unit 5, and the phase-modulated data D output from the reading and holding differential pairs 3 and 4. utl
The transistor 052 driven by the constant current source 113
The potential is shifted as necessary and the phase modulation signal is output externally. , and a differential pair 2 that provides phase information at the modulation signal input to the clock CL to which the falling slope is applied to the falling slope by the falling slope applying unit 1. This is solved by the present invention, which also reads the on-time pulse of the main data D and holds the on-time pulse when it is off, and outputs a phase modulation signal.

In the principle diagram of FIG. 1 showing the basic configuration of the phase modulation circuit of the present invention, 1 is a constant current II with respect to the input main data clock GK.
5 and a capacitor C to repeat charging and discharging to give a slope to the falling edge.

2 inputs the clock CK whose falling edge is sloped around 1 to one transistor 06, and the other transistor 06.
5, the modulation signal is inputted to the clock CK, which is driven by a constant current I7 and is differentially given the falling slope. Two transistors 0.0 and 0.0, which input the main data D and an appropriate DC potential vI, and read the pulse when the main data is turned on.
A differential pair 3 for reading consisting of 0□, and two transistor pairs 3 that hold the on-time pulse when off. Clock CK with phase information in differential pair 4 for holding consisting of n4
,,, two transistors 3 supplying CK 2,
This is a differential pair consisting of 06.

Reference numeral 3 designates a reading differential pair consisting of two transistors 0+, (h) which input the main data D and an appropriate DC potential V and read the on-time pulse of the main data.

4 are two transistors 3.4 that hold the pulse when the input main data D is turned off when it is turned on. (This is a holding differential pair consisting of 1.

5 is a transistor 05.5 driven by a constant current source +9+r+1 to change the DC potential of each output of the differential pair 3 for reading. mouth,
.

This is a holding potential applying section that determines the input potential of the holding differential pair 4 by shifting the holding potentials respectively.

Reference numeral 6 denotes phase-modulated data D output by the reading and holding differential pair 3.4, which is supplied with a necessary potential from the holding potential applying unit 5. This is an output section that shifts the potential by a necessary amount by a transistor 05□ driven by a constant current source 113 with respect to all, and outputs a phase modulation signal D out to the outside.

7 is a constant current source that outputs a constant current +15 by applying an appropriate DC potential V, and a constant current source r7.7 which applies an appropriate DC potential v2 in common. '19.11□, 11. This is a constant current source section consisting of constant current sources that individually output .

[Effect]

The phase modulation circuit of the present invention has two transistors.
．． A differential pair 2 consisting of a transistor Q is connected to the base of one of the transistors Q6 by a clock C, which is obtained by adding a slope to the falling edge of the clock CK of the input main data D by a falling slope adding section 1.
A low-speed burst wave data modulation signal N is input to the base of the other transistor 05, and the signal is differentially driven by the constant current 7 from the constant current source 7. The falling position of the clock CK+ from the slope part is changed to have phase information on the clock CK+, which is given a downward slope, and the clocks CKs+ and CKM2 having the phase information are respectively transferred to a reading circuit consisting of two transistors [11 and 2]. Differential pair 3 and 2
transistor Q3. 'A4 is supplied to the holding differential pair 4. The differential pair 3 for reading inputs the main data D and an appropriate DC potential vl and reads the pulse when the main data is on, and the differential pair 4 for holding reads the pulse when the main data is on when the main data is off. hold.

That is, two transistors 05. A differential pair 2 consisting of Qb is a clock (J) whose falling edge is sloped.

It is used to change the fall position from the slope and provide phase information, and at the same time reads the on-time pulse of the input high-speed main data log and holds the on-time pulse when off. It is also used to apply +l'l modulation to the main data. Therefore, when applying phase modulation to the conventional main data log, the clock CK3□ with input phase information,
The input clock CM 2M of the differential pair 0°0 is set so that the waveform of CKz+z does not overlap the waveform of the input main data row.
Potential shift circuit (transistors 0□, ~0□3 and resistors Rho, R) to shift the DC potential of
23) is no longer necessary, the phase modulation circuit of the present invention has a small circuit scale and low power consumption, thus solving the problem.

〔Example〕

FIG. 2 is a circuit diagram showing the configuration of a phase modulation circuit according to an embodiment of the present invention, and FIG. 3 is a waveform diagram for explaining its operation.

In the circuit diagram of FIG. 2, the falling slope imparting unit 1 includes an NPN transistor whose collector is grounded, inputs a signal to the base, and outputs it from the emitter 5;
It consists of a capacitor C between the emitter of a transistor QI4 and ground, and the transistor 0. Based on the base of (
2) Input the clock CK of a high-speed main data register such as the clock GK, the emitter of which is connected to the collector of the transistor register 15 of the constant current source section 7, and the resistor RI5 between the emitter of 0.5 and the power supply V□. A constant current r is obtained by applying a suitable DC potential ν5 to the base of the transistor 01. Drive with constant current.

Then, the capacitor C between the 1 trillion ivy of the transistor I4 and the ground is charged and discharged, and the clock C of the input main data row is charged and discharged.
K (Figure 3) (2)) d, Figure 3 (7) (31CK,
As shown in (7), a slope is given to the fall.

2 differential pairs, 2 npn transistors 5. oh
The input main data clock GK is connected to the base of one of the transistors 06 and 1 and 1 is connected to the base of the transistor 06.
Enter the clock CK with a slope at the falling edge,
Inputting the low-speed burst wave data modulation signal M ((4) in FIG. 3) into the base of the other transistaro 5,
The clock C is driven differentially by the constant current I7 from the transistor 7 of the constant current source section 7 and is given the falling slope.
K, the falling position from the slope is changed as shown in (3), (4), and (5) in Fig. 3, and there is no phase information.

Then clocks with phase information (JM□, CKI2
A differential amplifier 3 for reading main data consisting of two transistors 011 and 2, and two transistors 3.
It is supplied to the holding differential pair 4 consisting of Q4.

The differential pair 3 for reading is connected to the main data row and an appropriate DC potential V,
is input to each base, and the clock CK with phase information supplied to the master data is read in the pulse when the main data is turned on, and the holding differential pair 4 is clock CK
M2 holds the pulse when the main data is on when it is off.

The differential pair 3 for reading and the differential pair 4 for holding generate phase modulated signals whose pulse positions change depending on the modulated signal input H, as shown in (6) o, , t in FIG. . , outputs.

The holding potential applying section 5 is an NPN transistor.

The collector potential of transistor 0□0° of differential pair 3 for reading and transistor 0□0Q4 of differential pair 4 for holding is connected to transistor 0.0 of constant current source section 7. The transistors 0□ and L are driven by the constant current ■7 of the transistor 01□ and the constant current I'l+ of the transistor 01□.

The transistor 3. of the holding differential pair 4 is shifted by 3. Input to the base of Q4 to determine the potential.

Output section. is composed of an npn transistaro I2, and is supplied with a necessary potential from the holding potential applying section 5 to output phase-modulated data D for reading and holding differential pairs 3 and 4. utl is input to its base, and the transistor [112 driven by the constant current 113 of the transistor 0□0 of the constant current source section 7 shifts the DC potential as necessary.
Then, the phase modulation signal is sent to the outside. Output ut.

With the above operation, the phase modulation circuit of the embodiment shown in FIG.
2 Transistaro 5. The differential pair 2 consisting of Oh
It is used to change the falling position of the clock CK, which has been given a slope at the falling edge by the falling slope applying section 1, and to give it phase information. It is also used to read the pulse at the time, hold the pulse at the time of on when it is off, and apply phase modulation to the main data D, so the phase modulation is applied to the main data D of the conventional example in Fig. 4. At the same time, the differential pair Q9. A potential shift circuit (transistors Q19-0□3 and resistor R2) shifts the DC potential of the input clock C1hM of Q to an appropriate value.
゜.

Since R23) is not required, the phase modulation circuit has a small circuit scale and low power consumption, so there is no problem.

[Effects of the Invention] As explained above, according to the present invention, the circuit scale is smaller and the power consumption can be reduced compared to the conventional example.
This has the effect of making it easier to integrate the phase modulation circuit into an IC.

[Brief explanation of drawings]

FIG. 1 is a principle diagram showing the basic configuration of a phase modulation circuit according to the present invention, FIG. 2 is a circuit diagram showing the configuration of a phase modulation circuit according to an embodiment of the present invention, and FIG. 3 is a diagram showing the operation of an embodiment of the present invention. A waveform diagram for explanation. FIG. 4 is a circuit diagram of a conventional phase modulation circuit. In the figure, (2) is a falling slope applying section, 2 is a differential pair, 3 is a differential pair for reading, 4 is a differential pair for holding, 5 is a holding potential applying section, 6 is an output section, and 7 is a differential pair for reading. This is a constant current source.

Claims (1)

[Claims] The pulse position of the main data (D) of the high-speed on/off pulse is changed by changing the falling position of the clock pulse of the main data (D) using the modulation signal (M) of the sub-data of the low-speed carrier wave burst. A phase modulation circuit that changes
A constant current (I_1_
5) and a falling slope imparting unit (1) that repeatedly charges and discharges using a capacitor (C) to give a slope to the falling edge, and a clock (CK_1) whose falling edge is given a slope to one transistor (Q_6). and the other transistor (Q_
5), input the modulation signal (M) to the constant current (I_7
), the clock (CK_1) is differentially driven and given the falling slope, and the falling position from the slope part is changed to have phase information, and the main data (D) and the appropriate DC potential (V_1 ) and reads the on-time pulse of the main data (Q_1, Q_2), and the two transistors that hold the on-time pulse when off. A differential pair (2) consisting of two transistors (Q_5, Q_6) that supplies a clock (CK_M_1, CK_M_2) with phase information to a holding differential pair (4) consisting of (Q_3, Q_4); The potential of each output of the differential pair (3) for reading is set by a constant current source (
Transistor (Q_9, I_1_1) driven by
8, Q_1_0) to shift the holding differential pair (
4) and a constant current source ( transistor (Q_1_2) driven by transistor (I_1_3)
) for shifting the potential by a necessary amount and outputting a phase modulation signal (D_o_u_t) to the outside,
A differential pair (2) that imparts phase information at the modulation signal input (M) to the clock (CK_1) whose falling edge has been sloped by the falling slope applying unit (1) converts the input main data ( D
1. A phase modulation circuit characterized in that it is also used to read pulses when the circuit is turned on and hold the pulses when the circuit is turned off.