JPH0332160B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a search circuit for a failure analysis memory of a semiconductor testing device.

(Prior art) In semiconductor test equipment, defective repair of a device under test (for example, a memory IC) is performed (replacing a defective line in a memory cell array with a spare line).
As a means of performing this, the test results stored in the failure analysis memory are read out, and failure analysis is performed, such as searching for defective addresses, counting the number of defective addresses, and counting the number of defective cells of interest in the bit configuration of the memory under test. Do this. However, in the past, failure analysis was performed on defective addresses and defective cells as described above, but when there are consecutive defects, the search stops every time a defect is detected, so the analysis is difficult. The drawback was that it took a long time to process.

Note that the bit configuration of the device under test refers to the configuration of the number of bits of the I/O (input/output terminal) of the memory. For example, in the case of 4KW/4BIT, the memory in this example has a 4BIT configuration.

(Problems to be Solved by the Invention) The present invention was made in order to solve the above-mentioned disadvantage that the analysis process of the device under test (memory under test) takes time, and it reduces the processing time when analyzing failures. The aim is to

[Structure of the Invention] (Means and Effects for Solving Problems) The present invention provides a failure analysis memory for extracting the contents of test results of a device under test, and a failure analysis memory for determining whether or not to invert the output polarity from the memory. It is characterized by comprising a control means, a polarity inversion circuit for inverting the output from the failure analysis memory according to the control means, and a means for detecting the quality of the device under test from the output of the polarity inversion circuit. do. That is, when failures occur continuously, the normal side is detected by the polarity inversion circuit. This aims to shorten the processing time during failure analysis.

(Example) An example of the present invention will be described below with reference to the drawings. FIG. 1 is an overall configuration diagram of the same embodiment. The failure analysis memory 1 takes in the test results of the device under test in response to an address input, and outputs the read out test results as failure analysis data. The register circuit 2 determines whether or not to invert the output polarity of the failure analysis memory 1. The polarity inversion circuit 3 inverts the output polarity of the failure analysis memory 1 according to the output of the register circuit 2. Note that when the register circuit 2 is not operated, the polarity inverting circuit 3 does not invert the output polarity of the failure analysis memory 1 and outputs the output with the same polarity. The gate circuit 4 performs an AND operation on the strobe pulse S and shapes the waveform. The defective address detection circuit 5 is
A defective address is detected by the output from the gate circuit 4. Note that when the output polarity of the polarity inversion circuit 3 is inverted, a normal address is detected. The defect number counting circuit 6 counts the number of defective addresses and the number of defective cells of interest in the bit configuration of the device under test (memory) based on the output from the gate circuit 4. Note that when the output polarity of the polarity inversion circuit 3 is inverted, the number of normal addresses and the number of cells are counted.

FIG. 2 shows a specific example of the vicinity of the polarity inversion circuit shown in FIG. In this case, the bit configuration of the device under test is n
+1, and the output from the failure analysis memory B ₀ ~ _{B o}
each becomes one input of AND gates 7 ₀ to 7 _o . The outputs O ₀ to _{O o} of the register circuit 8 are respectively
It becomes the other input of AND gates 7 ₀ to 7 _o . ₀ to _o of the register circuit 8 correspond to the total number of bits of the bit configuration of the device under test, and the output of the register circuit 8
_O.sub.0 to _O.sub.o are selected, any plurality of outputs thereof are set to logic "1" at the same time, and only the AND gate to which it is input allows the output from the failure analysis memory to pass. In this case, the polarity inversion circuit 3 is composed of an exclusive OR circuit, and one input of the polarity inversion circuit 3 is an exclusive OR circuit.
The wire OR outputs of the AND gates ₇₀ to _7o are supplied to the other input, and the output of the register circuit 2 is supplied to the other input.

In the above configuration, the failure analysis memory 1 has the same bit configuration as the memory under test and is accessed with a time delay, and the test result is written as "1" to the defective cell at the address where the defect occurred. Does nothing for normal cells. Thereafter, at another timing, the address of the failure analysis memory 1 is accessed, the contents are read out, and the contents are output to the polarity inversion circuit 3. The register circuit 2 is a register that determines whether or not to invert the polarity of the output from the failure analysis memory 1, and the output polarity of the polarity inversion circuit 3 is determined by the input signal from the register circuit 2. Since the output of the register circuit 2 is normally "0", normal detection is performed. That is, the output of the polarity inverting circuit 3 is "0" if it is good, and "1" if it is bad. The gate circuit 4 shapes the waveform using a strobe pulse S, and the output of the gate circuit 4 is output to a defective address detection circuit 5 and a defective number counting circuit 6. Defective address detection circuit 5
stops accessing the address of the failure analysis memory 1 in response to an input signal from the gate circuit 4, and by reading the address at that time, the failure address can be known.
The number of defects can be determined by counting the input signals from the

On the other hand, when the defects are continuous, by setting the output of the register circuit 2 to "1", the output polarity of the polarity reversing circuit 3 is changed when the output at point a is "0" (good product). It is reversed and the normal address side is detected. Therefore, since addresses other than normal addresses can be detected as defects, it is possible to shorten the time when defects occur continuously.

[Effects of the Invention] Conventionally, only defective addresses were detected and the number of defects was counted, but the present invention makes it possible to detect normal addresses and count the number of normal addresses by using a polarity inversion circuit. This makes it possible to shorten the failure analysis processing time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of a main part of the same structure. 1...Failure analysis memory, 2...Register circuit (control means), 3...
Polarity inversion circuit, 5... Defective address detection circuit, 6
...Defective number counting circuit.

Claims (1)

[Claims] 1 A failure analysis memory for extracting the contents of test results of a device under test, a control means for determining whether or not to invert the output polarity from the failure analysis memory, and a control means for controlling the output from the failure analysis memory according to the control means. 1. A search circuit for a failure analysis memory, comprising: a polarity inversion circuit for inverting polarity; and means for detecting the quality of the device under test based on the output of the polarity inversion circuit.