SU760194A1 - DYNAMIC RECORDING DEVICE WITH SELF-MONITOR - Google Patents

Description

The invention relates to techno-storage devices and can be used in automation devices and computing equipment containing semiconductor dynamic memory blocks (chips), in which the regeneration of information is combined with reading.

Known storage devices containing semiconductor dynamic memory blocks, bit part, decoder, selector, counter, address register, clock generator.

The disadvantage of these devices is the need to use test control, which is time-consuming, and in some cases, for example, when operating in real time, may be unacceptable.

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Also known are memory devices containing semiconductor dynamic memory blocks, bit part, control circuit, decoder, selector, counter,

address register, clock generator £ 1].

The disadvantage of these devices is the possibility of multi-bit errors in the read information during prolonged operation of the device

and uneven access to the storage device. These errors may not be detected by the control circuit.

The closest to the claimed is a storage device on semiconductor dynamic memory blocks (memory chips), in which the regeneration of information is combined with the reading of £ 2].

This device contains semiconductor dynamic memory blocks, informational inputs and outputs of which are connected to the digital buses through the bit part and control circuit inputs, sample inputs to the decoder outputs, regeneration inversion inputs to the counter outputs, and part of the address register outputs, inputs " which is connected to the address bus, the clock generator, the first outputs of which are connected to the strobe input of the decoder and the input of the memory block mode, the latter with the control input of the selector and with the counting input ohm meter, and input from the input control bus;

The disadvantage of the prototype is the possibility of not detecting the circuit

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The role of multi-bit errors in reading information that occurs when the device is operated for a long time and when it is irregularly accessed. For promotion. the reliability of the known device requires the organization of test control, which requires time-consuming, which in some cases may be unacceptable.

The aim of the proposed invention is to increase the reliability of the device by increasing the reliability of reading information.

This goal is achieved by the fact that the device contains additional selector and counter ^ the first inputs of the additional selector are connected to other outputs of the address register, the second inputs are from the outputs of the additional counter, the control input of the additional selector is connected to the control input of the main selector, some outputs are addressable the drive inputs, the other outputs are from the decoder inputs, the counting input of the additional counter is connected to the transfer output of the main counter.

The introduction of an additional counter and selector allows periodically, during regeneration, to read all the information from the storage device and monitor it. its correctness: as a result, the probability of the appearance of an error control circuit that is not detectable is reduced.

The drawing shows a diagram of a storage device.

. The storage device contains drives 1 on semiconductor memory elements, a numeric register 2, a control unit 3, a decoder 4, a main selector 5, a main counter 6, an address register 7, a clock generator 8, an additional selector 9, an additional counter 10. The outputs of the main selector 5 connected to the circulation inputs - regeneration of drives 1, - the outputs of the additional selector 9 - with address inputs and inputs of the decoder 4, the outputs of the decoder 4 - with the inputs of the drives selection. The inputs and outputs of the register number 2 are connected to the number lines 11, the input of the register 7 address is connected to the address 10

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12 buses, clock input with input control bus 13.

In the cycle of writing to the number bus 11, the code of the number being written is flipped; through the numeric register 2 55

arrives at information inputs of drives 1. From address buses 12, the address code goes to register 7 of the address, from it through selector 5 to inputs of regeneration-inversion of accumulators, and through selector 9 and decoder 4 to address inputs and input of select drives 1. Command “Record” via bus 13 goes to clock generator 8, which produces a pulse20

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sy write information in memory cells.

In the readout cycle, the 12 "address of the memory cells is supplied. The address part is similar to the write cycle. The bus 13 receives the" Read "command, the number read from the drives 1 through the numeric register 2 post * goes to the number buses 11 and the control unit 3, which determines the correctness of the read information.

After a time equal to the regeneration period, generator 8 generates a regeneration command, according to which the contents of counters 6 and 10 through selectors 5.9 and decoder 4 arrive at the address inputs and sample inputs of drives 1. The clock generator produces pulses that carry out the regeneration of one line drives at the address given by the first counter b. In this case, the information read at the address specified by the counters b and 10 is passed through the numeric register 2 to the control unit 3. Monitoring of read information is carried out. At the end of the regeneration cycle, generator 8 adds "1." To the contents of counter 6. During one period of regeneration, generator 8 starts 64 cycles of regeneration. At the same time, information is controlled in 64 memory cells. The width of the counter 10 is equal to N / 64 bits, where N is the number of words stored in the storage device (memory) .. The control of the entire contents of the memory is carried out in a time equal to where T _p is the period

regeneration (for ^ of the considered example T _p = 2 ms). Control of the entire contents of the memory with a capacity of 32 words is carried out in a time approximately equal to 1s.

Additional time spent on control is not required.

The proposed device allows for minor equipment costs (1 counter and 1 selector) to periodically monitor the entire contents of the memory. The frequency of the contra is less than a few seconds.

At the same time, the possibility of non-detectable error control schemes in the read information is practically excluded. The time required in the prototype for the implementation of testovogr control, the proposed device is missing.

Claims (1)

Claim Dynamic memory with self-control, containing drives on semiconductor memory elements, information inputs and outputs of which are connected to information buses and inputs of the control unit through the number register, inputs of drives selection are connected to the outputs of the decoder, and circulation or regeneration inputs through the main selector five 760194 b with the outputs of the main counter and one of the outputs of the address register whose inputs are connected to address buses, a clock generator, the first. outputs of which are connected to the gate of the decoder and the input of the drive mode, the second with the selector control input and the counter input of the counter, and the input of the clock generator connected to the input control bus, characterized in that, in order to improve the reliability of the device for 'θ by increasing the reliability of reading information, it contains an additional selector and counter, the first input The additional selector is connected to other outputs of the ad-15 register. rez, the second inputs - with the outputs of the additional counter, the control input of the additional selector is connected to the control input of the main selector / one outputs - with the address inputs of the accumulators, the other outputs with the inputs of the decoder, the count input of the additional counter is connected to the transfer output of the main counter.