JPH0332064A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0332064A JPH0332064A JP16759789A JP16759789A JPH0332064A JP H0332064 A JPH0332064 A JP H0332064A JP 16759789 A JP16759789 A JP 16759789A JP 16759789 A JP16759789 A JP 16759789A JP H0332064 A JPH0332064 A JP H0332064A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- diffusion layer
- source
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 abstract description 26
- 230000005684 electric field Effects 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000005036 potential barrier Methods 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は絶縁膜上に形成されたシリコン層に作られた
トランジスタにおいて、基板が電極と接地されないトラ
ンジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a transistor made of a silicon layer formed on an insulating film, in which the substrate is not grounded to an electrode.
第2図は従来の半導体装置を示す断面図で、図において
、(1)はシリコン基板、(2)はシリコン酸化膜、(
3)はシリコン層、0υ、■はそれぞれシリコン層(3
)内におけるドレイン拡散層、ソース拡散層である。@
υはドレイン電極、(6)はソース電極、(5)はゲー
ト電極、(6)はゲート酸化膜である。FIG. 2 is a cross-sectional view showing a conventional semiconductor device, in which (1) is a silicon substrate, (2) is a silicon oxide film, (
3) is a silicon layer, 0υ, ■ are silicon layers (3
) are the drain diffusion layer and source diffusion layer. @
υ is a drain electrode, (6) is a source electrode, (5) is a gate electrode, and (6) is a gate oxide film.
次に動作について説明する。ソース電極(6)を接地し
ゲート電極(5)に正の電圧を印加すると、ゲート酸化
膜(6)直下のシリコン層(3)表面では反転層が形成
される。この状態で、ドレイン電極(ハ)に正の電圧を
印加すると、ソースドレイン方向に沿って反転層内に電
位勾配ができ、ソース拡散層(2)より電子がドレイン
拡散rmC3υに流れる。このときのドレイン電圧−ド
レイン電流特性は第3図に示すようになる。ソース拡散
11図より流れ出た電子は、電位勾配によって加速され
、エネルギーが大きくなると、シリコン基板(3)内の
格子に衝突し、電子−正孔対を発生させ、エネルギーを
失う。これを衝突電離現象という。この衝突[離現象で
生じた電子はドレイン電界によって引き寄せられ、ドレ
イン拡散meX)に入りドレイン電流となる。一方、正
孔は吸収されるところがなく基板領域に蓄積される。ド
レイン拡散層近傍ではドレイン電界によって、正孔は追
いやられ、ソース拡散層□近傍に正孔が集まる。その結
果、ソースと基板間の電位障壁が小さくなり、ソースか
らより多くの電子が流れ出て、ドレイン電流は増加し、
第3図に示す第1キンクを生じる。ドレイン印加電圧が
さらに高くなるとこの現象が著しくなり、トランジスタ
がバイポーラ動作してしまう。これが第2キンクである
。Next, the operation will be explained. When the source electrode (6) is grounded and a positive voltage is applied to the gate electrode (5), an inversion layer is formed on the surface of the silicon layer (3) directly under the gate oxide film (6). In this state, when a positive voltage is applied to the drain electrode (c), a potential gradient is created in the inversion layer along the source-drain direction, and electrons flow from the source diffusion layer (2) to the drain diffusion rmC3υ. The drain voltage-drain current characteristics at this time are as shown in FIG. Electrons flowing out of the source diffusion diagram 11 are accelerated by the potential gradient, and when their energy increases, they collide with the lattice in the silicon substrate (3), generate electron-hole pairs, and lose energy. This phenomenon is called impact ionization phenomenon. The electrons generated by this collision [separation phenomenon] are attracted by the drain electric field and enter the drain diffusion meX), resulting in a drain current. On the other hand, holes have no place to be absorbed and are accumulated in the substrate region. In the vicinity of the drain diffusion layer, holes are driven away by the drain electric field, and holes gather in the vicinity of the source diffusion layer □. As a result, the potential barrier between the source and the substrate becomes smaller, more electrons flow out of the source, and the drain current increases,
A first kink shown in FIG. 3 occurs. As the voltage applied to the drain becomes higher, this phenomenon becomes more pronounced, and the transistor operates in a bipolar manner. This is the second kink.
従来のSOI内に形成された半導体装置は以上のように
基板が電極と接続されていないため、正孔がソース近傍
に集まりキンク現象が表れやすく耐圧が低いという問題
点があった。As described above, in the conventional semiconductor device formed in SOI, the substrate is not connected to the electrode, so holes tend to gather near the source, and a kink phenomenon tends to occur, resulting in a low breakdown voltage.
この発明は上記のような問題点を解消するためになされ
たもので、SOI内に形成された高内圧トランジスタを
得ることを目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a high internal voltage transistor formed in SOI.
この発明に係る半導体装置は基板の底にr拡散領域を形
成したものである。A semiconductor device according to the present invention has an r-diffusion region formed at the bottom of a substrate.
この発明におけるP拡散領域は、衝突電離現象によって
発生した正孔を集収する。The P diffusion region in this invention collects holes generated by impact ionization.
以下、この発明の一実施例を図について説明する。第1
図において、(1)はシリコン基板、〈2)はシリコン
酸化膜、〈3)はシリコン層、0υはドレイン拡散層、
(2)はソース拡散層、(至)はP鴬散層、ODはドレ
イン電極、04はソース電極、(5)はゲート電極、(
6)はゲート酸化膜である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a silicon substrate, <2) is a silicon oxide film, <3) is a silicon layer, 0υ is a drain diffusion layer,
(2) is the source diffusion layer, (to) is the P diffusion layer, OD is the drain electrode, 04 is the source electrode, (5) is the gate electrode, (
6) is a gate oxide film.
次に動作について説明する。ソース電極(6)を接地し
、ゲート電極(5)に正の電圧を印加すると、トランジ
スタがオン状態となる。この状態でドレイン電極0に正
の電圧を印加すると、先に述べたようにソース拡散層(
2)からドレイン拡散MO])に電子が流れる。また、
十分に電子がエネルギーを得ると、シリコン格子に衝突
し電子正孔対を発生する。Next, the operation will be explained. When the source electrode (6) is grounded and a positive voltage is applied to the gate electrode (5), the transistor is turned on. When a positive voltage is applied to the drain electrode 0 in this state, the source diffusion layer (
Electrons flow from 2) to the drain diffusion MO]). Also,
When the electrons gain enough energy, they collide with the silicon lattice and generate electron-hole pairs.
ここで発生した電子はドレイン電界に沿ってドレイン拡
散層0υに吸収される。正孔は基板中を流れ正孔密度の
高いP4″拡散層(至)に吸収される。これにより、ソ
ース拡散層(2)近傍に蓄積することがなくなり、ソー
スと基板間の電位障壁も低くならなくなる。その結果、
キンク現象が小さく、あるいは出現しなくなる。The electrons generated here are absorbed into the drain diffusion layer 0υ along the drain electric field. Holes flow through the substrate and are absorbed by the P4'' diffusion layer (2), which has a high hole density.This prevents them from accumulating near the source diffusion layer (2) and lowers the potential barrier between the source and the substrate. As a result,
The kink phenomenon becomes smaller or does not appear.
なお、上記実施例ではP+拡散層(至)をシリコン層(
3)下部に配置した場合を示したが、P”411を散層
Qをソース領域近傍だけに配置してもよい。また、シリ
コン酸化膜(2)の一部分を摺り下げP+拡fi層を設
けてもよい。Note that in the above embodiment, the P+ diffusion layer (to) is replaced by a silicon layer (
3) Although the case where it is placed at the bottom is shown, the P"411 diffused layer Q may be placed only in the vicinity of the source region. Also, a part of the silicon oxide film (2) is slid down and a P+ diffused layer is provided. You can.
以上のようにこの発明によれば、基板にP+拡散層を配
置したので、衝突電離現象によって発生した正孔を吸収
することができ、SOI内のトランジスタの耐圧を向上
させることができる。As described above, according to the present invention, since the P+ diffusion layer is disposed on the substrate, it is possible to absorb holes generated by impact ionization phenomenon, and it is possible to improve the breakdown voltage of the transistor in SOI.
第1図はこの発明の一実施例による半導体装置を示す断
面図、第2図は従来の半導体装置を示す断面図、第3図
は従来の半導体装置のドレイン電流−ドレイン電圧特性
を示す図である。
図において、(1ンはシリコン基板、(2)はシリコン
酸化膜、(3)はシリコン層、 00はドレイン拡散層
、■はソース拡散層、(至)はP1拡散層、四はドレイ
ン電極、(6)はソース電極、(5)はゲート電極、(
6)はゲート酸化膜を示す。
なお、図中、同一符号は同一、又は相当部分を示す。
代
理
人
大
岩
増
雄
第1図
17
2
シース電械
第2区
2
第3図
トーレイ:、tFL
16事件の表示
平
特願l1ii 1−167597号
2、発明の名称
半導体装置
3、補正をする者
事件との関係FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view showing a conventional semiconductor device, and FIG. 3 is a diagram showing drain current-drain voltage characteristics of the conventional semiconductor device. be. In the figure, (1) is a silicon substrate, (2) is a silicon oxide film, (3) is a silicon layer, 00 is a drain diffusion layer, ■ is a source diffusion layer, (to) is a P1 diffusion layer, 4 is a drain electrode, (6) is the source electrode, (5) is the gate electrode, (
6) shows the gate oxide film. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 17 2 Sheath Electrical Machinery No. 2 Section 2 Figure 3 Toray:, tFL 16 Display of Cases Plain Patent Application 11ii 1-167597 No. 2, Title of Invention Semiconductor Device 3, Person Who Makes Amendment Case connection of
Claims (1)
スタにおいて、基板濃度より濃い領域を備えたことを特
徴とする半導体装置。A semiconductor device characterized in that a transistor is manufactured in a silicon layer formed on an insulating film, and includes a region having a higher concentration than the substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16759789A JPH0332064A (en) | 1989-06-29 | 1989-06-29 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16759789A JPH0332064A (en) | 1989-06-29 | 1989-06-29 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0332064A true JPH0332064A (en) | 1991-02-12 |
Family
ID=15852719
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16759789A Pending JPH0332064A (en) | 1989-06-29 | 1989-06-29 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0332064A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6770517B2 (en) | 1997-06-19 | 2004-08-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
-
1989
- 1989-06-29 JP JP16759789A patent/JPH0332064A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6770517B2 (en) | 1997-06-19 | 2004-08-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
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