JPH0331003B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency comparator used for detecting a change in frequency difference between two input signals, and in particular, the present invention relates to a frequency comparator used for detecting a change in frequency difference between two input signals, and in particular, a frequency comparator used for detecting a change in frequency difference between two input signals. , we propose an improved frequency comparator that can obtain accurate comparison results even when one frequency fluctuation is large.

FIG. 1 shows a conventionally proposed frequency comparator for detecting fluctuations in the frequency difference between two input signals. In FIG. 1, an input terminal 1 is supplied with a first input signal S ₁ having a frequency F ₁ .
The frequency F ₁ of this first input signal S 1 is divided by 1/M by the frequency divider ₂ , and the first input signal S 1 is output to the phase comparator 3 as a signal S ₁ ' having a frequency of 1/M·F ₁ . 1 input terminal. On the other hand, input terminal 4 has a frequency F ₂
A second input signal S 2 is provided having S ₂ . This second input signal S ₂ is divided by frequency divider 5 into its frequency
F ₂ is frequency-divided by 1/N and supplied to the other input terminal of the phase comparator 3 as a signal S ₂ ' having a frequency of 1/N·F ₂ . Then, in the phase comparator 3, the signal
The phase difference between S ₁ ' and signal S ₂ ' is detected, and the detected output is obtained at output terminal 6. Here, the frequency dividers 2 and 5 are configured such that, for example, if there is no variation in the frequencies F ₁ and F ₂ , the frequencies 1/M・F ₁ and 1/N・F ₂ are equal to each other, and therefore the frequencies When at least one of F ₁ and F ₂ fluctuates, S ₁ ′ and signal S ₂ ′ have a mutual phase difference depending on the fluctuation. Therefore, the phase difference detection output obtained at the output terminal 6 becomes the frequency comparison output of the first and second input signals S1 _{and S2} , and the difference between the first and second input signals _S1 and _S2 is It represents the fluctuation of the frequency difference between.

However, in such a conventional frequency comparator, if at least one of the frequencies F ₁ and F ₂ of the first and second input signals S ₁ and S ₂ fluctuates significantly, the signal S The mutual phase difference between _{S 1} ' and S ₂ ' becomes large, so that the phase comparator 3 may no longer be able to operate properly. For example, the signal
If the mutual phase difference between S ₁ ' and S ₂ ' becomes 2π+α with reference to the one with the smaller period, it will no longer be possible to differentiate from the case where the mutual phase difference is α. Therefore, if at least one of the frequencies F 1 and F ₂ of the first and second input signals S _{1 ′} and S ₂ ′ fluctuates significantly, there is a possibility that accurate frequency comparison output may not be obtained. There is. Also, frequency divider 2
Since the frequency division ratios 1/M and 1/N of 1/M and 5 are difficult to change once they are set, the frequencies F ₁ and F ₂
In order to make the frequencies 1/ _M・F ₁ and ₁ /N・F ₂ equal to each other when there is no variation in There is also the disadvantage that the degree of freedom of choice is reduced.

The present invention provides an improved frequency comparator that does not have the problems found in conventional frequency comparators and can obtain accurate frequency comparison results even for two signals whose respective frequency differences vary greatly. I will provide a. Hereinafter, embodiments of the present invention will be described with reference to FIG. 2 and subsequent figures.

FIG. 2 is a circuit diagram showing an example of a frequency comparator according to the present invention. In FIG. 2, 7 and 8 are input terminals to which a first input signal P ₁ and a second input signal P ₂ are supplied, respectively, and 9 is an output terminal. The input terminal 7 is, for example, a trigger input terminal T of a positive edge trigger type D-type flip-flop circuit (hereinafter referred to as an F/F circuit) 10.
The data input terminal D of this F/F circuit 10 is connected to the inverting output terminal. Also, F.
An F/F circuit 11 similar to the F circuit 10 is provided,
The input terminal 8 is connected to the trigger input terminal T of this F/F circuit 11, and the data input terminal D is connected to the inverting output terminal Q. The non-inverting output terminal Q of the F•F circuit 10 is connected to the direct reset terminal R of the F•F circuit 11 and to the control terminal of the first constant current source 12. Also, F.
The non-inverting output terminal Q of the F circuit 11 is connected to the F/F circuit 10.
It is connected to the direct reset terminal R of the constant current source 13, and also to the control terminal of the second constant current source 13. The current path of the first constant current source 12 and the current path of the second constant current source 13 are connected in series, and one end of a capacitor 14 is connected between both constant current sources. The other end of this capacitor 14 is grounded, and the one end connected between the first and second constant current sources 12 and 13 is connected to the output terminal 9 via a voltage follower circuit 15 and a low-pass filter 16. has been done.

Next, the operation will be explained with reference to FIGS. 3 to 6. First, the F/F circuits 10 and 11 are
In each case, the output of the non-inverting output terminal Q becomes a low level,
Assume that the inverting output terminal is in an initial state where the output is at a high level. In this case, the F/F circuits 10 and 11
Since the input to the direct reset terminal R of the F/F circuit is at a low level, the trigger input terminal T
is in a state where it can be triggered on its rising edge when an input signal is supplied to it. Then, input terminals 7 and 8 are connected to the first input terminals as shown in FIG.
and second input signals P ₁ and P ₂ are supplied respectively, the F/F circuit 10 is triggered at one rising edge and the next rising edge of the first input signal P ₁ , and between these two rising edges. , that is, during the period t ₁ of the first input signal P ₁ , a high-level control signal P ₁ ' as shown in FIG. 3B is obtained from the non-inverting output terminal Q of the F/F circuit 10. It will be done. Note that this control signal
During the period when P ₁ ' is obtained, the input to the direct reset terminal R of the F/F circuit 11 is at a high level, so the F/F circuit 11 is in a state where the output at its non-inverting output terminal Q is at a low level. held, the second input signal
Even if P ₂ is supplied to the trigger input terminal T, it will not be triggered.

A control signal P ₁ ' from the non-inverting output terminal Q of the F.F circuit 10 is supplied to the control terminal of the first constant current source 12 to operate it. This allows the control signal
During the period _P1 ', that is, the period _t1 of the first input signal _P1 , the constant current I of the first constant current source 12 charges the capacitor 14 through the capacitor 14,
As shown in FIG. 3E, the terminal voltage V _c rises from the reference voltage V _p set in the initial state.

Next, the second signal that arrives after the falling edge of the control signal P ₁ '
The F/F circuit 11 is triggered at the rising edge of the input signal P ₂ and the next rising edge, and the period between these two rising edges, that is, the period t ₂ of the second input signal P ₂
During the period, a high level control signal as shown in FIG.
P ₂ ′ is obtained. Note that during the period when this control signal P ₂ ' is obtained, the input to the direct reset terminal R of the F/F circuit 10 is at a high level, so the output of the non-inverting output terminal Q of the F/F circuit 10 is low. level, and is not triggered even if the first input signal _P1 is supplied to the trigger input terminal T.

The control signal P ₂ ' from the non-inverting output terminal Q of the F.F circuit 11 is supplied to the control terminal of the second constant current source 13 to operate it. This allows the control signal
During the period _P2 ', that is, the period _t2 of the second input signal _P2 , the constant current J of the second constant current source 13 (here,
I>J) flows through the capacitor 14, the capacitor 14 is discharged, and its terminal voltage
V _c falls as shown in FIG. 3E.

Furthermore, at the rising edge of the first input signal P ₁ that arrives after the falling edge of the control signal P ₂ ′ and the next rising edge,
The F/F circuit 10 is triggered again and the control signal
P ₁ ' is generated, and thereafter the above-described charging and discharging of the capacitor 14 is repeated. The terminal voltage V _c of the capacitor 14 is then supplied to the low-pass filter 16 via the voltage follower circuit 15 , and a smoothed output is obtained at the output terminal 9 .

In this case, the F/F circuits 10 and 11 constitute a period detection section that detects the periods t ₁ and t ₂ of the first and second input signals P ₁ and P ₂ , and the output of this period detection section is Based on the control signals P ₁ ′ and P ₂ ′,
During the period corresponding to the period t ₁ , the capacitor 14 is charged with the constant current I of the first constant current source 12 , and then during the period corresponding to the period t ₂ , the capacitor 1 is charged with the constant current I of the first constant current source 12 .
4, the discharge at the constant current J of the second constant current source 13 is performed.

Here, as shown in FIG. 4, the first input signal
If the ratio of the period t ₂ of the _second input signal P ₂ to the period _t 1 of P 1 is equal to the ratio of the constant current I of the first constant current source 12 to the constant current J of the second constant current source 13 ,
That is, when the frequency of the first input signal P ₁ is f ₁ and the frequency of the second input signal P ₂ is f ₂ , if t ₂ /t ₁ = f ₁ /f ₂ = I/J, the capacitor The terminal of the capacitor 14 after the amount of charged charge and the amount of discharged charge in 14 become equal, and the terminal of the capacitor 14 is charged during the period (t ₁ ) of the control signal P ₁ ′ and discharged during the period (t ₂ ) of the control signal P ₂ ′. The voltage V _c becomes the reference voltage V _p . Also, as shown in Figure 5,
When the ratio of the period t ₂ to the period t ₁ is smaller than the ratio of the constant current I to the constant current J, that is, when t ₂ /t ₁ =f ₁ /f ₂ <I/J, the charging in the capacitor 14 The amount of charge becomes larger than the amount of discharged charge after that, and the control signal
The terminal voltage V _c of the capacitor 14 after being charged during the period of P ₁ ′ (t ₁ ) and discharged during the period of the control signal P ₂ ′ (t ₂ ) is equal to the voltage value corresponding to the difference between the two charges. It becomes higher than the reference voltage V _p . Further, as shown in FIG. 6, when the ratio of the period t ₂ to the period t ₁ is larger than the ratio of the constant current I to the constant current J, that is, t ₂ /t ₁ =f ₁ /f ₂ >I /J, the amount of charge subsequently discharged is larger than the amount of charge charged in the capacitor 14, and it is charged during the period (t ₁ ) of the control signal P ₁ ', and the control signal
Capacitor 1 after being charged during the period P ₂ ′ (t ₂ )
The terminal voltage V _c of No. 4 becomes lower than the reference voltage V _p by a voltage value corresponding to the difference between the two charges. Therefore, the terminal voltage V _c of the capacitor 14 is centered around the reference voltage V _p and corresponds to the ratio of the frequency f ₁ of the first input signal P ₁ and the frequency f ₂ of the second input signal P ₂ . The output obtained at the output terminal 9 is the first
and a frequency comparison output for the frequencies f ₁ and f ₂ of the second input signals P ₁ and P ₂ .

In this case, even if both or one of frequencies f ₁ and f ₂ fluctuates significantly, and the difference between them fluctuates greatly, the ratio of frequency f ₁ and frequency f ₂ is the ratio of constant current I to constant current J. A comparison output is obtained based on when f ₁ /f ₂ = I/J, and therefore, by appropriately selecting the values of constant currents I and J, frequency fluctuation of either or both can be reduced. A reliable comparison output can be obtained even for two input signals with large values.
In the example of FIG. 2, the terminal voltage V _c of the capacitor 14 can also be directly used as the frequency comparison output.

Specifically, the first and second constant current sources 12 and 13 in the above embodiment are configured as shown in FIG. 7, for example.

Here, the first constant current source 12 is a transistor
The second constant current source ₁₃ is composed of transistors _{X 4 ,} X ₅ , X _{6 and} X ₇ . The collectors of transistors X ₂ and X ₆ are connected to each other, and a terminal 17 is connected from the midpoint of the connection to a terminal 17 to which one end of the capacitor 14 is connected.
has been derived. Also, transistors X ₁ and
The base of X ₄ is provided with the control signals P ₁ ′ and
P ₂ ′ is supplied. Note that +B indicates a power supply.

To briefly describe the operation of this specific circuit example, a control signal that takes a high level at the base of _transistor
During the period when P ₁ ' is supplied, transistor X ₁ is turned off, which turns transistor X ₂ on. When the control signal P ₁ ′ is obtained,
Since the control signal P ₂ ′ is not available, the transistor X ₄
The potential at the base of the transistor is at a low level,
X ₄ is off and transistor X ₅ is on, which turns off transistor X ₆ .
Therefore, at this time, a constant current I equal to the constant current flowing through the transistor X ₃ flows from the power supply +B through the transistor X ₂ , and this constant current I flows into the capacitor 14 via the terminal 17 .

On the other hand, during the period when the high level control signal P ₂ ' is supplied to the base of transistor X ₄ , transistor X ₄ is turned on and transistor X ₅ is turned off, thereby turning on transistor X ₆ . . When the control signal P ₂ ′ is obtained,
Since the control signal P ₁ ′ is not available, the transistor X ₁
The base potential of is at a low level and the transistor
X ₁ is turned on and transistor X ₂ is turned off.
Therefore, at this time, a constant current J equal to the constant current flowing through transistor X ₇ flows from terminal 17 through transistor X ₆ to ground, and therefore,
A constant current J flows out from the capacitor 14.

In this way, the first constant current source 12 that flows the constant current I and the second constant current source 13 that flows the constant current J
is formed by transistors X ₁ to X ₇ .

FIG. 8 shows an example of a frequency modulation circuit constructed using the example of the frequency comparator according to the present invention shown in FIG. In this Fig. 8, the part surrounded by the broken line is the frequency comparator shown in Fig. 2.
Indicates FC. A reference oscillator 18 is connected to the input terminal 7, and an output terminal of a voltage controlled oscillator 19 is connected to the input terminal 8. moreover,
One input terminal of an adder 20 is connected to the output terminal 9, and the other input terminal of the adder 20 is connected to a modulation input terminal 21 to which a modulation signal S _n is supplied. The output end of the adder 20 is connected to the control input end of the voltage controlled oscillator 19, and the midpoint between the output end of the voltage controlled oscillator 19 and the input terminal 8 is connected to a modulation output for taking out a frequency modulated output. A terminal 22 is led out.

In such a configuration, the frequency from the reference oscillator 18 supplied to the input terminal 7 of the frequency comparator FC
The reference signal S _s of f _s and the oscillation output signal S v of frequency f _v from the voltage controlled _oscillator 19 supplied to the input terminal 8
are the first and second input signals in the example of FIG.
Corresponding to P ₁ and P ₂ , the frequencies are compared by this frequency comparator FC, and a comparison output is obtained at the output terminal 9. The frequency comparison in this case is based on the first and second input signals P ₁ and P ₂ in the example of FIG.
This is done in the same way as the frequency comparison for . The comparison output obtained at the output terminal 9 is then supplied to the voltage controlled oscillator 19 via the adder 20.
The frequency _fv of the oscillation output signal _Sv from the voltage controlled oscillator 19 is controlled. In this case, the frequency f _v of the oscillation output signal S _v is the capacitor 1 in the frequency comparator FC.
In other words, the frequency f v of the oscillation output signal S _v of the frequency f _s of the reference signal S s is set so that the amount of charged charge due to charging with constant current I and the amount of discharged charge due to discharging with constant current J _{in 4} are equal _. The ratio of the constant current I to the constant current J is controlled to be equal to the ratio of the constant current I to the constant current J.
Therefore, by supplying the comparison output from the output terminal 9 to the voltage controlled oscillator 19, an attempt is made to establish the relationship f _s /f _v =I/J, and therefore f _v =J/I·f _s . Control is carried out to

In this state, the modulation signal S _n from the modulation input terminal 21 is supplied to the voltage controlled oscillator 19 via the adder 20, so that the frequency f _v of the oscillation output signal S _v becomes f _v = From a stable state with a relationship of J/I·f _s , it is changed to both high and low levels depending on the modulation signal S _n . That is, the frequency of the oscillation output signal S _v
f _v has a deviation corresponding to the modulation signal S _n with J/I·f _s as the center, and the oscillation output signal S _v is
The center frequency is set to J/I·f _s , and the result is a frequency modulated output with a frequency shift according to the modulation signal S _n . This frequency modulated output is then taken out from the modulated output terminal 22. In this case, the frequency comparator FC has a large degree of frequency modulation, and even if the frequency f v of the oscillation output signal S _v has a large fluctuation, the frequency _{f s of} the reference signal S _s and the oscillation output signal S _{v It} is possible to perform a reliable comparison _with the _frequency f _v of
Since control is performed to establish the relationship J/I f _s , even when deep frequency modulation is performed,
The center frequency J/I·f _s of the frequency modulation output is kept extremely stable.

Furthermore, by changing the ratio between the constant current I and the constant current J, the center frequency of the frequency modulation output can be changed, and furthermore, the frequency f _s of the reference signal S _s
Even if the constant current I changes, the center frequency of the frequency modulation output can be kept constant by changing the ratio between the constant current I and the constant current J. This means that the degree of freedom of the reference oscillator 18 is expanded. In addition,
Since it is usually easy to set and adjust the constant current value of the constant current source, it is easy to change the ratio between the constant current I and the constant current J.

As explained above, the frequency comparator according to the present invention can be used even when the frequency fluctuation of each or one of the two input signals to be frequency compared is large and the frequency difference between the two input signals is large. , it is possible to obtain stable and accurate frequency comparison output. Furthermore, in the frequency comparator according to the present invention, the two input signals are compared at their original frequencies without being frequency-divided, so the comparison response is extremely quick. By using the frequency comparator according to the present invention, it is possible to construct a high-performance frequency modulator that can obtain a frequency modulation output in which the center frequency is kept stable even when the degree of modulation becomes large. .

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a conventional frequency comparator, FIG. 2 is a block connection diagram showing an example of a frequency comparator according to the present invention, and FIGS. 3, 4, 5, and 6 are FIG. 2 is a waveform diagram for explaining the operation of the example shown in FIG. 2, FIG. 7 is a circuit diagram showing a specific configuration example of a part of the example shown in FIG. 2, and FIG. 8 is a frequency comparator according to the present invention. FIG. 2 is a block connection diagram showing an example in which the above is applied to a frequency modulation circuit. In the figure, 7 and 8 are input terminals, 9 is an output terminal, 1
0 and 11 are F.F circuits, 12 is a first constant current source, 13 is a second constant current source, and 14 is a capacitor.

Claims (1)

[Claims] 1 a period detection section that detects the period of the first input signal and the period of the second input signal, and a period detection section that corresponds to the period of the first input signal based on the output of the period detection section. and a capacitor that is charged with a first constant current for a period and discharged with a second constant current for a period corresponding to the period of the second input signal, and the terminal voltage of the capacitor is , a frequency comparator configured to obtain a comparison result between the frequency of the first input signal and the frequency of the second input signal.