JPH0330191A - Input buffer circuit - Google Patents

Abstract

PURPOSE:To suppress a delay when an output of an inverter changes from L to H by using a drain of an N-channel transistor (TR) whose source and gate connects to a power line as a pseudo power line, using its current as the current of an input buffer and providing a capacitor between the drain and ground. CONSTITUTION:An N-channel TR N1 connects to a current voltage supply section (a) of a CMOS inverter in series and a capacitor C is provided between the current voltage supply section (a) and ground. Thus, the capacitor C is charged through the N-channel TR N1 normally and when a VIN changes from L to H, a current flowing from the capacitor C through a TR P is added to a current flowing from a Vcc through the TRs N1, P to bring a level Vo from L to H. Thus, the operation of the Vo is quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS type semiconductor device, and particularly to speeding up an input buffer circuit that can be directly connected to TTL.

[Conventional technology]

FIG. 3 is a circuit diagram showing an input buffer circuit of a conventional TTL direct-coupled CMOS semiconductor device.

In the figure, P is a P-channel transistor, N is an N-channel transistor, VIN is an input signal, and Vo is an inverter output.

The input buffer circuit of a conventional CMOS type semiconductor device is composed of a simple inverter or a NOR circuit. Of these, the type of monoha that can be directly connected to TTL, voO = 5v
lm vs. 1.5V or more wo'u" 1.5V or less 4L
For example, in an input buffer circuit configured with an inverter as shown in Fig. 3, the transistor size of the P-channel transistor P is reduced to suppress the driving force, and the transistor size of the N-channel transistor N is reduced. By increasing the driving force, the logic threshold of the inverter is shifted to the side closer to GND.

[Problem to be solved by the invention]

Since the conventional input buffer 1 circuit is configured as described above, when the input changes from L level to H level and the output of the inverter changes from L level to H level, due to the small driving ability of the P channel transistor, A problem has arisen in that the operating speed is slow.

This invention was made in order to solve the above problem, and it is an input buffer circuit that suppresses the delay when the output of this inverter changes from 'L' to ('H') using an input inverter that can be directly connected to TTL. The purpose is to obtain.

(Means for Solving Problem 8) The input buffer 1 of the CMOS semiconductor device according to the present invention includes an N-channel transistor connected in series to the power supply voltage supply section of the CMOS inverter, and further connected to the power supply voltage supply section and the ground. A capacitor is added in between.

[Effect]

This predetermined capacitor acts to suppress the delay when the inverter output changes from <L> to <H'/.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an input buffer circuit showing one embodiment of the present invention. In the figure, P is a P-channel transistor, N%N1 is an N-channel transistor, and C is a capacitor.

Further, VIN indicates an input signal to the input buffer, ■ indicates an output signal of the input buffer, and a indicates a node name.

In addition, the threshold voltage of the P-channel transistor P is VT
fIp, the threshold voltage of the N-channel transistor is
Let it be T11IN.

Next, the operation will be explained. When VIN is not operating, the potential of node a is (Voo - VTx)
becomes. Here, Voo = 5. 0 (V), VT
If HN = O, 8(v) Toshita, Vco - VTH
N = 4.2 (Ill/) tonal.

In short, this is the same as operating an inverter made up of transistors P and N when the power supply voltage is 4.2 (V). Therefore, when this inverter is used as an input buffer, Voo = 4.2 V and the logic threshold is set to 1.
All you have to do is set it to 5V. In order to set the logical threshold to 1.5V with a power supply voltage of 5■, it is necessary to make the P-channel transistor P considerably smaller, but with a power supply voltage of 4.2■, the theoretical threshold can be set to 1.5V. In order to achieve this, there is no need to particularly reduce the size of the P-channel transistor P.

However, when VIN moves from 4}{# to rumored L', power is supplied through N-channel transistor N1 and P-channel transistor P to change Vo from ゃL〃 to 4H', but the driving force of P-channel transistor P Even if becomes large, the impedance of the N-channel transistor NZ is added, and the series circuit of transistors N1 and P will not be able to obtain sufficient driving force. Capacity C compensates for this. Capacitance C is usually an N-channel transistor Nl
is being charged through. When VIN changes from ゞL〃 to 2H', Vco changes from ゞL〃 to 5H'.
The current flowing from C through transistor P is added to the current flowing from C through transistors Nl and P, resulting in faster operation of Vo.

In the above embodiment, the N-channel transistor N1 that provides (Voa - VTHN) and an inverter are combined, but the N-channel transistor N1 and the NOR circuit PA-NA (7) shown in FIG.
A combination may also be used. In the figure, S indicates a control signal such as a chip select signal.

〔Effect of the invention〕

As described above, according to the present invention, C
In the input buffer circuit of a MOS type semiconductor device, the power supply voltage of the input inverter is now (Voo - VTHN), so there is no need to increase the ratio of the driving power between the P-channel transistor and the N-channel transistor, and the P-channel transistor There is no need to squeeze it small. In addition, since a capacitor was inserted to compensate for the driving ability impaired by the impedance of the N-channel transistor that provides (Vaa-VTHN), the delay that occurred when the inverter output changed from もL# to もH〇 was reduced. There is no element, and the effect is that a speed comparable to that of going from ゞ■' to 4L〃 can be obtained.

[Brief explanation of drawings]

Figure v441 is a circuit diagram of one input buffer circuit of a CMOS semiconductor device showing one embodiment of this invention, Figure 2 is a characteristic curve diagram of VIN and Vo in Figure 1, and Figure 3 is another embodiment of this invention. 4 is a circuit diagram of an input buffer circuit of a conventional CMOS semiconductor device,
FIG. 5 is a characteristic curve diagram of VIN and Vo in FIG. 4. In the figure, P is a P-channel transistor%N%N1 is an N-channel transistor, C is a capacitance, and PA and NA are NO
The R circuit is shown. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In an input buffer circuit configured using a P-channel transistor and an N-channel transistor, the drain of the N-channel transistor whose source and gate are connected to a power supply line is used as a pseudo power supply line, and this pseudo power supply line is used as a power supply for the input buffer, and the An input buffer circuit characterized by adding a capacitor between a pseudo power line and ground.