JPH03296266A - Storage circuit and storage controller - Google Patents

Abstract

PURPOSE:To constitute a storage circuit with fewer transistors by providing three or more kinds of a transistors, wherein threshold voltages are different, in array shape so as to constitute a storage circuit. CONSTITUTION:In a storage circuit 31, four kinds of MOS transistors are arranged in array shape, according to specified patterns. The gate electrodes 17a, 17b, and 17c of each transistor are connected to a row decoder 33, and drain windings 19a, 19b, 19c, and 19d of each transistor are connected to a column decoder 34. A voltage supply circuit 32 supplies three kinds of voltages to the control terminal of the transistor constituting the storage circuit 31. 35 is an address circuit, and supplies address information to the row decoder 33 and the column decoder 34. A latch circuit 36 latches a high-order bit out of the stored data of two bits, and a latch circuit 37 latches a low-order bit. These latch circuits 36 and 37 constitute a reading circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit and a memory control device.

[Prior Art] Conventionally, each memory cell of a ROM (read only memory) has been written with either "0" or "1" data, thereby storing one bit of data. That is, the transistors constituting each memory cell have two types of threshold voltages, high and low, and data "0" or "1" is stored corresponding to these two types of threshold voltages. In addition, stored data has been determined by applying a voltage between the above two types of threshold voltages to the control terminal of the transistor, and checking whether the transistor becomes conductive.

[Problem to be solved] However, in the above-mentioned conventional devices, only one bit of data can be stored in one transistor, so there is a problem that the number of transistors that make up the memory circuit becomes enormous. .

An object of the present invention is to configure a memory circuit with a small number of transistors.

[Means for Solving the Problems] The present invention configures a memory circuit by providing three or more types of transistors having different threshold voltages in an array.

[Example] Hereinafter, an example of the present invention will be described based on the accompanying drawings.

The embodiment shown in FIG. 1 has four different threshold voltages.
This figure shows the manufacturing process of different types of MOS transistors. When actually configuring a memory circuit, these four
Various types of MOS transistors are arranged in an array.

11 is a silicon substrate, 12 is a gate insulating layer, and 13 is an interlayer insulating layer. Impurity layers 14a, 14b, and 14c are layers into which impurity ions are implanted in order to control the threshold voltage of the MOS transistor. 15 is a source, and 16 is a drain. 17a, 17b, 17c and 17d are gate electrodes. I B a, 18
b, 18c and 18d are source wiring, 19a
% 19 b % 19 c and 19 cl are train wiring. The threshold voltages of the four MOS transistors 21 and 22 shown on the photoresist are as follows:
From the left side, they are 4 volts, 3 volts, 2 volts, and 1 volt.

Next, the manufacturing process will be explained according to FIGS. 1(A) to 1(C).

Step (A) - After forming the gate insulating layer 12 on the surface of the silicon substrate 11, the threshold voltage of each transistor is adjusted in advance to be 1 volt. Next, a pattern of the photoresist 21 is formed in which an open pattern is provided in the leftmost transistor portion and the second transistor portion from the left. Using this photoresist 21 as a mask, impurity ions are implanted in an amount that changes the threshold voltage of the transistor by 2 holts. Photoresist 21 after ion implantation
remove. In this way, impurity layers 14a and 14b having a threshold voltage of 3 volts are formed.

Step (B) - Form a pattern of photoresist 22 in which an open pattern is provided in the leftmost transistor part and the third transistor part from the left.

Using this photoresist 22 as a mask, impurity ions are implanted by an amount that changes the threshold voltage of the transistor by one Holt. After ion implantation, the photoresist 22 is removed. In this way, impurity layer 14a having a threshold voltage of 4 volts and impurity layer 14c having a threshold voltage of 2 volts are formed.

Step (C): Gate electrodes (17a, 17b, 17C and 17d), source 15 and train 16, interlayer insulating layer 13, source wiring (18a, 18b, 18c and 1
8d) and drain wiring (1 9 a, 1 9 b
, 19c and 19d) are sequentially formed by known methods.

The threshold voltages of the four types of MOS type L transistors obtained through the above steps are 4 volts, 3 volts, 2 volts, and 1 volt in order from the left side. These four types of transistors allow 2-bit data to be stored. For example, for each transistor with a threshold voltage of 4 volts, 3 volts, 2 volts, and 1 volt, "11" 1
2-bit data of 0, 01, and 00 can be respectively associated with each other.

Nao, if each threshold voltage and each 2-bit data correspond to each other as described above, the first ion implantation process (Fig. 1 (A)
It can be seen that the second ion implantation step (FIG. 1(B)) corresponds to the lower bit of the 2-bit data.

Therefore, for example, assuming that the upper bits are basic data and the lower bits are variation data, when changing only the halition data, it is only necessary to change the photomask for the second ion implantation. Furthermore, if only basic data is required, the second ion implantation step is not necessary. In this case, it is equivalent to writing 1-bit data to each transistor, and has upward compatibility with the conventional one.

FIG. 2 shows an example of a storage control device constructed using the storage circuit obtained in the manufacturing process shown in FIG. In the following explanation, for each transistor with a threshold voltage of 4 Ports, 3 Holts, 2 Volts, and 1 Port,
It is assumed that the 2-bit data "11", 10", "01", and "00n" correspond to each other.

31 is a memory circuit, in which four types of MO5 type transistors shown in FIG. 1(C) are arranged in an array according to a predetermined memory pattern. To explain the terminals of each transistor using FIG. 1(C), the case I electrodes 17a, 17b, 17c, and 17d of each transistor are connected to a row decoder 33, which will be described later, and the drain wiring 19a, 19b, . 19c and 19d are connected to a column decoder 34, which will be described later.

Reference numeral 32 denotes a voltage supply circuit that supplies three types of voltages to control terminals of transistors forming the memory circuit 31. Specifically, the gate electrodes 17a, 17b, 17C and 17d of each transistor shown in FIG.
It supplies three types of voltages: 3.5 volts, 2.5 volts, and 1.5 volts.

33 is a row decoder, which is an address designation circuit 3 to be described later.
The voltage output from the voltage supply circuit 32 is supplied to each transistor located at the row address designated by 5.

A column decoder 34 selectively reads data stored in a transistor located at a column address designated by an address designation circuit 35, which will be described later.

35 is an address designation circuit that supplies address information to the row decoder 33 and column decoder 34.

36 and 37 are latch circuits, and column decoder 3
This is to latch the storage data output from 4.

The latch circuit 36 latches the upper bit of the 2-bit stored data, and the latch circuit 37 latches the lower bit. The latch circuits 36 and 37 constitute a read circuit.

Reference numeral 38 denotes a control circuit, which mainly controls the timing of the voltage supply circuit 32, latch circuits 36, 37, and the like.

Next, the operation of the storage control device shown in FIG. 2 will be explained.

First, address information is supplied from the address designation circuit 35 to the row decoder 33 and column decoder 34, and a transistor from which stored data is to be read is designated. On the other hand, a voltage of 2.5 volts is output from the voltage supply circuit 32 and applied to the gate electrode of a designated transistor through the row decoder 33. If the specified transistor is conductive at this time, the threshold voltage of that transistor is 1.
volt or 2 volts, and the upper bit of the stored data is "0". If there is no conduction,
The threshold voltage of the designated transistor is 3 volts or 4 volts, and the upper bit of the stored data is "1". The 1st bit data thus obtained is latched into the latch circuit 36 by a latch signal from the control circuit 38.

Next, the voltage supply circuit 32 outputs a voltage of 1.5 volts or 3.degree. Latch data ("1st focus data)"
0", a voltage of 1.5 volts is output from the voltage supply port ult32 and applied to the gate electrode of the designated transistor. At this time, if the designated transistor conducts, the threshold voltage of that transistor is 1 volt. Therefore, the lower bit of the stored data will be "0".If it is non-conductive, the threshold voltage of the designated transistor will be 2 volts, and the lower bit of the storage data will be "1". The lower bit data thus obtained is latched in the latch circuit 37 by the latch signal from the control circuit 38. On the other hand, when the latch data (upper bit data) is “1”, the lower bit data is latched from the voltage supply circuit 32. A voltage of 3.5 volts is output and applied to the gate electrode of the designated transistor.In this case as well, the lower bit of the stored data is latched into the latch circuit 37 based on the conduction state of the designated transistor.

As described above, 2-bit data is latched into the latch circuits 36 and 37 in correspondence with the four types of threshold voltages of the designated transistors.

Note that when reading only the upper bits using the circuit shown in Figure 2, it is equivalent to writing 1-bit data to each transistor, and is upwardly compatible with the conventional circuit. will have the following.

Although the examples shown in FIGS. 1 and 2 above are cases in which 2 bits of data are stored in one transistor, the present invention is also applicable to cases in which 2 bits of data are stored in one transistor.

[Effects] In the present invention, since the memory circuit is configured by providing three or more types of transistors and transistors having different threshold voltages in an array, the memory circuit can be configured with a small number of transistors.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a manufacturing process showing an example of a memory circuit according to the present invention, and FIG. 2 is a block diagram showing an example of a storage control device constructed using the memory circuit shown in FIG. 1. . 31...Memory circuit 32...Voltage supply circuit 36.37...Latch circuit (read circuit)

Claims (2)

[Claims] (1) A memory circuit in which three or more types of transistors with different threshold voltages are arranged in an array. (2) a memory circuit in which three or more types of transistors with different threshold voltages are arranged in an array; a voltage supply circuit that supplies two or more types of voltage to the control terminal of the transistor; and a voltage supply circuit that supplies two or more types of voltage to the control terminal of the transistor; and a reading circuit for reading the on/off state of the transistor for each voltage supplied to the storage controller.