JPH0329530A - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPH0329530A
JPH0329530A JP16471189A JP16471189A JPH0329530A JP H0329530 A JPH0329530 A JP H0329530A JP 16471189 A JP16471189 A JP 16471189A JP 16471189 A JP16471189 A JP 16471189A JP H0329530 A JPH0329530 A JP H0329530A
Authority
JP
Japan
Prior art keywords
signal
gate
section
voice
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16471189A
Other languages
Japanese (ja)
Other versions
JP2967783B2 (en
Inventor
Kiyoshi Matsutani
清志 松谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16471189A priority Critical patent/JP2967783B2/en
Publication of JPH0329530A publication Critical patent/JPH0329530A/en
Application granted granted Critical
Publication of JP2967783B2 publication Critical patent/JP2967783B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To reduce the generation of stimulating voice giving displeasure in audible sense when the voice is generated again after the end of muting period by decreasing the voice level just after the end of the muting period. CONSTITUTION:When the input of a mute signal is finished, a gate switching section 11 sends a signal turning off a gate from a zero cross point just after, sends a signal turning off the gate, sends a select signal to a selector section 14 simultaneously, and the selector section 14 selects the outputs a digital voice data from a bit shift section 13. Moreover, a gate section 12 outputs a voice data from the selector section 13. Then the gate switching section stops the transmission of the select signal at the succeeding zero cross point, the selector section 14 selects an input digital voice data and the gate section outputs the input digital voice data. Thus, the outputted voice signal, after the end of the mute signal, becomes a signal whose level is halved only till the succeeding zero cross point and even when a voice signal at the end of the muting period is large, the listening sense of a stimulating voice is relieved.

Description

【発明の詳細な説明】[Detailed description of the invention]

[a業上の利用分野] この発明は、音声信号のくユーティング回路に関する, [従来の技術] 第4図は、従来のミューティング回路のプロック回路図
である.図において、<10)はゼロクロス検出部で、
入力されるデイジタル音声データ中のゼロクロス点を常
C検出する, (1))はゲート開閉部で、ミュート信
号の開始、あるいは終了時点の直後のゼロクロス点を以
って、入カデイジタル音声データのゲートをON/OF
Fするゲート信号を送出する, (12)はゲート部で
、ゲート開閉部(1l)からのゲート信号をうけてデイ
ジタル音声データをゲートする. 第5図はこの従来例の信号波形およびタイミング図で、
同図(a)は出力音声信号、同図(b)はaユート信号
である. 次に動作について説明する.例えば、2の補数形式で符
号化されたディジタル音声データが入力されている場合
、その最上位のビットデータが「1」から「0」、ある
いは「o」から『1」に変化する点がゼロクロス点とな
る.ゼロクロス検出部(lO)は、このゼロクロス点を
常時検出する.ゲート開閉部(1))は、主ユート信号
が入力されると、その直後のゼロクロス点から、ゲート
をONにする信号を送出し、ゲート部(12)はディジ
タル音声データをマスクして、出力音声データを全ビッ
ト「0」にする.こうすることによって、以降、ヨユー
テイング期間が終了するまで、出力音声信号はレベルゼ
ロの無音状態となる.次にミュート信号が終了すると、
ゲート開閉部(1))は、その直後のゼロクロス点でゲ
ートをOFFにする信号を送出し、ゲート部(l2)は
ディジタル音声データを出力する. この結果、出力音声信号aの波形は第5図(a)のよう
になる. [発明が解決しようとする課題J 従来の主ユーテイング回路は以上のように構成されてい
るので、主ユーテイング期間の終了時Cは無音状態のゼ
ロクロス点から音声が始まるので、スムーズに音がつな
がるが、ミューティング期間終了直後の音声レベルが大
きい場合にはひっかかったような刺激的な音声として聴
こえるといういう問題点があった. この発明は、上記のような問題点を解消するためになさ
れたもので、従来の利点は生かしつつ、さらに主ユーテ
イング期間終了直後の音声レベルが大きい場合でも、ひ
っかかったような刺激的な音声として聞こえないよユー
テイング回路を得ることを目的とする.
[Field of Application in Business A] The present invention relates to a muting circuit for audio signals. [Prior Art] Fig. 4 is a block circuit diagram of a conventional muting circuit. In the figure, <10) is the zero cross detection section,
The zero-crossing point in the input digital audio data is always detected. (1)) is the gate opening/closing part, and the gate of the input digital audio data is detected at the zero-crossing point immediately after the start or end of the mute signal. ON/OF
(12) is a gate section, which receives the gate signal from the gate opening/closing section (1l) and gates the digital audio data. Figure 5 shows the signal waveform and timing diagram of this conventional example.
Figure (a) shows the output audio signal, and Figure (b) shows the a-ute signal. Next, we will explain the operation. For example, when digital audio data encoded in two's complement format is input, the point where the most significant bit data changes from "1" to "0" or from "o" to "1" is the zero crossing point. It becomes a point. The zero-crossing detection unit (lO) constantly detects this zero-crossing point. When the main user signal is input, the gate opening/closing section (1) sends out a signal to turn on the gate from the zero cross point immediately after that, and the gate section (12) masks the digital audio data and outputs it. Set all bits of audio data to ``0''. By doing this, the output audio signal will be in a silent state with a level of zero until the end of the yawing period. Then, when the mute signal ends,
The gate opening/closing section (1) sends out a signal to turn off the gate at the zero cross point immediately after that, and the gate section (12) outputs digital audio data. As a result, the waveform of the output audio signal a becomes as shown in FIG. 5(a). [Problem to be Solved by the Invention J] Since the conventional main using circuit is configured as described above, at the end of the main using period C, the sound starts from the zero cross point in the silent state, so the sound is connected smoothly. However, there was a problem in that if the audio level was high immediately after the muting period ended, the audio would sound distorted and irritating. This invention was made to solve the above-mentioned problems, and while making use of the advantages of the conventional technology, even when the sound level is high immediately after the end of the main usage period, it can be used to create a scratchy, stimulating sound. The purpose is to obtain an inaudible euting circuit.

【課題を解決するための手段1 この発明におけるξユーテイング回路はミューティング
期間終了直後のゼロクロス点から一定区間後のゼロクロ
ス点までの出力音声信号のレベルを下げる手段を備えた
点を特徴とする.【作用】 この発明における音声レベルを下げる手段は、ミューテ
ィング期間の終了直後から一定の間、音声レベルを下げ
るため、主ユーテイング終了直後の音声がひっかかった
ような刺激的な音声として聴こえる度合が軽減される.
[Means for Solving the Problems 1] The ξ-utilizing circuit of the present invention is characterized by having means for lowering the level of the output audio signal from the zero-crossing point immediately after the end of the muting period to the zero-crossing point after a certain interval. [Operation] The means for lowering the audio level in the present invention lowers the audio level for a certain period of time immediately after the end of the muting period, thereby reducing the degree to which the audio immediately after the end of the main usage sounds like a scratchy or irritating sound. It will be done.

【発明の実施例】[Embodiments of the invention]

以下、この発明の一実施例を、図について説明する. 第1図は、この実施例のブロック回路図で、(l3)は
デイジタル音声データをビットシフトして音声レベルを
半減させるビットシフト部、(l4)は入カデイジタル
音声データと、ビットシフトされたデイジタル音声デー
タとを切換えるセレクタ部である. 第2図は、この実施例で信号波形およびタイミング図で
、同図(a)は出力音声信号、同図(b)はミュート信
号、同図(C)はセレクト信号である. 次に動作について説明する. ビットシフト部(l3)は、デイジタル音声データの最
上位のビットデータは保持しつつ、全ビットデータを1
ビットずつ下位ヘシフトさせることにより、実データの
半分のレベルに下げた音声データを常時出力する.ゲー
ト開閉部(l1)は、ミュート信号が入力されると、そ
の直後のゼロクロス点からゲートをONにする信号を出
力し、ゲート部(12)は、セレクタ部(14)から入
力されるデイジタル音声データをマスクして出力データ
を全ビット「0」とする.こうすることによって、以降
ミユーテイング期間が終了するまで、音声はレベルゼロ
の無音状態となる. 次に、ミュート信号の入力が終ると、ゲート開閉部(1
))は、その直後のゼロクロス点からゲートをOFFに
する信号を送出すると同時に、セレクタ部(14)にセ
レクト信号を送出し、セレクタ部(14)は、ビットシ
フト部(13)からのデイジタル音声データを選択して
出力する.ゲート郎(l2)は、そのセレクタ部(l3
)からの音声データを出力する.そして、ゲート開閉部
(1))は、次のゼロクロス点でセレクト信号の送出を
停止し、セレクタ部(l4)は人力デイジタル音声デー
タを選択し、ゲート部は、その入力デイジタル音声デー
タを出力する. この結果、出力される音声信号は、第2図(a)の実線
に示すように、ミュート信号の終了後、次のゼロクロス
点までの間だけレベルが半減された信号となり、主ユー
テイング期間終了時の音声信号が大きい場合でも刺激的
な音声として聴えることが軽減される. なお、上記実施例では音声信号として、デイジタル信号
を用いたが、アナログ信号にも同様に適用できる. また、音声信号のレベルを下げる手段は、ビットシフト
部に限られるものではなく、さらにレベルを下げる割合
は、半分に限られない.また、上記実施例では、ミュー
ティング期間終了直後のゼロクロス点から次のゼロクロ
ス点まで、期間の音声信号のレベルを下げたが、第3図
の示すようにタイマ(l5)を設け、ある一定時間、レ
ベルを下げた状態を続けた後、最初に検出したゼロクロ
ス点から元のレベルに復帰させるようにしてもよい. [発明の効果] 以上のように、この発明によれば、主ユーテイング期間
の終了直後の音声レベルを下げるようにしたので、ミュ
ーティング期間が終了して、再び音声が出る時の聴感上
ひっかかるような刺激的な音声が出るのを軽減できる主
ユーテイング回路が得られる効果がある.
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block circuit diagram of this embodiment, in which (l3) is a bit shift unit that bit-shifts digital audio data to reduce the audio level by half, and (l4) is a block circuit diagram of the input digital audio data and the bit-shifted digital audio data. This is a selector section that switches between audio data and audio data. FIG. 2 is a signal waveform and timing diagram for this embodiment, in which (a) shows the output audio signal, (b) the mute signal, and (C) the select signal. Next, we will explain the operation. The bit shift unit (l3) converts all bit data to 1 while retaining the most significant bit data of the digital audio data.
By shifting bits to the lower level, audio data is always output with the level lowered to half that of the actual data. When a mute signal is input, the gate opening/closing unit (11) outputs a signal that turns on the gate from the zero cross point immediately after the mute signal, and the gate unit (12) outputs a signal that turns on the gate from the zero cross point immediately after the mute signal is input. Mask the data and make the output data all bits ``0''. By doing this, the audio becomes silent with a level of zero until the muting period ends. Next, when the input of the mute signal is finished, the gate opening/closing section (1
)) sends out a signal to turn off the gate from the zero cross point immediately after that, and at the same time sends out a select signal to the selector section (14), and the selector section (14) receives the digital audio from the bit shift section (13). Select and output data. Gatero (l2) is the selector part (l3
) outputs the audio data from ). Then, the gate opening/closing section (1) stops sending out the selection signal at the next zero cross point, the selector section (l4) selects the human-powered digital audio data, and the gate section outputs the input digital audio data. .. As a result, the output audio signal becomes a signal whose level is halved only from the end of the mute signal until the next zero cross point, as shown by the solid line in Figure 2 (a), and when the main using period ends. Even when the audio signal is large, the sound is less likely to be perceived as irritating. Note that in the above embodiment, a digital signal was used as the audio signal, but the invention can be similarly applied to an analog signal. Further, the means for lowering the level of the audio signal is not limited to the bit shift section, and the rate at which the level is lowered is not limited to half. Furthermore, in the above embodiment, the level of the audio signal during the period is lowered from the zero-crossing point immediately after the end of the muting period to the next zero-crossing point, but as shown in FIG. , after the level continues to be lowered, the level may be returned to the original level from the first detected zero crossing point. [Effects of the Invention] As described above, according to the present invention, the sound level immediately after the end of the main listening period is lowered, so that when the muting period ends and the sound comes out again, it will not be audible. This has the effect of providing a main using circuit that can reduce the occurrence of irritating sounds.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例のブロック回路図、′!J
2図はこの実施例の信号波形およびタイミング図、第3
図はこの発明の他の実施例のブロック回路図、第4図は
従来の主ユーテイング回路のブロック回路図、′!J5
図はこの従来例の信号波形およびタイミング図である. (10・・・ゼロクロス検出部、(1))・・・ゲート
開閉部、(12)=・ゲート部、(l3)・・・ビット
シフト部、(l4)・・・セレクタ部. なお、各図中、同一符号は同一 または相当部分を示す
FIG. 1 is a block circuit diagram of one embodiment of the present invention, '! J
Figure 2 is a signal waveform and timing diagram of this embodiment, Figure 3 is
The figure is a block circuit diagram of another embodiment of the present invention, and FIG. 4 is a block circuit diagram of a conventional main using circuit.'! J5
The figure shows the signal waveform and timing diagram of this conventional example. (10... Zero cross detection section, (1))... Gate opening/closing section, (12)... Gate section, (l3)... Bit shift section, (l4)... Selector section. In each figure, the same symbols indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)入力音声信号のゼロクロス点を検出する手段と、
ミユート信号が入力された直後の音声信号のゼロクロス
点から音声信号をゲートし、ミユート信号が終了した直
後の音声信号のゼロクロス点から音声信号のゲートを解
除するゲート開閉手段と、入力音声信号のレベルを所定
のレベルに下げる手段と、上記音声信号ゲート解除時か
ら一定区間後のゼロクロス点まで上記所定レベルに下げ
た音声信号を出力する切換え手段とを備えたミユーテイ
ング回路。
(1) means for detecting a zero-crossing point of an input audio signal;
Gate opening/closing means gates the audio signal from the zero-crossing point of the audio signal immediately after the mute signal is input, and releases the gate of the audio signal from the zero-crossing point of the audio signal immediately after the mute signal ends, and the level of the input audio signal. and switching means for outputting the audio signal lowered to the predetermined level from the time when the audio signal gate is released to the zero cross point after a certain interval.
JP16471189A 1989-06-27 1989-06-27 Muting circuit Expired - Fee Related JP2967783B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16471189A JP2967783B2 (en) 1989-06-27 1989-06-27 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16471189A JP2967783B2 (en) 1989-06-27 1989-06-27 Muting circuit

Publications (2)

Publication Number Publication Date
JPH0329530A true JPH0329530A (en) 1991-02-07
JP2967783B2 JP2967783B2 (en) 1999-10-25

Family

ID=15798435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16471189A Expired - Fee Related JP2967783B2 (en) 1989-06-27 1989-06-27 Muting circuit

Country Status (1)

Country Link
JP (1) JP2967783B2 (en)

Also Published As

Publication number Publication date
JP2967783B2 (en) 1999-10-25

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