JPH0784588A - Delay circuit - Google Patents

Abstract

PURPOSE:To efficiently initialize a memory by routing an input signal. CONSTITUTION:The digital data outputted from an A/D converter 10 are stored in the memory 12, and the data read out from the memory 12 are converted to an analog signal by a D/A converter 14. Then, by making the read data from the memory 12 the data written before a prescribed time, a prescribed delay signal is obtained. Then, when a delay time is revised by switching a mode, the input signal is muted by a switch 50, and the signal in a soundless state is written in the memory 12, and the memory 12 is initialized. Thus, the memory 12 is initialized surely with simple constitution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, a memory and a delay circuit using a D / A converter used for generating surround sound of an audio device.

[0002]

2. Description of the Related Art Conventionally, a surround sound of an audio device is generated by delaying a reproduced sound for a predetermined time and attenuating it. Then, there are a stadium mode, a church mode, etc. as a mode at the time of reproducing, and the reproduced sound delayed by different methods is superimposed.

As a delay circuit used for such a purpose, there is a delay circuit as shown in FIG. In this circuit, the analog reproduction signal is once converted into digital data by the A / D converter 10 and stored in the memory 12. In addition, the data read from the memory 12 is stored in the D / A converter 1
In 4, it is converted back into analog data. Then, in this circuit, the difference between the writing time and the reading time to the memory 12 becomes the delay time.

The A / D converter 10 includes an adder 2
0, a quantizer 22, a variable integrator circuit 24, and a control circuit 26, and the analog output of the variable integrator circuit 24 is fed back to the adder 20 to which the analog signal is input. The quantizer 22 converts the input signal into a 1-bit digital signal with a clock that is sufficiently fast for the input signal. The variable integrator circuit 24 integrates the output from the quantizer 22 to obtain an analog signal corresponding to the input signal. Since the output of the variable integrator circuit 24 is fed back to the adder 20, the difference between the two signals is taken in the adder 20, and in the case of an unchanged input signal, the quantizer 2
The output of 2 becomes a signal in which H and L are alternately repeated.

On the other hand, the control circuit 26 detects the output state of the quantizer 22 and changes the time constant in the variable integration circuit 24. That is, when the output level of the adder 20 is large and the output of the quantizer 22 is biased to one of "0" and "1", the time constant of the variable integrator circuit 24 is reduced and the output level of the adder 20 is changed. Small quantizer 22
When the output of is repeated "0" and "1", the time constant of the variable integrator circuit 24 is increased. With such control, the time constant is increased when there is no sound,
It is possible to suppress the generation of high-frequency noise, and to reduce the time constant when the input signal changes to sufficiently output a high tone.

On the other hand, the D / A converter 14 comprises a variable integrator circuit 28 and a control circuit 29. The pulse train type input signal read from the memory 12 is integrated by the variable integrator circuit 28 into an analog signal. Become. Here, the time constant in the variable integration circuit 28 is controlled by the signal from the control circuit 29. The control circuit 29 has the same configuration as the control circuit 26 described above. That is, the level of the input signal is detected and the time constant of the variable integrator circuit 28 is controlled accordingly. Since the input signal and the output signal of the memory 12 are basically the same, the variable integrator circuit 28 is controlled by such control.
The time constant of can be matched with the time constant of the variable integrator circuit 24, and the same signal as the input signal can be delayed by a predetermined time and output.

[0007]

In such a conventional delay circuit, when the delay time is changed to change the reproduction mode, the switch 16 is controlled to change the timing of reading from the memory 12. However, if the read timing is simply changed, the A / D side control and D /
The control on the A side cannot be made the same, and the delay signal becomes different from the input signal, resulting in a sense of discomfort. Therefore, in the conventional device, the switch 18 for prohibiting the output is provided on the output side, and the memory is initialized in the state where the output is prohibited.

However, in order to initialize the memory in this way, there is a problem that a circuit therefor is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a delay circuit capable of performing processing when changing a delay time without requiring memory initialization. With the goal.

[0010]

A delay circuit according to the present invention comprises an A / D conversion section for sequentially converting an analog input signal into digital data, and a memory for sequentially storing the digital data from the A / D conversion section. , Out of the data stored in the memory, the reading means for reading the data written before the predetermined time, the reading control means for controlling the data to be read by the reading means in accordance with the delay time command, and the memory A D / A conversion unit that sequentially converts the read data into an analog signal and outputs a delayed signal;
An input side switch provided on an input path of an analog signal to the A / D conversion section for controlling input of an input signal to the A / D conversion section, and a signal output provided on an output path from the D / A conversion section. An output side switch, and a control means for controlling the input side switch and the output side switch when the delay time is switched by the delay time command and prohibiting the input of the input signal and the output of the output signal for a predetermined time. It is characterized by having.

[0011]

As described above, the control means turns off the input side switch and mutes the input signal when the delay time is changed due to the change of the reproduction mode. As a result, silent data is written in the memory, and the memory can be initialized. Therefore, it is possible to achieve reliable memory initialization with a simple configuration.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the delay circuit of the embodiment, which has a switch 50 and a control circuit 52 provided in the input path of the analog input signal.

In the stadium mode or the like, since a reverberation in a wide space is required, a signal with a large delay time is created, and in the church mode or the like, a signal with a small delay time is created. Therefore, the read timing is changed by the switch 16.

When a mode switching signal is generated by a user's switch operation or the like, this mode switching signal is input to the control circuit 52. The control circuit 52 connects the switches 50 and 18 to the dummy terminal side and prohibits signal input and output. The dummy terminal has a reference potential that is the same as the bias level of the input signal. Then, in this state, the switch 16 is switched to change the data read timing. By changing the read timing, the delay time of the output signal with respect to the input signal is changed. That is, since the input signal converted into digital data is sequentially written in the memory 12, it is possible to obtain predetermined delay data by reading the data from the address where the data was written a predetermined time ago. Then, in the stadium mode or the like, since a reverberation in a wide space is required, a signal with a large delay time is created, and in the church mode or the like, a signal with a small delay time is created. Therefore, the read timing is changed by the switch 16.

Here, in order to change the read timing, it suffices to invert a predetermined bit of the address signal that determines the location for accessing the memory 12. That is, if the third bit of the signal of the write address is inverted, the address that has become 4 bits away will always be accessed.
Therefore, the switch 16 can be configured by a switch that controls whether or not to operate the inverter.

In the present embodiment, the switch 50 is operated to mute the data input prior to such switching of the switch. If there is no data input,
The output from the A / D converter is data that means no signal. This data is, for example, a constant signal in which "1" and "0" are alternately repeated. Therefore, by writing this data in the memory 12, the same effect as when the memory 12 is initialized can be obtained.

After such processing is completed, the switch 5
If 0 and 18 are turned on and A / D is started, A / D and D
It is possible to prevent the generation of an output that is uncomfortable to the listener due to the difference in conversion characteristics between / A and A.

[0018]

As described above, according to the delay circuit of the present invention, by muting the input signal,
The memory can be initialized. Therefore, the circuit for initialization becomes very simple, and its operation is ensured.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a delay circuit.

FIG. 2 is a block diagram showing a configuration of a conventional delay circuit.

[Explanation of symbols]

 10 A / D converter 12 Memory 14 D / A 24 Variable integration circuit 26 Control circuit 28 Variable integration circuit 16, 18, 50 Switch 52 Control circuit

Claims (1)

[Claims] 1. An A / D converter that sequentially converts an analog input signal into digital data, a memory that sequentially stores digital data from the A / D converter, and a predetermined time of the data stored in the memory. The reading means for reading the previously written data, the reading control means for controlling the data read by the reading means according to the delay time command, and the data read from the memory are sequentially converted into analog signals. A D / A converter that outputs a delayed signal; an input-side switch that is provided in an analog signal input path to the A / D converter and that controls input of an input signal to the A / D converter; The switch on the output side provided on the output path from the D / A converter and for controlling the signal output, and the switch on the input side when the delay time is switched by the delay time command Controls preliminary output side switch, delay circuit and having a control means for prohibiting the output of the input and output signals of a predetermined time only the input signal.