JPH03290958A - Optical information processor - Google Patents

Abstract

PURPOSE:To realize an optical neurocomputer, e.g. an integrated dynamic neurochip, by providing a floating gate under a control gate of a variable- sensitivity photodetector and by adding a memory function thereto. CONSTITUTION:A floating gate 2 is provided under a control gate 1, and when an incident light is made to enter a depletion layer region 7 through transparent electrodes of the gates 1 and 2 by a metal electrode 6, a photocurrent is generated. In the case of writing, a positive high voltage is applied to the gate 1 and an N-type drain 4 and moreover the amplitude of the voltage applied to the drain 4 is varied. Thereby the amount of storage of a charge on the gate 2, i.e., a gate voltage, is varied and also execution of a multistage control is enabled. In the case of erasure, electrons are extracted by applying a high voltage between the drain 4 and the gate 1 and further a higher voltage is applied after the erasure. Then the photocurrent flows through the gate 2 in accordance with the amount of the stored charge and thereby a state of 1 is brought forth. By such a process as stated above, electric adjustment of sensitivity is enabled and an optical neurocomputer can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a variable sensitivity photodetector having a memory function suitable for optical neurocomputing.

[Conventional technology]

Figure 3 shows, for example, Quantum Electron.
ics magazine, 1989, Vol. 25, No. 5, p. 896~
903 is a configuration diagram of the variable sensitivity photodetector shown on page 903. FIG.

In the figure, (la) is a polysilicon transparent electrode, (
3a) is a silicon oxide insulating film, (6) is a metal electrode, (
4a) is a P-8, and (5a) is an N81 substrate.

Figure 4 shows Transactions on Elect.
ron Devices magazine, 1986, No. ED-33
EEPRO shown in Vol. 6, pp. 835-844.
This is a configuration diagram of M, and in Figure 1, (1b) is a control gate, (2b) is a floating gate, and (3b) is a floating gate.
) is the field oxide film, (4b) is the n+-drain,
(11) is an n''-source, and (5b) is a P-substrate.

Next, the operation will be explained.

In Fig. 3, an MIs structure (Metal-In5ulator-
Sem1conductor). Electrode (1
When a negative bias voltage is applied to a), the insulating film (3a
) and the semiconductor (5a), a depletion layer is generated near the interface. Incident light passes through the polysilicon transparent electrode (1a) and enters the depletion layer from the vertical direction. The wavelength of the incident light is
5a) If the wavelength is shorter than the absorption edge wavelength of the material, a photocurrent (electron-hole pair) is generated in the depletion layer. The generated electrons are n
Type (5a).

It is collected by the P-n junction of the P-type (4a) semiconductor and taken out from the electrode (6). The magnitude of the photocurrent generated from this element is proportional to the thickness of the depletion layer, and the photocurrent increases as the thickness increases. In addition, the thickness of the depletion layer is determined by the electrode (
It is proportional to the magnitude of the bias voltage applied to 1a). Therefore, the element shown in FIG.

By applying a bias voltage to the electrode (1a), the photocurrent flowing through the element, that is, the sensitivity to incident light can be varied.

Figure 4 shows nine representative EEPROMs (elect
rically erasable and prog
A configuration example of rammable ROll) is shown.

ROM (read) is a memory that allows access to any address in any order, but whose main or only operation is reading.

11y meIIory). Further, a ROM that can be electrically erased and written is called an EEPROM. Writing is performed on the control gate (16) and drain (4).
A high positive voltage is applied to b) to generate hot electrons in the drain, which are injected into the floating gate (2b) from the drain side. As a result, the threshold voltage seen from the control gate becomes a high state ("0' state). When the gate voltage is less than the threshold voltage, the drain current becomes difficult to flow. Erasing starts from the source (5b) side. F-
Electrons are extracted by N (Flower-Nordheim) tunneling to create a "1" state with a low threshold voltage. For reading, a voltage is applied to the control gate (1b) to select a cell, and a sufficiently low voltage is applied to the drain so as not to generate hot electrons. '/'0' is read.

[Problem to be solved by the invention]

The conventional variable-sensitivity photodetector shown in Figure 3 is configured with one or more elements, so the device itself does not have a memory function, so when modulating the sensitivity, a voltage is applied to the control gate. There was a problem in that it was difficult to write data when forming an array.

This invention was made to solve the above problems, and aims to add a memory function to a variable sensitivity photodetector and to obtain an optical integrated circuit suitable for optical computing. do.

[Means to solve the problem]

The optical information processing device according to the present invention has a variable sensitivity photodetector having a Mis structure, and a floating gate is provided below the control gate.
It has a similar structure.

[Effect]

In the optical information processing device according to the present invention, the sensitivity is modulated according to the amount of charge accumulated in the floating gate by the EEFROM structure, and a nonvolatile memory function is added.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is a control gate made of a transparent polysilicon electrode to which a gate voltage V6 is applied. (2) is a floating gate electrode made of a transparent polysilicon electrode, which is attached in a floating state in an insulating film (3) of silicon oxide film. An n-type doped silicon semiconductor (4) is formed under the silicon oxide film (3). A drain voltage VI) is applied to (4).

(5) is a P-type doped silicon semiconductor substrate. (6) is an oxide film (3) on n-type silicon (4)
It is a metal electrode attached through the.

Next, the operation will be explained.

As shown in FIG. 1, input light enters the device from a vertical direction. As shown in the figure, the metal electrode (6)
Incident light passes through the transparent electrode and is incident only on the P-type substrate. When light enters the depletion layer region (7) shown in FIG. 1, a photocurrent T ph is generated. The current generation rate R is proportional to the depletion layer thickness d. Moreover, the depletion layer thickness d is the voltage V of the floating gate electrode (2)
It is proportional to p c. When VFo<O, there is no depletion layer at the interface between the P-type semiconductor (5) and the insulating film (3) (d
=o) and the photocurrent is 1. Production rate R1t of h, R=-
It becomes o. When VFG>0, the depletion layer thickness d increases in proportion to V Fc, and the relationship RCx-vFG holds true. First, a method of applying voltage to the floating gate will be explained.

The basic operation is similar to the principle of the EEPROM described above.

For writing, a high positive voltage is applied to the control gate (]) and the n-type drain (4) to generate hot electrons and inject them into the floating gate. At this time, by changing the magnitude of the voltage VG applied to the drain, the amount of charge accumulated in the floating gate, that is, the gate voltage VFG is changed. Furthermore, +VFG can be controlled in multiple stages by adding o as a constant pulse train. As a result, when v p c <O, a state in which no photocurrent of 1 ph flows (“O” state) is achieved. Erasing is done by connecting the drain (4) where writing was performed and the control
A high voltage is applied between the gates (1) and electrons are extracted by F-Nl- tunneling. After erasing is completed, when a larger voltage is applied, holes are injected into the floating gate (2) and Vpc>0, resulting in a photocurrent of 1. h flows and the state becomes 21'. Through the above writing and erasing processes, the sensitivity of the device shown in Figure 1 can be adjusted electrically, and since EEPROM is a non-volatile memory, it is possible to retain the information for a long period of time after it has been written. .

Note that in the above embodiment, (4) is an n-type drain (5).
Although a P-type substrate is shown in (4), the same effect can be expected even if an n-type substrate is used for the P-type drain (5). However, in that case, the voltages of V, , V, will be reverse biased, and the direction of the current will be reversed.

Furthermore, in the above embodiment, the case of a single n-type channel 7 and a p-type channel was explained, but as shown in FIG.
When the type and n-type channels are integrated next to each other, the CMO
Effects different from those of the above-mentioned embodiment of the 8-structure can be achieved. In Figure 2, first a P-type channel (4) is placed on an n-type substrate (5).
and provide a PMO8 structure. By forming a P-type well layer (10) on a substrate (5) and further forming an n-type channel.

A NMO5 structure is provided within the well. Set the above two gates and connect P-type and n-type channels (4) and (9).
Furthermore, the control gate (1) of PMO5NMO3
be electrically common.

When light is uniformly incident on this device, V. and v6
When a high positive voltage is applied to , NMO3 is written, ie, in the #0'' state, and PMO3 is erased.

21'' state. At this time, light is detected only on the PMO 5 side, and a positive current flows from the drain (4).

When a negative voltage is applied, the exact opposite situation occurs and a negative current flows from the drain (9).

Therefore, when this device is used, optical signals can be converted into positive and negative photocurrents by the gate voltage.

〔Effect of the invention〕

As described above, according to the present invention, since the photodetector is configured to have a variable sensitivity function and a memory function, it is possible to realize a device that realizes an optical neurocomputer, for example, an integrated dynamic neurochip. .

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a photodetector according to one embodiment of the invention, and FIG. 2 is a sectional view showing another embodiment. FIGS. 3 and 4 are sectional views showing conventional examples, respectively. (1) and (2) are the gate h, and (3) is the insulating film. In Figure 1, the same reference numerals refer to the same or corresponding parts.

Claims (2)

[Claims] (1) An optical information processing device comprising an EEPROM structure having a two-layer gate and electrically erasable and writable, and having a photodetection sensitivity variable by a voltage applied to the gate. (2) The optical information processing device according to claim 1, wherein the amount of charge applied to the electrically insulated gate is made variable, and the charge is accumulated in the gate.