JPH0329000A - Or circuit for serial data - Google Patents

Abstract

PURPOSE:To obtain a compact OR circuit with high reliability for serial data by executing OR with the serial data as they are without executing serial / parallel conversion. CONSTITUTION:Clock signals generated in a clock generating means 10 are inputted to a frame signal generating means 30 and counted and frame signals are generated. An arithmetic means 20 executes the OR of alarm (ALM) information, which are sent as the serial data from an ALM data bus, with the OR between input data in this time and ALM information up to the moment. Then, the value is held. When the ALM information of a magnetic field are inputted, the OR between the information held up to the moment and ALM information in the next time is executed and held. A clear signal generating means 40 delays a frame pulse and generates a pulse and the arithmetic means 20 is reset by the pulse. Thus, the OR can be executed without executing the serial / parallel conversion.

Description

[Detailed Description of the Invention] [Summary] Regarding the OR circuit of alarm information sent on a serial data bus, the alarm information sent as serial data can be serialized without serial/parallel conversion. The purpose is to provide a small-scale and highly reliable OR circuit for serial data by performing an OR operation on the data as it is, and a clock generation means for generating a clock signal and an alarm for the serial data input this time. an arithmetic means for logically ORing the information and the logical sum of the previous alarm information and holding that value; a frame signal generating means for counting the clock signal generated by the clock generating means and generating a frame signal; A clear signal generating means is provided for generating a reset pulse that resets the arithmetic means by delaying the frame signal generated by the frame signal generating means.

[Industrial application field]

The present invention relates to an OR circuit for alarm information sent on a serial data bus.

In a device composed of multiple interface panels,
There is an increasing number of systems in which various alarm information generated from multiple interface panels is transferred onto a serial data bus and collected on an alarm panel.

In such a method, the alarm information collected on the alarm panel is logically summed, and the output is used to light a light emitting diode,
Alarm information is displayed by operating the relay and driving other display means with its contacts.

There is a demand for a small-scale and highly reliable OR circuit for such alarm information. [Prior art] Fig. 4 is a diagram illustrating an example of the device configuration, and Fig. 5 is a diagram illustrating an example of a conventional example. FIG. 6 is a diagram illustrating a logical sum circuit for alarm information, and FIG. 6 is a diagram illustrating a time chart of a conventional logical sum circuit. Figure 4 shows an example of the device configuration, with an interface panel (
(hereinafter referred to as INF board) 101 to 10N and alarm board 201
An alarm (hereinafter referred to as ALM) data path, an address bus, and a cross signal are connected to each of them.

FIG. 5 shows a conventional logical sum circuit for ALM information. In this example, there are eight types of ALM information, ALM1 to ALM8, which are carried on ALM data buses DO to D7, and the number of INF boards is three. .

The circuit configuration of this conventional example includes an oscillator 11 that generates a clock signal, an address counter 32 that generates an address for identifying ALM information on an ALM data path, and eight types of ALM information that are manually input using serial data. , respectively perform serial/parallel conversion (hereinafter referred to as S/P conversion).
ALM from P conversion circuits 25a to 25h and three S/P converted interface boards
It consists of logical sum circuits (hereinafter referred to as OR circuits) 26a to 26h that calculate the logical sum of information.

FIG. 6 is a time chart of the operation of the above circuit,
Here, it is assumed that three INF boards 101 to 103 are installed, and there are three types of ALM information, ALMI to ALM3.

■ is the clock signal generated by the oscillator 11, ■ is the IN
This is an address signal for identifying Flxo1 to Flxo103, and address signals INFI to INF3 are repeatedly sent onto the address bus.

(2) is ALM information on each bus line, and indicates a situation in which the same type of alarm information is sent as serial data on the same bus line.

ALMi-j indicates ALM information i generated from the j-th INFI (for example, ALM1 is powered off, ALM2 is powered off, etc.).

■ ALM information 1 from INF boards 101 to 103 is S/
A signal that is S/P converted and latched by the P conversion circuit 25a (here, only ALMI is shown to avoid complication of the diagram).

■ is AL converted to parallel data and latched at ■
It shows an output signal obtained by logically ORing the M information in the OR circuits 26a to 26h.

This output signal lights up a light emitting diode (hereinafter referred to as LED) or operates a relay or the like to perform an ALM display.

[Problem to be solved by the invention]

In the conventional example described above, as the number of INF panels and the types of ALM information increase, the scale of the alarm panel increases in proportion to the product of the two.

The present invention creates a small-scale and highly reliable OR circuit for serial data by ORing the alarm information sent as a serial data without serial/parallel conversion. The purpose is to provide.

(Means for solving problems) FIG. 1 shows a block diagram illustrating the principle of the invention.

In the block diagram of the principle of the present invention shown in FIG. 1, 10 is a clock generation means for generating a clock signal, 20 is alarm information of serial data manually inputted this time,
It is an arithmetic means that calculates the logical sum with the logical sum of the previous alarm information and holds the value, and 30 is a frame signal generating means that counts the clock signal generated by the clock generating means 10 and generates a frame signal. 40 is a clear signal generating means for generating a reset pulse that resets the arithmetic means 20 by delaying the frame signal generated by the frame signal generating means, and by providing such means, the present problem can be solved. Use it as a means to solve the problem.

[For production]

The ALM information is input as serial data in synchronization with the clock signal generated by the clock generating means IO. Further, the clock signal generated by the clock generation means 10 is manually inputted to a frame signal generation stage 30, and a frame signal is generated by counting the clock signal. This frame signal indicates a reference position for ALM information.

The calculation means 20 performs a logical OR operation between the current input data of the ALM information stored as serial data from the ALM data path and the logical sum of the previous ALM information.
retain its value.

When the next ALM information is input, the information held until then is logically ORed with the next ALM information and held. Thereafter, in the same manner, the ALM information input manually one after another is logically ORed with the information held up to that point, and the value is held.

The clear signal generating means 40 generates a pulse by delaying the frame pulse, and the calculating means 20 is reset by the pulse.

By arranging as described above, it is possible to logically OR the ALM information sent as serial data without converting it into parallel data.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a diagram for explaining an embodiment of the present invention, and FIG. 3 is a diagram for explaining a time chart of the embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 uses three D as the clock generating means 10 explained in FIG.
Flip-flop circuit (hereinafter referred to as FF circuit) 21A
, 21B, a logical sum circuit (hereinafter referred to as an OR circuit) 22A, whose inputs are the output of the DFF circuit 21A and the input ALM1, and whose output is connected to the input terminal of the DFF circuit 21A. and three D for holding the output of the OR circuits 22B, 22C and the FF circuit 2l for one frame, which are connected in the same way.
FF circuit 23 consisting of FF circuits 23A, 23B, and 23C
, a frame counter 3 that counts clock signals and generates frame pulses as a frame signal generation means 30;
1, an address counter 32 that generates an address for identifying the address of ALM information from a frame pulse and a clock signal, an INV4 1 that inverts the frame pulse as a clear signal generating means 40, and a delay circuit 42. It is.

In this embodiment, as in the conventional example, the INF board has 10
Three types of ALM information: 1 to 103, ALMI to AL
We will explain the operation of the three types of M3. Figure 3 is a time chart of the operation of the circuit described above, (1) is the clock signal generated by oscillator l1, (2)
is a frame pulse generated by counting the clock signal (1) with the frame counter 3l, (3) is a frame pulse generated by inverting the frame pulse by INV41,
A clear pulse for clearing the FF circuit 21 delayed by the delay circuit 42; (4) an address signal for identifying an address generated by counting the frame pulse and clock signal by the address counter 42; 5) is the ALM+¥4 report sent from the INF boards 101 to 103 on the ALM data path, and ALMi-j has the same content as the conventional example.

(6) is the output of the FF circuit 2l, which is first cleared by the clear pulse (3).

In this state, ALMI is input to the OR circuit 23A, and F
It is input to the F circuit 2l. Since the inverted clock signal is input to the clock terminal of the FF circuit 21,
ALM1 is output with a delay of half a cycle of the clock signal.

ALMI-1 delayed by half a cycle of the clock signal is input to one terminal of the OR circuit 23A, and then ALMI-1 is input to one terminal of the OR circuit 23A.
-2 is input to the other input terminal, OR circuit 23A
Therefore, the logical sum of ALM1-1 and ALMI-2 (hereinafter (
ALMI-1+ALMl-2)) is taken, and D
It is input to the input terminal of the FF circuit 21A.

Here, when a clock signal is input, (ALMl-1
+ALM1-2) is output to the output terminal of the DFF circuit 21A. Output of DFF circuit 21A (ALMI-1+ALMl-2
) is manually input to one terminal of the OR circuit 23A, and then ALMI-3 is input to the other input terminal, the OR circuit 23A calculates the logical sum of (AL.M1-1+ALM1-2) and ALMI-3. (ALMI-1+ALM1-2+
ALM1-3) are taken and input to the DFF circuit 21A.

Similarly, with the next clock signal (ALMI-1+AL
M1-2+ALM1-3) is output to the output terminal of the DFF circuit 21A.

(7) Output of DFF circuit 21A (ALMI-1+ALM
I-2+ALM1-3) is input to the DFF circuit 23A,
By punching with a frame pulse, the OFF circuit 23
To the output terminal of A (ALMI-1+ALM1-2+ALM
1-3) is output and that value is held until the next frame pulse arrives. The above is only about ALMt-j, but ALM
The operation is exactly the same for ALM 2-j and ALM 3-j.

By taking precautions as described above, it is possible to logically OR the ALM information input as serial data without converting it to parallel data, making the circuit scale small and highly reliable. I can do it.

For example, when there are 20 INF@ sheets and 8 types of ALM information, when constructing a circuit using a general commercially available IC, using the circuit of the present invention will result in a 1/2
The scale can be less than 10. [Effects of the Invention] According to the present invention as described above, it is possible to provide an OR circuit that is small in circuit scale and highly reliable for ORing ALM information input as serial data.

[Brief explanation of drawings]

Figure 1 is a block diagram explaining the principle of the present invention, Figure 2 is a diagram explaining an embodiment of the invention, Figure 3 is a diagram explaining a time chart of an embodiment of the invention, and Figure 4 is an apparatus. FIG. 5 is a diagram illustrating a conventional OR circuit for alarm information; FIG. 6 is a diagram illustrating a time chart of a conventional OR circuit. In the figure, 10 is a clock generation means, l1 is an oscillator, 12 and 41 are inverters, 20 is arithmetic means, 21, 21A to 21C, 23A to 23C are FF circuits, 22A to 22C 126a to 26h are O 25a to 25h are S/ 30 is a frame signal generating means, 31 is a frame counter, 32 is an address counter, 40 is a clear signal generating means, and 42 is a delay circuit. R circuit, -. ．． −． ．． ．． −． −． --------． ．． −． ．． −(−
．． Otsu-0----------------
Figure M2 for explaining the embodiment of the present invention Figure 1 Block diagram for explaining the principle of the invention Figure 1 JIJ Figure Figure 4 for explaining an example of the device configuration

Claims (1)

[Claims] A logical sum circuit for alarm information sent on a serial data bus, comprising clock generation means (10) for generating a clock signal, alarm information of serial data input this time, and the clock generation means (10) for generating a clock signal. arithmetic means (20) for calculating the logical sum with the logical sum of the alarm information up to and holding the value; and a frame signal generating means for counting the clock signal generated by the clock generating means (10) and generating a frame signal. means (30); and clear signal generation means (40) for generating a reset pulse that resets the calculation means (20) by delaying the frame signal generated by the frame signal generation means (30). A serial data OR circuit characterized by: