SU1716455A1 - Signal simulator - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in radar operators simulators. The purpose of the invention is to improve the accuracy of simulation - by forming partial radio pulses of a group target by cutting out from the output continuous harmonic oscillations M generators of rectangular radio pulses of a given duration with the required mutual displacement in time. 2 hp f-ly, 3 ill.

Description

The invention relates to automation and computer technology and can be used in the educational process of universities to demonstrate methods of super-relay resolution of radar targets, digital methods for measuring their coordinates, in radar operators simulators for training personnel, in experimental installations for scientific research.

The purpose of the invention is to improve the accuracy of imitation.

FIG. 1 shows a functional diagram of the proposed device; in fig. 2 and 3 are variants of the functional diagrams of a setup signal forming unit.

The simulator contains a clock generator 1, M radio frequency generators 2.1 - 2.m (, 3, ..., Yu, adder 3, the first driver of the echo signals including the first register 4, the first trigger 5, the first element OR 6, the first counter 7, the first element and 8,

second register 9, DOW inverter second element AND 11, second element OR 12, second trigger 13, second counter 14 AND switch 15, M-1 driver: echo signals in register 16, first element AND 17, first element OR 18, the first TT of the 19, the first counter 20, the inverter 21, the second element AND 22, the second element OR 23, the second trigger 24, the second counter 25, the switch 26, the setting signal generating unit 27.

The installation signal shaping unit 27 comprises a trigger, a delay block of an even number of inverters and a differentiating circuit (FIG. 2) or a delay block of an odd number of inverters and an OR element — NOT (FIG. 3).

The simulator of radar signals works as follows.

In the initial state, the absolute time delay code of the first simulated signal is fed to the information input D of the first register 4 of the first echo shaper

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(TK 1 in Fig. 1), and the information inputs D of registers 16 of all the remaining M-1 drivers are codes for the time shifts of the echo signals generated by them (TK t) relative to the output signal of the first driver. In addition, the information input D of the second register 9 of the first generator receives the code of the duration of the echo signals (TI in Fig. 1), which is common to all the simulated targets. The clock generator 1 forms a clock pulse sequence, and each of the M radio frequency generators 2.1 - 2.t (, 3, ..., H) is a continuous harmonic signal. On the first and second control inputs of the simulator (N.Ust. And Dis. In Fig. 1), the signals are set to zero

level I

The initial installation of the device is carried out by issuing a pulse signal N. Ust to its first control input. (Initial setting of the unit level. In this case, the registers 4, 9, 16 record the codes assigned to their information inputs D, and the first trigger 5 of the first Shaper is set to one. As a result, the unit level signal from the direct output of the specified first trigger 5 through the first element OR 6 acts on the control input U of the first counter 7 of the first driver, switching the counter 7 to the parallel loading mode of the counting coefficient on its input D parallel loading. In addition, the signal of ur From the direct output of the first trigger 5, the input goes to the combined first inputs of all the other elements of the OR device and then to the corresponding installation inputs of the other triggers of the simulator (13, 19 and 24 in Fig. 1), also setting them to the single state. the rest of the simulator counters are switched to parallel loading mode, and the switches 15, 26 connected to the direct outputs of the second triggers 13 and 24 are in the open state. The zero potential from the inverse output of the first trigger 5 of the first Shaper blocks the passage through the first element And 8 pulses of a single level from the output.

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counter 7, with the result that a zero potential is applied to the first installation input of the first trigger 19 of the first shaper and the second trigger 13 of the first shaper.

The arrival of each of the next clock pulse at the clock inputs of counters 7,14,20,25 leads to a reset in them of the coefficients of the invoices issued to their inputs of parallel loading from the outputs of the corresponding registers 4,9,16. In this state, the simulator can stay for an arbitrarily long time until its second control input receives a pulse signal of a single resolution level of the imitation Dis. (Resolution). With its arrival, the first trigger 5 of the first driver is shifted to the zero state, transferring the first counter 7 to the counting down mode (zero potential is set at the control input of the U 5 counter). Subsequently, with the arrival of the next clock pulse at the clock input C, the state code of the first counter 7 is successively reduced, reaching its minimum value, with the result that a single level pulse that passes through the first element II 8 occurs at its output, the end of the count (at the inverse trigger output 5 in the zero state, the signal has a single potential). This pulse through the first element OR 6 enters the control input U of the counter 7, transmits information to it. In addition, the second trigger 13 of the first driver is shifted to the zero state by the same pulse. In order to guarantee switching of the trigger 13, an inverter 10 is used, the zero output signal of which blocks the passage of the second trigger input 13 to the second installation input. Account countdown from the corresponding output of the second counter 14. With the trigger 13 switching to the zero state, the counter 14 switches to the counting mode for decreasing At the same time, the switch 15 closes and the harmonic signal passes to its output - the front of the first of the simulated radio pulses is formed. In the zero state, the second trigger 13 is held until the counter 14 counts

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em code TI radio pulse loaded in it. When this moment comes, the impulse Ending a single-level count from the output of the second counter 14 passes through the second element 11 and the second element OR 12 to the second installation input of the second trigger 13, transferring it to the single state. As a result, THIS switch 15 is disconnected, forming a cut of the radio pulse of the first source, and at the same time counter 14 is again switched to parallel loading mode, in which it will remain before the appearance of the count end output of the first counter 7 of the next impulse of a single level.

In parallel with the beginning of the formation of the radio pulse of the 1st source by the leading edge of the pulse. The counting of the counter 7 of the 1st generator

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all first triggers 19 of the remaining M-1 drivers are flip to the zero state. At the same time, their first counters 20 are transferred to the counting mode for decreasing, measuring the specified time delays of the m-th (, 3, ..., M) echoes relative to the start of the radio pulse of the first source. Upon completion of the counting of a given number of clock pulses at the output. The end of the counting of the first counter of the 20th m (, 3, ..., M) generator appears the corresponding impulse of a single level that passes through its first element AND 17, the first element OR 18 at the second setup input of the first trigger 19, switching it to the alternate state, and at the forward output of the first trigger 19, a single potential occurs, transferring the first counter 20 again to the parallel loading mode. At the same time, under the influence of this single difference at the direct output of the first flip-flop 19, the setting signal generating unit 27 outputs a single-level impulse to the second set input of the second flip-flop 24, transferring it to the zero state. The zero difference that occurs at the forward output of the trigger 24 is transformed on the switch 26 to the front of the radio pulse of the m-th simulated source and, in addition, translates the second counter 25 from parallel loading mode,

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in which it was in the initial state, in the counting mode to decrease. Next, the second counter 25 measure -; the duration of the TI of the echo signal of the g-th source. Upon completion of counting the specified number of clock pulses on the output. The counting of the second counter 25 TGTS of the former is set to a single level pulse, the leading edge of which passes through the second element AND 22, the second element OR 23 to the first installation input of the second trigger 24, returning it to its original state . The differential of the unit level arising at the direct output of the second trigger 24 causes the counter 25 to be in parallel loading mode and is simultaneously transformed by the switch 26 into the cut of the radio pulse of the m-th (m 2, 3, ..., M) source.

With the appearance of the next pulse, the end of the counting at the corresponding output of the first counter 7 of the first driver, the described operation process is repeated. As a result, a sequence of radio pulses with specified parameters is formed. The adder 3 provides sewage of all M formed echo signals on a common cable.

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Claims (3)

1. Simulator of radar signals, containing a clock-generator. the torus, the adder and the first driver of the echo signals, which includes two registers, two triggers, the OR element, the switch and the first counter and the element I, in series, are connected in series with the purpose of increasing Imitation accuracy, M radio frequency generators, M-1 echo signal drivers were introduced, containing two triggers, two counters, a register, a switch, two OR elements, two AND elements, an inverter and a setup signal generating unit, and the first driver echo signals are entered the second element OR, the second counter, sec second AND gate and an inverter, the output of the clock generator is connected to the combined clock WMOs rows of first and second counters of all formers echo register inputs of which are data inputs of the simulator, the first The simulator's control input is the combined first setup input of the first trigger of the first echo generator and the control inputs of all registers, and the second control input of the simulator is the second setup input of the first trigger of the first echo generator, the output of the first register of which and the register outputs the remaining M-.1 drivers are connected to the inputs of parallel loading of the corresponding first counters and drivers of echo signals, and the combined inputs of parallel loading of the second account The signals of all M echo shapers are connected to the outputs of the second register of the first shaper of the echo signals, the direct output of the first trigger of which is connected to the combined first inputs of all the first and second OR elements, in the first shaper of the echo signals the output of the first OR element is connected to the control the input of the first counter, the second input of the first element And is connected to the inverse output of the first trigger, and the output of the first element And is connected to the second input of the first element OR, the input of the inverter, the first installation input of the second trigger and with the combined first installation inputs of the first triggers of all the remaining M-1 echo drivers, in all the echo drivers, the direct outputs of the second triggers are connected to the combined control inputs of the second counters and switches, the outputs of the second count counters are connected to the first inputs of the second elements And, the second inputs of which are connected to the output of the corresponding inverter, the outputs of the second elements And connected to the second inputs of the second elements OR, the output of which is The emitter of the echo signals is connected to the second setup input of the second trigger, and the outputs of the second OR elements in the remaining M-1 echo signals are connected to the first setup input of the second trigger, respectively, the inputs of the H-switch of the echo signal generator are connected to the output of the corresponding The M-go of the radio frequency generator, and the outputs of all the switches are connected to the inputs of the adder, the output of which is the output of the simulator, with this is in each M-1 echo shaper, besides the first one, the output of the first element OR is connected to the second setup input of the first trigger, the direct output of the first trigger connection 5 is not the control input of the first the counter and the input of the forming unit of the setup signal, the inverse output of the first trigger is connected to the first input of the first element AND, the second input of which is connected to the output of the counting of the first counter, the output of the first element AND is connected to the second input of the first element OR The signal is connected to the second setup input of the second trigger and to the input of the inverter. 2. The simulator according to claim 1, characterized in that the block for generating setup signals contains a trigger, a delay block and differential v: raiding circuit, whose input is the input of the block, and the output is connected to the first setup input of the trigger and through the delay block - with the second trigger setup input, exit. which is the output of the block, and the delay block consists of an even number of series-connected about inverters. 3. The imitator according to claim 1, characterized in that the block for forming setup signals comprises a delay block and an OR-HHO element, 5, the combined inputs of which are the input of the block, and the output of the delay block is connected to the second input of the OR-NOT element, the output of which is the output of the block, the delay block consisting of an odd number of inverters connected in series.