JPH03289789A - Encoder and decoder - Google Patents

Abstract

PURPOSE:To accelerate coding processing and decoding processing by completing readout when an address shows the one in which the last non-zero coefficient exists in a block and attaching an EOB(END OF BLOCK) code when a conversion coefficient in the block is coded. CONSTITUTION:When the conversion coefficient is written on memory 101, the coefficient in the block is written according to constant sequence, and also, it is decided whether the conversion coefficient to be written is zero or non-zero by a non-zero coefficient decision means 102, and when the conversion coefficient is the non-zero coefficient, the address is stored in a non-zero coefficient address storage means 104. When the conversion coefficient in the block is coded, the conversion coefficient in the block is read out from the memory 101 sequentially, and it is compared with the address stored in the non-zero coefficient address storage means 104 by an address comparison means 105, and the readout is completed when the address shows the one in which the last non-zero coefficient exists in the block, and the EOB(END OF BLOCK) code is added. In such a way, the coding processing and the decoding processing can be accelerated.

Description

Detailed Description of the Invention Field of the Invention The present invention relates to an encoding device and a decoding device for image data, and in particular to an encoding device and a decoding device in a variable length encoding system that encodes the number of consecutive zeros and non-zeros. Conventional technologyAs a still image encoding method, focusing on the fact that data within an image has a correlation, the image data is divided into blocks of N x N pixels, and the image data is divided into blocks of N x N pixels. Performs orthogonal transformation such as discrete cosine transformation m (DCT) on the data in the block.
There is a method for encoding and compressing the transform coefficients. Figure 12 shows the characteristics of the transform coefficients of the discrete cosine transform.

Figure 12 i: Transform coefficients when discrete cosine transform is applied to pixels in a two-dimensional block of LN×N,
The shaded area is the part with large numbers. This is the method for quantizing and encoding such transform coefficients. Transform coefficients j of blocks with many low frequency components & Large numbers are concentrated in the upper left of the block. The transform coefficients are arranged in one dimension, and the number of consecutive zero coefficients and non-zero coefficients are encoded for the transform coefficients arranged in the - dimension.The encoding process will be explained below. Indicates the scanning direction when encoding the transform coefficients obtained by orthogonally transforming the block. Encoding method ζDai Scan and arrange the transform coefficients in one dimension as shown in Fig. 5, and encode the number of consecutive zero coefficients and non-zero coefficient values for the transform coefficients arranged in this − dimension as shown in Fig. 6. In a case like this, that is, when the conversion coefficients are arranged in one dimension ☆
If the coefficient is zero after the non-zero coefficient in the part of the block, coding is performed after the non-zero coefficient in the part with ☆, f, EOB.
(End Of Block) Add code
FIG. 8 shows encoded data when the blocks in FIG. 6 are encoded.

Next, the decoding process (decoding process obtains the number of consecutive zero coefficients and non-zero coefficient values from the encoded data. If there are zero coefficients, write zeros for that number into the coefficient memory, and If it is a coefficient, write the non-zero coefficient value L
Even if it is an EOB code (writing zero coefficients until the end of the L block is a problem that the French invention attempts to solve), however, in the above still image encoding method & above 1) there is a high probability that the transform coefficients in the high frequency part are zero, Even though the zero coefficients are considered to be continuous, when encoding coefficients with a high probability that the last non-zero coefficient in the block is like this, read out all the zero coefficients after the last non-zero coefficient in the block, and then write them to the end of the block. If the EOB code was added, one block of coefficients would have to be read out at all times. 1. Processing speed could not be increased. % Also
When the number of consecutive zero coefficients exceeds a certain number, the power to divide the code into multiple zero runs (if such a zero run occurs at the end of the block, multiple zero run codes are EOB)
2) Writing data to coefficient memory during encoding process,
Alternatively, if you try to read data in an arbitrary scanning direction, you will need a buffer memory and the processing speed will be slow. (4) Writing data to coefficient memory during decoding processing,
Alternatively, if data is read in an arbitrary scanning direction, a buffer memory or the like is required, which slows down the processing speed. Means for solving problems even if the purpose is to provide a decoding device The present invention is directed to achieving the above objects.The present invention provides a memory for storing at least data in a block, and whether the transform coefficients are zero coefficients or non-zero coefficients. non-zero coefficient determination means for determining the conversion coefficient; address generation means for generating an address to be stored in the memory when writing the conversion coefficient into the memory; and non-zero coefficient address storage means for storing the memory address to write the non-zero coefficient. The encoding device is equipped with address comparison means for comparing the address stored in the non-zero coefficient address storage means and the address read from the memory, and in addition thereto, it is equipped with an address conversion means for converting the address generated by the address generation means. The encoding device also includes a memory for storing at least data in a block, an address generating means for generating an address to be stored in the memory when writing a transformation coefficient into the memory, and a memory address for writing a non-zero coefficient. a non-zero coefficient address storage means for comparing the address stored in the non-zero coefficient address storage means with an address read from the memory; and an address comparison means for comparing the address stored in the non-zero coefficient address storage means and the address read from the memory, and selecting whether the output is the content stored in the memory or zero when outputting the coefficient data. The present invention has the above-described structure. When encoding the transform coefficients, write them into the memory in a fixed order, and at the same time, use a non-zero coefficient determining means to sequentially determine whether the written transform coefficients are zero or non-zero. If the conversion coefficient is a non-zero coefficient, its address is stored in the non-zero coefficient address storage means, and the address where the last non-zero coefficient exists in the data read direction in the block is stored. During encoding, the transform coefficients in the block are sequentially read out from the memory, and the address comparison means compares them with the address stored in the non-zero coefficient address storage means to determine the address where the last non-zero coefficient exists in the block. When this happens, the readout is finished and the EOB code is added.Also, the address given when writing the conversion coefficient to the memory and when reading it are made different depending on the address conversion means.
The present invention also enables writing and reading in any scanning order.If an EOB code is detected during decoding, data from that address onwards is written to the memory.Writing to the memory is completed and that address is stored as an address. When reading the coefficients from the memory, the address comparing means compares the address stored in the non-zero coefficient address storage means with the address to be read, and the address stored in the non-zero coefficient address storage means is reached. The output is switched by the data selection means and zero coefficients are read from that address onward.

In addition, the addresses given when writing conversion coefficients to memory and when reading them are made different depending on the address conversion means,
Embodiment of the present invention in which writing and reading can be performed in an arbitrary scanning order Hereinafter, the present invention will be explained in detail with reference to the drawings.Go to FIG. 1. A block diagram of an encoding device in a first embodiment of the present invention is shown. . In the figure, 101 is a coefficient memory that stores read data at a predetermined address, and 102 is a zero coefficient detection block 103 that detects whether the read coefficient data is a zero coefficient or a non-zero coefficient, and stores the coefficient data in the coefficient memory 101. 104 is a register that stores the address of the last non-zero coefficient when reading out in a certain order in the block to be encoded; 105 is a register stored in the coefficient memory 101; A combiner 106 that compares the address read from the coefficient memory 101 and the address stored in the register 104 when encoding the coefficient data stored in the coefficient memory 104 is the output of the zero coefficient detector 102, and the output is a non-zero coefficient. If so, the address specified by the address generator 103 is stored in register 1.
04, and the output of the comparator 105 causes EOB to be stored in EOB when encoding the coefficient data.
Timing system @f that controls the timing of code output
E, 107 is an encoding unit that encodes the coefficient data read from the coefficient memory 101.The circuit operation of FIG. 1 will be explained in detail below.First, the coefficient data is read,
Write to the coefficient memory 101 The address for writing the coefficient data can be given from the address generation unit 103. In this case, the address generation order is the order shown in FIG. 5. This is the low frequency component after orthogonal transformation. This is because the conversion coefficients of blocks with many values are concentrated in the upper left corner of the block. At this time, the zero coefficient detection unit 102 detects whether the read coefficient is a zero coefficient or a non-zero coefficient. If the coefficient is non-zero, the timing control unit 106
The address of the address generation unit 103 is sent to the register 104 according to the control signal from the timing control unit 106.
If the coefficient data to be stored is a non-zero coefficient, the address is newly stored in the register 104. Therefore, all the data of one block is stored in the coefficient memory 101. 101, even if the register 104 stores the address of the part of the coefficient data stored in the coefficient memory 101 in which the last non-zero coefficient exists in the order in which it should be stored, for example, the coefficient data in the block Even if it is the data shown in Figure 6 (as soon as all the coefficient data in the block is written to the coefficient memory, register 1
Even though 04 has the address of the ☆ part, if all the coefficients in the block are written to the coefficient memory 101 in this way, then the coefficients are read out from the coefficient memory 101 and encoded by the encoding unit 107. reads the coefficient data sequentially from the coefficient memory 101. If the address stored in the register 104 (the address in the ☆ part) matches the address in the address generation unit 103, then
The comparator 105 informs the timing control unit 106 of this fact, and the timing control unit 106
After finishing reading from 01, the encoding unit 107 reads EO
When the B code is added and this EOB code is added, the encoding process for one block is completed. Once the encoding of one block is completed, the next block is processed. In this example, one block is 8x8. Since the image is composed of dot pixels, it is necessary to process 10,240 blocks to process an image of 640 dots vertically and 1024 dots horizontally.According to this embodiment, the encoding processing time is Since the zero coefficients after the last non-zero coefficient can be encoded without reading them from the coefficient memory, the number of data to be read can be reduced and the speed of the encoding process can be increased. 2 shows a block diagram of a decoding device in FIG.
is an address generator a that generates an address for the coefficient memory 202; 204 is a selector that selects the coefficient read from the coefficient memory 202 and zero; and outputs either one as coefficient data; 205 is a block to be decoded;
A register 206 stores the address of the last non-zero coefficient when reading out in a certain order. Reference numeral 206 indicates the address and register read from the coefficient memory 202 when decoding the coefficient data stored in the coefficient memory 202. 207 is a timing control unit that compares the addresses stored in 205.The circuit operation of FIG. 2 will be explained in detail below. The coded data is read and decoded by the decoding unit 201.The decoded coefficient data is written to the coefficient memory 202.The address given to the coefficient memory 202 is generated by the address generation unit 203. In this embodiment, coefficient data is written into the coefficient memory 202 in a fixed order as shown in FIG. After writing in the prescribed order and memorizing the non-zero coefficients of the partial addresses marked with ☆ in FIG. is stored, but at this point the coefficient memory 2
02ζ Even if the state shown in Figure 7 is reached, the areas marked with an x in Figure 7 are areas where no writing has been done and the previously recorded information remains as is, or the total heat data is recorded. The power that is in the state where the At this time, the coefficient data of the coefficient memory 202 is sequentially read out until the address of the ☆ part stored in the register 205 and the address given to the coefficient memory 202 by the address generation unit 203 match, and if they match, the comparator 206 indicates that The timing control unit 207 gives a select signal to the selector 204 to select a zero coefficient, and controls the addresses after the ☆ part to read zero.
Even if it is filled with all zero data, in this way EOB
The decoding process for one block is completed by replacing the code with zero data. When the decoding for one block is completed, the process proceeds to decoding the next block and repeats the same operation.

In this embodiment, the decoding process is limited. Since the zero coefficients after the last non-zero coefficient in the block to be decoded can be decoded without writing them to the coefficient memory, the number of data to be written can be reduced and the speed of the decoding process can be increased. 4. Next, a block diagram of the encoding device according to the third embodiment of the present invention is shown in FIG. Coefficient detection starvation 30
3 is an address generator that generates an address for the coefficient memory 301; 304 is an address converter a that converts the address generated by the address generator 303 into a different address;
305 is a select register for selecting either the address generated by the address generation unit 303 or the address converted by the address conversion unit 304; 306 is a register register for storing the address converted by the address conversion unit 304; and 307 is a register stored in the register 306. A timing controller 308 compares the address with the address specified by the address converter 304.The circuit operation of FIG. 3 will be explained in detail below.Coefficient data is read into the coefficient memory 30
Write to 1 a The address to write is the address generator 30
Assuming that the address generation order in this case is as shown in FIG. 9, the address converter 304 converts the address into the zigzag scan address in FIG. 1O. Specifically, for example, in FIG. If the address of is 8, the address is converted to 2 as shown in FIG.
It detects whether it is a non-zero coefficient, and if it is a non-zero coefficient, it notifies the timing control unit 308 of that fact, and according to the control signal from the timing control unit 308, the address of the address conversion unit 304 is fetched into the register 306. The coefficient data in the block to be encoded is written to the coefficient memory 301, and if there is a non-zero coefficient, the address of the non-zero coefficient is converted by the address conversion unit 304 and the address stored in the register 306 is converted. The comparator 307 compares the address, and if the address specified by the address conversion unit 304 is larger than the address stored in the register 306, the address of the new non-zero coefficient is stored in the register 306.More details about address conversion Description: Here, we will explain the operation when the coefficients in a block are as shown in FIG. 9. First, the data in FIG. 9 is written into the coefficient memory 301 in the scanning order shown in the drawing. This is because the orthogonally transformed coefficient data is generally output in the form shown in Figure 9.In accordance with the data writing, address 7 in Figure 9 is a non-zero coefficient. The register 306 contains the address 28 after conversion.
is stored, but when scanning is performed in the order shown in Figure 9, the address of the next non-zero coefficient is 16. In this case, the address after conversion is 3 in Figure 10. Therefore, 28>3. Therefore, the register 306 is not updated and remains 28. Comparison and judgment of this address are performed by the comparator 307. In this way, all the coefficient data shown in FIG. 9 are stored in the coefficient memory 3.
Even though the register 306 has 28 addresses at the time of writing to 01, all the coefficients in the block are written to the coefficient memory 301 in the scanning order shown in FIG.
The register 306 contains the address of the last non-zero coefficient in the block when scanning in a zigzag manner as shown in Figure 10.
Next, in order to encode the data stored in the coefficient memory 301, the coefficient data is read out from the coefficient memory 301 in the scanning direction shown in FIG. 1O. The subsequent encoding operations are the same as those in the first embodiment, so they are omitted here. Coefficient data can be imported in accordance with the output format of the part before the data is output, and there is no need for a buffer memory, etc., which speeds up the encoding process.In this embodiment, the coefficient data is written horizontally serially. (Another method, for example, writing vertically and serially, can be easily realized without changing the configuration of this embodiment. In this embodiment, the address of the last non-zero coefficient in the block is Coefficient memory 3 for judgment
Comparator 30 that determines the end of reading from 01
Figure 4 shows a block diagram of a decoding device according to a fourth embodiment of the present invention. 402 is a coefficient memory, 403 is an address generator ff1L that generates an address for the coefficient memory 402, 404 is an address conversion unit that converts the address generated by the address generation unit 403 into a different address, and 405 is an address generation unit 403. A select register 406 selects between the generated address and the address converted by the address converter 404. A register 407 stores the address converted by the address converter 404. 407 refers to the address stored in the register 406 and the address converter 404.
Compare the address specified by 408
409 is a timing control section.
The circuit operation in Fig. 4 will be explained in detail.
We will explain the process of decoding the coded data obtained by coding the coefficient data in Figure 0. First, read the coded data,
The decoded coefficient data decoded by the decoding unit 401 is written to the coefficient memory 402. The address given to the coefficient memory 402 is the 9th address generated by the address generation unit 403.
The address converter 404 converts the address in the scanning order in the figure into the 10th address in the scanning order.
This is the address converted to the scanning order in the figure.The coefficient memory is written in the order shown in Figure 10, and 2 in Figure 10.
Even if an i EOB code is detected by decoding 8 non-zero coefficients, the register 406 is controlled to store the address of the last non-zero coefficient in the order of writing in the block to be decoded by the function of the J & timing control unit 409. Therefore, even if the address 28 of the address conversion unit 404 is stored, the coefficient memory 402 at this time is in the state shown in FIG. 11. In FIG. A state in which the recorded data remains as is, or a state in which the total heat data is not recorded.

Next & Next Read the coefficients in the coefficient memory 402 in order to completely decode the coefficient data. Also read the coefficients in the scanning order shown in FIG. 9. Here, address 28 stored in the register 406 and the coefficient memory The address of the address generating unit 403 given to the register 402 is compared with the address converted by the address converting unit 404. If the register 406 is larger, the coefficient data of the coefficient memory 402 is sequentially read out. If it is smaller, the comparator 407 notifies the timing controller 409. Also, the timing control unit 409 gives a select signal to the selector 408 to select the zero coefficient.
Control is performed to read out zeros a. This completes the decoding of one block, and the next block is sequentially decoded.

In this embodiment, reading from the coefficient memory can be performed serially in the horizontal direction, eliminating the need for a buffer memory and speeding up the decoding process. Encoding and decoding are performed by dividing the blocks into blocks of ×N pixels. As described above, according to the present invention, in a variable-length code encoding/decoding device that encodes the number of consecutive zeros and non-zero, the limit of encoding and decoding processing is set after the last non-zero coefficient in the block. Since the zero coefficients of Since the coefficients are not written, the number of data to be written can be reduced and the decoding process can be made faster. Furthermore, since the write address can be controlled when writing to the coefficient memory, writing to the coefficient memory can be performed in any direction order. , it is possible to speed up the encoding and decoding process since there is no need for buffer memory, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an encoding device according to a first embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a decoding device according to a second embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of a decoding device according to a second embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of the encoding device according to the fourth embodiment of the present invention. FIG. 5 is a block diagram showing the configuration of the decoding device according to the fourth embodiment of the present invention. Fig. 6 shows the data structure showing the content of the data to be encoded in the first embodiment, and Fig. 7 shows the data showing the content of the coefficient data in the block to be decoded in the second embodiment. Figure 8 is a data configuration diagram showing the state of code data in the first embodiment.
Figure 10 shows the addresses within the block in the scanning order. Figure 11 shows the coefficients within the block.
Figure 2 shows the characteristics of the transform coefficients of cosine transform.
01...Coefficient memory, 102...Zero coefficient detection screen 103
...Address generation unit 104... Regis Kyu 105... Combare Kyu 106 -- Timing control section 107...
Encoding paste Figure 1 4! number data

Claims (8)

[Claims] (1) Divide the image into blocks of N×N pixels (N: an integer), perform orthogonal transformation on the data in the blocks, perform quantization to obtain transform coefficients, and calculate zero coefficients for the transform coefficients. In a variable-length encoding method that encodes the number of non-zero coefficients and assigns an EOB code to the consecutive zero coefficients if the end of the block ends with consecutive zero coefficients, at least a memory that stores the data in the block is used. , non-zero coefficient determining means for determining whether the conversion coefficient is a zero coefficient or a non-zero coefficient; address generating means for generating an address to be stored in the memory when writing the conversion coefficient to the memory; non-zero coefficient address storage means for storing an address of a memory in which a coefficient is written; and address comparison means for comparing an address stored in the non-zero coefficient address storage means with an address read from the memory; When writing into the block, the contents of the block are written in a certain order, and at the same time, the non-zero coefficient determining means sequentially determines whether the conversion coefficients to be written are zero or non-zero, and the conversion If the coefficient is a non-zero coefficient, its address is stored in the non-zero coefficient address storage means, and when encoding the transform coefficients in the block, the transform coefficients in the block are sequentially read from the memory, and the address is stored in the non-zero coefficient address storage means. The address comparing means compares the address with the address stored in the non-zero coefficient address storage means, and when the address in which the last non-zero coefficient exists in the block is reached, reading is finished and an EOB code is added. Characteristic encoding device. (2) It is characterized by comprising an address conversion means for converting the address generated by the address generation means, and when writing the conversion coefficient to the memory, the address given to the memory is written in accordance with the output format in which the conversion coefficient is output. The encoding device according to claim 1, wherein: (3) The address comparison means includes a first address comparison means that compares the address stored in the non-zero coefficient address storage means and the address read from the memory, and the address converted by the address conversion means and the storage of the non-zero coefficient address storage means. 3. The encoding device according to claim 2, further comprising a second address comparing means for comparing the first address with the second address. (4) Divide the image into blocks of N×N pixels (N: integer), perform orthogonal transformation on the data in the blocks, perform quantization to obtain transform coefficients, and calculate zero coefficients for the transform coefficients. In a variable-length encoding method that encodes the number of non-zero coefficients and assigns an EOB code to the consecutive zero coefficients if the end of the block ends with consecutive zero coefficients, at least a memory that stores the data in the block is used. , an address generation means for generating an address to be stored in the memory when writing the conversion coefficient into the memory, a non-zero coefficient address storage means for storing an address to write the non-zero coefficient, and the non-zero coefficient address storage means. an address comparison means for comparing an address stored in the EOB with an address read from the memory; and a data selection means for selecting the stored contents of the memory or zero as an output when outputting coefficient data; If a code is detected, writing to the memory is completed and the address is stored in the address storage means, and when reading a coefficient from the memory, the address comparison means compares the non-zero coefficient address stored in the storage means. The decoding method is characterized in that an address to be read is compared with an address to be read, and when an address stored in the non-zero coefficient address storage means is reached, the output is switched by the data selection means and zero coefficients are read from that address onwards. Device. (5) It is characterized by comprising an address conversion means for converting the address generated by the address generation means, and when writing the conversion coefficient to the memory, the address given to the memory is written in accordance with the output format in which the conversion coefficient is output. 5. The decoding device according to claim 4. (6) The address comparison means includes a first address comparison means that compares the address stored in the non-zero coefficient address storage means and the address read from the memory, and the address converted by the address conversion means and the storage of the non-zero coefficient address storage means. 6. The encoding device according to claim 5, further comprising a second address comparing means for comparing the second address with the second address. (7) Divide the image into blocks of N×N pixels (N: an integer), perform orthogonal transformation on the data in the blocks, perform quantization to obtain transform coefficients, and apply zero coefficients to the transform coefficients. In a variable-length encoding method that encodes the number of non-zero coefficients and assigns an EOB code to the consecutive zero coefficients if the end of the block ends with consecutive zero coefficients, at least a memory that stores the data in the block is used. , non-zero coefficient determining means for determining whether the conversion coefficient is a zero coefficient or a non-zero coefficient; and address generation means for generating an address to be stored in the memory when writing the conversion coefficient to the memory;
non-zero coefficient address storage means for storing an address of a memory in which the non-zero coefficient is written; and address comparison means for comparing an address stored in the non-zero coefficient address storage means and an address read from the memory; When writing into the memory, the blocks are written in a certain order, and at the same time, the non-zero coefficient determining means sequentially determines whether the conversion coefficients to be written are zero or non-zero. , if the transform coefficient is a non-zero coefficient, its address is stored in the non-zero coefficient address storage means, and when encoding the transform coefficients in the block, the transform coefficients in the block are sequentially stored from the memory. Reading, the address comparison means compares the address with the address stored in the non-zero coefficient address storage means, and when the address becomes the address where the last non-zero coefficient exists in the block, the reading ends and an EOB code is added. encoding method. (8) Divide the image into blocks of N×N pixels (N: integer), perform orthogonal transformation on the data in the blocks, perform quantization to obtain transform coefficients, and calculate zero coefficients for the transform coefficients. In a variable-length encoding method that encodes the number of non-zero coefficients and assigns an EOB code to the consecutive zero coefficients if the end of the block ends with consecutive zero coefficients, at least a memory that stores the data in the block is used. , an address generation means for generating an address to be stored in the memory when writing the conversion coefficient into the memory, a non-zero coefficient address storage means for storing an address to write the non-zero coefficient, and the non-zero coefficient address storage means. an address comparison means for comparing an address stored in the EOB with an address read from the memory; and a data selection means for selecting the stored contents of the memory or zero as an output when outputting coefficient data; If a code is detected, writing to the memory is completed and the address is stored in the address storage means, and when reading a coefficient from the memory, the address comparison means compares the non-zero coefficient address stored in the storage means. The decoding method comprises comparing an address to be read with an address to be read, and when an address stored in the non-zero coefficient address storage means is reached, the output is switched by the data selection means and zero coefficients are read from that address onward.