JP3222633B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for decoding an image signal or the like in which the amount of information is coded and compressed, and in particular, decodes a compressed data string which has been subjected to entropy coding and run-length coding. In the information processing device,
The scan order conversion process can be realized with a smaller amount of hardware, the run-length code decoding process can be realized with a smaller hardware configuration, and can be performed efficiently without wasting time. The present invention relates to an information processing apparatus in which a hardware load on a code decoder is reduced.

[0002]

2. Description of the Related Art In recent years, there has been a movement to record an image signal on a storage medium of a computer and to treat the image signal uniformly like ordinary data. This is generally referred to as multimedia. However,
Since the image signal has a very large data amount, some data compression is required. Three data compression methods are commonly used: (1) a data compression method using temporal redundancy, (2) a data compression method using spatial redundancy, and (3) a data compression method using code redundancy. In the present invention, coding using temporal redundancy is not described.

Data compression using spatial redundancy is firstly developed into orthogonal functions having different frequencies, such as cosine transform, and the sensitivity of the human eye is insensitive to the obtained coefficients corresponding to each frequency. Data compression is performed by performing quantization so that the coefficient of a high-frequency portion has a large quantization width. In recent years, two-dimensional cosine transform is often used in data compression by this method.

[0004] On the other hand, data compression using code redundancy refers to encoding in the form of a set of a zero run length and a value (run length encoding), and allocating the data so as to have a shorter code length in order of appearance probability. This is a compression method (entropy coding or variable length coding).

As described above, run-length codes are often used for data compression in combination with entropy codes and the like. According to this run-length code system, some of the original information source symbols are collected. Can be sent as one piece of information. FIG. 12A shows an example in which run-length encoding is performed on a binary data sequence. By counting the number of continuous "0" and the number of "1", and alternately arranging the runs of "0" and the runs of "1", the number of symbols is greatly reduced, and information can be compressed. .

When the run-length code is applied to a multi-gradation image signal, a method can be used in which a continuous number of uncoded data and data to be coded are combined into one symbol. FIG. 12B shows an example in which run-length encoding is performed on a multi-valued data sequence. The number of symbols can be reduced by expressing a combination of the number of “0” preceding the data other than “0” and the value other than “0”.

[0007] Such a run-length code is a discrete cosine transform (hereinafter referred to as DCT).
It is particularly effective when used in combination with the above. In information compression of a multi-gradation image signal, an image is first divided into small blocks (for example, blocks of 8 × 8 pixels), and each is appropriately transformed (orthogonal transformation such as DCT or a base value such as an average value of pixels). , The quantization is performed for each pixel. With these operations, the block is
After converting the data into data in which "0", that is, uncoded data, appears frequently, the data is arranged one-dimensionally, and the number of leading "0" s (hereinafter referred to as "zero run") for the data sequence.
And a value other than “0” (hereinafter referred to as “level”) as a set to reduce the number of symbols and perform entropy coding.

In such an information compression method, the decoded result does not completely return to the original data due to a conversion error or quantization, but the quantization width is adjusted for each pixel to obtain "0". By adjusting the frequency of occurrence of, it is possible to compress the data while balancing it with the visual image of the data when decoding. In multi-tone image information compression, a method that combines DCT, quantization, run-length encoding, and variable-length encoding is often used.

FIG. 13 shows an example of run-length encoding for a small block (8 × 8 pixels) obtained by orthogonally transforming and quantizing pixels. Data that has been subjected to orthogonal transformation such as two-dimensional DCT
Utilizing that the resolution of the high-frequency component is not visually high, a large quantization width is given to the data corresponding to the high-frequency component, and the appearance frequency of “0” is set high. FIG.
(1) is a small block processed in this way.

[0010] Run length coding is performed on the small block by combining a zero run and a level. However, since the run length code is further variable length coded, the run length coded data is biased. The encoding efficiency is improved. In other words, since the lower right region of the small block corresponds to the coefficient of the cosine function having a higher frequency, the value after quantization is almost zero,
When run-length encoding is performed on a zigzag-scanned data sequence, the number of run-length codes is reduced as compared with a normal raster-ordered data sequence. Both raster scan and zigzag scan have the same number of symbols as a result of cellolan encoding. What really matters is the length of the zero run and the order in which the levels appear. As a result of DCT, many levels appear in the upper left corner, so zigzag scanning has more zero runs, which makes variable-length coding more efficient.

Therefore, data is arranged in a zigzag order so that many small zero-runs appear as shown in FIG. 13 (2), and run-length coding is performed on the data sequence, whereby the run-length code shown in FIG. 13 (3) is obtained. Is obtained. Further, variable-length coding is performed on the run-length code of FIG. 13C, and header information such as quantization width information is added.
The final compressed data is obtained.

FIG. 14A shows a configuration diagram of a decoding apparatus for decoding image data compressed in this way. This conventional decoding apparatus includes a buffer BUF for inputting and temporarily storing a compressed data string Zdata, a variable-length code decoder V
LD, scan order converter ZIGZAG ', run-length decoder RLD, inverse quantizer IQ, inverse orthogonal transformer IOT
And sequentially expands the compressed data to obtain a final decoded data sequence Ddata.

That is, first, the variable-length code is decoded by using the variable-length code decoder VLD, and the obtained run-length code in zigzag order (see FIG. 15 (1)) is normally converted by the scan order converter ZIGZAG '. The scan order in the raster order (see FIG. 15 (2)) is changed, the run-length decoder RLD returns the run-length code to a sequence of values, and the coefficient sequence is subjected to inverse quantization by the inverse quantizer IQ. The decoded data sequence Ddata is obtained by performing the inverse orthogonal transform by the inverse orthogonal transformer IOT.

Here, the scan order converter ZIGZA
As the hardware specifications of G ′, data input in a zigzag order is written in a buffer memory in a zigzag order,
What is necessary is just to realize the function of reading it out at the address in the raster order. That is, a buffer memory having at least the address of the two-dimensional cosine transform area is required.
In order to perform processing in real time, writing in zigzag order and reading in raster order must be performed at the same time. Therefore, since the interleave method is used, a buffer having twice the address of the two-dimensional cosine transform area is used. Requires memory.

Therefore, the scan order converter ZIGZA
The configuration of G ′ is as shown in FIG. Where C
MEM0 and CMEM1 are buffer memories. When estimating the actual capacity of the buffer memory, first, in the word direction, the area of the two-dimensional cosine transform is n ×
If m [pixel] is set, it becomes an area of nm [word]. on the other hand,
In the bit direction, if it is an n × m cosine transform domain, it is necessary to represent up to n × m zero run lengths, and therefore w = log (nm) for the zero run length.
(The base of log is 2), and if the data value has a precision of a [bit], the bit width of a × W [bit] in total Is required. Therefore, as the capacity of the buffer memory, Is required.

As described above, the capacity of the buffer memory used in the scan order converter ZIGZAG 'of the conventional decoding apparatus increases as the two-dimensional cosine transform area (n.times.m) increases. Since a very small amount of hardware is generally required for the device, it is very important to reduce the capacity of the buffer memory in the configuration of the decoding device.

[0017]

As described above, in a conventional information processing apparatus that decodes an encoded image signal or the like in which the amount of information is compressed, it is necessary to convert a scan order from a zigzag order to a raster order. There is a problem that the capacity of the buffer memory used increases as the two-dimensional cosine transform area increases, and the amount of hardware of the decoding device increases.

The present invention solves the above problems,
It is an object of the present invention to provide an information processing apparatus for decoding a run-length coded compressed data sequence, which realizes a buffer memory used for converting a scan order from a zigzag order to a raster order with a smaller capacity. It is to be.

Another object of the present invention is to realize a run-length code decoding process with a smaller hardware configuration in an information processing apparatus for decoding a compressed data sequence that has been subjected to variable-length coding and run-length coding. Another object of the present invention is to provide an information processing apparatus which can perform the processing efficiently without wasting time and reduce the load on hardware for the variable length code decoder.

[0020]

In order to solve the above-mentioned problems, a first feature of the present invention is that, as shown in FIG. 1, FIG. 7, FIG. 9 and FIG. An information processing device that decodes a compressed data string encoded by being expressed by the number of times, and has at least two storage areas, such as bank memories BM0 and BM1, and performs writing and reading to and from these storage areas. A storage unit 13 for performing the initialization simultaneously by writing the same value to the memory bank BM0 or BM1 which is a first storage region in the storage region continuously, and an initialized part Address corresponding to the number of consecutive
It is provided with a decoding unit RLD having a writing unit for writing the compressed data string Vdata and a reading unit for reading the data string Rdata written in the second recording area of the storage area.

A second feature of the present invention is that, for example, FIG.
As shown in FIG. 7, an information processing apparatus for decoding a compressed data sequence Vdata represented by a set (z, d) of a continuous number z of consecutive identical values and a data value d other than the identical value, wherein at least two storage units Storage means 13 having an area; initialization means for performing initialization by successively writing the same value in the first storage area of the storage area; and initialization means for performing initialization on the initialized storage area. , Compressed data string Vdata
The data value d of the (i-1) -th set (zi-1, di-1)
The next address is obtained by adding the ith consecutive number zi of the same value to the address where i-1 is written, and the compressed data sequence Vdata is written so that the ith data value di is written to this next address. Writing means for writing;
And a reading means for reading data Rdata already written in the second storage area at the same time as the writing processing to the storage area.

A third feature of the present invention is that, in the above-mentioned invention, for example, as shown in FIG.
Scan sequence converting means Z for inputting a data sequence output from the above and converting the scan sequence of the data sequence into a scan sequence of a data sequence different from the input data sequence
Having IGZAG.

A fourth feature of the present invention is that, in the above invention, as shown in FIG.
An address generation unit 33 generates an address of the data Rdata to be read.
Address generation is performed so that the scan order of the data sequence is different from that of the input data sequence.

A fifth feature of the present invention is that, in the above invention, as shown in FIG. 10, the writing means has an address conversion means 40 for generating an address of write data Vdata. Means 40
Is to generate the address so that the scan order of the data series is different from the scan order of the data series that is input.

Further, the reading means has an address generating means for generating a read address when reading data of one block so that the scanning order in the block becomes a predetermined scanning order.

The writing means has an address conversion means for converting a write address so that a scan order in the block becomes a predetermined scan order when writing data for one block.

The storage means has a plurality of bank memories, and the reading means reads one block of data which has already been written in one of the bank memories, and the writing means stores A compressed data string for one block is written in another memory.

[0028]

In the information processing apparatus according to the first aspect of the present invention, at the time of writing to the storage means 13, a data value di (level lv) other than the same value is stored in an address corresponding to the number of consecutive times of the same value.
By writing only l), decoding is achieved, so that the variable-length code decoder does not pause until recognizing the end of the block, and as a result, the load on the hardware of the variable-length code decoder is reduced. And the wasted time caused by the suspension is eliminated. Further, in the information processing apparatus according to the first aspect of the present invention, the storage means 13 is constituted by a plurality of bank memories BM0 and BM1, and the read means 1
4 reads out one block of data Rdata already written in one bank memory BM0 or BM1, and at the same time, the writing means 10 writes one block worth of data to another BM1 or BM0 of the bank memory. Since the compressed data sequence Vdata was written,
The speed of the decoding process can be increased.

Further, in the information processing apparatus according to the second feature of the present invention, as shown in FIG. 7, a set (z, z) of a continuous identical value, for example, a preceding zero consecutive number z and a non-zero data value d. In the run-length decoding unit RLD for converting the compressed data sequence Vdata of, for example, a run-length code described in d) into a predetermined data sequence Rdata, the reading unit 14 reads the data Rdata already written in the storage unit 13. And the writing means 10 initializes the compressed data string Vda in the storage means 13 initialized to the zero value.
For the i-th set (zi, di) of ta, the number zi of the i-th zero is written at the address where the non-zero data value di-1 of the (i-1) -th set (zi-1, di-1) is written. The compressed data string Vdata is written so that the ith non-zero data value di is written to the added address.

That is, the data value d other than the i-th identical value
In the address calculation for writing i (level lvl), if the level (d1) of the first set of the block is "1", the preceding number of consecutive times z1 (zero run zr) of the same value is added, and the levels of the other sets (zero run zr) Di) can be realized by adding "1", zero run (zi), and the address where the immediately preceding set of levels (di-1) are written, so that if "1" is the carry-in of the adder, one is obtained. , The holding register 12 of the calculation result and its initialization (zero reset), and the error becomes a carry-out of the adder 11, thereby simplifying the circuit configuration.

At the time of writing to the storage means 13,
Since decoding is achieved by writing only data values di (level lvl) other than the same value to addresses corresponding to the number of consecutive same values, the variable-length code decoder pauses until recognizing the end of the block. As a result, the load on the hardware of the variable-length code decoder is increased, and wasted time caused by the temporary stop is eliminated.

As described above, according to the first and second aspects of the present invention, there is no time for writing the same value at the time of decoding.
Since decoding can be performed in a time corresponding to the number of data values other than the same value (for example, a symbol of a run-length code), the variable-length code decoder VLD can perform the decoding process at a stretch,
No wasted time. That is, for example, the header information can be decrypted during the run-length code supply suspension time. Further, generation of zero for zero run, generation of an address, and generation of an error signal can be performed by one adder, thereby simplifying the circuit configuration.

In the information processing apparatus according to the third aspect of the present invention,
As shown in FIG. 1, in the above invention, the compressed data sequence Zd
For example, immediately after the variable-length code is decoded by the variable-length code decoder VLD, the compressed data sequence Vdata is decoded by the run-length decoding means RLD, and is equal to the number of consecutive times z of the same value. The data is returned to a data sequence based on a set (z, d) of data values d other than the values. Then, the scan order is converted from the zigzag order to the raster order by the scan order conversion means ZIGZAG using, for example, the buffer memories CMEM0 and CMEM1. Raster series data can be decoded by performing inverse quantization and inverse orthogonal transform.

In the configuration of the information processing apparatus according to the third feature, when the capacities of the buffer memories CMEM0 and CMEM1 used for the conversion from the zigzag order to the raster order are estimated, first, the word direction is the same as that of the conventional buffer memory. Similarly, if the area of the two-dimensional cosine transform is n × m, the area is (nm) [word]. On the other hand, in the bit direction, since decoding from the compressed data sequence (run-length code) into a sequence of only normal values has already been completed, the value a
If there is an accuracy of [bit], it becomes a [bit]. Therefore, the capacity of the buffer memory is (nm) [word] × a [bit] × 2. As described above, the buffer memory in the conventional technology requires a capacity of (nm) [word] × (a + W) [bit] × 2. Therefore, compared to the conventional technology, the buffer memory of nm × W × 2 It is possible to configure with a memory amount smaller by the capacity.

In the information processing apparatus according to the fourth feature of the present invention, as shown in FIG.
When reading the block data Rdata, the address generation unit 33 generates the read address so that the scan order is different from the scan order at the time of input. Therefore, the scan order is arranged in the run-length decoding unit RLD. Since the function of changing the scan order has been added, the amount of hardware can be reduced, and the scan order conversion processing does not need to be performed separately, so that the processing can be sped up.

In the information processing apparatus according to the fifth aspect of the present invention, as shown in FIG.
When writing the data Vdata, the address conversion means 4
Since 0 converts the write address so that the scan order is different from the scan order at the time of input, a function of rearranging the scan order is added to the run-length decoding means RLD. Can be reduced, and it is not necessary to separately perform the scan order conversion processing, so that the processing can be sped up.

[0037]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1A shows a configuration diagram of an information processing apparatus according to a first embodiment of the present invention. In the figure, the same reference numerals are given to portions overlapping with FIG. 14 (conventional example).

In the figure, the information processing apparatus of the present embodiment includes a buffer BUF for inputting and temporarily storing a compressed data sequence Zdata, a variable length code decoder VLD, a run length decoder RLD, and a scan order converter ZIGZAG. ,
An inverse quantizer IQ, an inverse orthogonal transformer IOT,
This is a decoding device that obtains a final decoded data sequence Ddata by sequentially expanding compressed data.

That is, the decoding apparatus of the present embodiment has a configuration in which the scan order converter ZIGZAG is arranged after the run-length decoder RLD for converting a run-length code into a sequence of normal values, as compared with the conventional example. I have.

Therefore, the encoded image signal (compressed data string Zdata) is first held in the buffer BUF, and then decoded by the variable length code decoder VLD into a series of run-length codes (Vdata). The code string Vda
ta is converted into a series of original values Rdata by the run-length decoder RLD. Those data are written in the buffer memory CMEM0 with the zigzag address generated by the zigzag address generation circuit Zad. At the zigzag address, the buffer memory CMEM0
From the buffer memory CMEM1, the data of the small block that has not yet been written is converted from the zigzag order to the raster order by the address generated by the raster address generation circuit Rad as a data sequence Rdata '. Is read. Thereafter, inverse quantization is performed by the inverse quantizer IQ, and inverse orthogonal transform is further performed by the inverse orthogonal transformer IOT, thereby obtaining a final decoded data sequence Ddata.

The scan order converter ZIGZAG for converting the zigzag order to the raster order includes two buffer memories CMEM0 and CMEM1, a zigzag address generation circuit Zad, and a raster address generation circuit Rad. FIG. 2 shows the scan order converter ZIGZ of the present embodiment.
FIG. 3 shows a detailed configuration diagram of an AG.

In FIG. 2, a buffer memory CMEM0
And a counter CN for sequentially counting up, an address converter ADC for converting a sequential address into an address in a zigzag order, a selector S0 for selecting an address for the buffer memory CMEM0, and selecting an address for the buffer memory CMEM1. Selector S
1 is provided. Note that the contents held by the address converter ADC are as shown in FIG. 3 when the size of the two-dimensional cosine conversion area, that is, the small block is n × m = 8 × 8.

That is, in FIG. 2, the zigzag address generation circuit Zad includes a counter CN, an address converter ADC, and a selector S0 or S1, and the raster address generation circuit Rad includes a counter CN, and a selector S0 or S0.
1, respectively.

As described above, the information processing apparatus (decoding apparatus) according to the present embodiment has the configuration in which the scan order converter ZIGZAG is arranged after the run-length decoder RLD, so that the buffer used in the scan order converter ZIGZAG is used. The capacities of the memories CMEM0 and CMEM1 can be configured with a smaller memory capacity by the capacity of nm × W × 2 [bit] from the above equations (1) and (2). Here, the size of the two-dimensional cosine transform area is n × m = 8 × 8.
In this case, w = log (8 × 8) = 6W, and 8
It is possible to save a buffer memory having a capacity of × 8 × 6 × 2 = 768 [bit].

[First Modification of First Embodiment] FIG. 1 (2) is a block diagram of an information processing apparatus according to a first modification of the first embodiment of the present invention.

In the configuration of this modification, the zigzag address generation circuit Zad and the raster address generation circuit Rad for the buffer memories CMEM0 and CMEM1 are exchanged as compared with the first embodiment, and one of the buffer memories CMEM0 and CMEM0 is replaced with the address in the raster order. , And at the same time, the data of the previously written small block is read from the other buffer memory CMEM1 at an address in a sigzag order. Even in such a configuration, the effect of reducing the capacity of the buffer memories CMEM0 and CMEM1 can be obtained as in the first embodiment.

[Second Modification of First Embodiment] FIG. 6A is a block diagram of an information processing apparatus according to a second modification of the first embodiment of the present invention.

In the configuration of the present modification, the buffer memory CMEM is constituted by one bank, as compared with the configuration of the first embodiment.
After writing at an address in a zigzag order, reading is performed at an address in a raster order. If high speed is not required, such a configuration is possible.

[Third Modification to First Embodiment] FIG. 6 (2) is a block diagram of an information processing apparatus according to a third modification to the second embodiment of the present invention.

In the configuration of the present modification, the buffer memory CMEM is constituted by one bank, as compared with the configuration of the first embodiment.
After writing at an address in a raster order, reading is performed at an address in a zigzag order. As in the second modification, when high speed is not required, such a configuration can be adopted.

[Detailed Description of Run-Length Decoder RLD in First Embodiment] Next, the first embodiment and the first embodiment will be described.
The configuration and operation of the run-length decoder RLD in the first, second, and third modifications of the embodiment of the present invention will be described in detail, and its problems will be mentioned.

The run-length decoder RLD decodes the compressed data string Zdata into a series of run-length codes Vdata by the variable-length code decoder VLD, and then decodes the code string Vdata into a series of original values Rdata. is there. In the configurations shown in FIGS. 1 (1) and (2) and FIGS. 6 (1) and (2), the run length code Vdata of the variable length code decoding result and the output R of the run length decoder
Since data has a different number of symbols, handshaking is performed between the variable-length code decoder VLD and the run-length decoder RLD, and the run-length decoder RLD supplies the run-length code Vdata output from the variable-length code decoder VLD. The decoding is performed while stopping timely.

FIG. 4 shows the run-length decoder RL of this embodiment.
3 shows a detailed configuration diagram of D. FIG. FIG. 4 assumes run-length decoding when the size of a small block (two-dimensional cosine transform area) is, for example, 8 × 8.

In the run-length decoder RLD shown in FIG. 4, the run-length code Vdat as a result of decoding the variable-length code is obtained.
a is supplied as a set of a zero run zr representing the number of leading zeros and a level lvl having a non-zero value. EOB is a signal indicating that the run-length code for one small block has been completed, and halt is a signal for stopping the supply of the run-length code to the variable-length code decoder VLD while it is active.

The decrementer 101 and the register 102
First, a zero run zr is set, decremented until the value becomes zero, and the run length code supply stop signal halt is activated until the value becomes zero. The output of the counter 103 is used as an input of a controller 104 and an error detector 106.

The controller 104 receives the block end signal EOB, and the period until the counter 103 is "63" is a period during which the run-length decoder RLD outputs zero.
lt is activated. The selector 105 outputs a signal during a period in which the run-length code supply stop signal halt is active.
Select "0" and output.

The error detector 106 compares the value obtained by subtracting the output value of the counter 103 from the value “63” with the zero run zr.
Activate and output the error signal error. In this case, the decoding result Rdata of the run-length code is "
This means that 64 or more symbols including 0 "are included, and it is detected that there is an error in the input data. Thus, in the run-length decoder RLD of this embodiment,
"0" is output by the number of zero runs zr.

FIG. 5 shows the variable length code decoder VL of this embodiment.
4 is a timing chart illustrating the operation of D and the run-length decoder RLD. In the figure, VLD indicates a variable length code decoder, and RLD indicates a run length decoder.

As shown in the figure, the run-length decoder R
Since the LD outputs as many data as the number of original image data, a certain time is always required for decoding. Further, the variable-length code decoder VLD must temporarily stop the decoding of the variable-length encoder VLD and stop supplying the run-length code while the run-length decoder RLD outputs zero. Such frequent repetition of suspension makes the hardware configuration difficult.

Further, in the compressed data, not only the run-length code but also information such as the number of symbols of the run-length code and quantization information, which are essential for decoding, and various additional information are variable-length. Since they are encoded, these data must also be decoded. Since the header information cannot search for any data in the bit stream due to the nature of the variable length code, it cannot be normally extracted unless the run-length code portion is completely extracted. Therefore, the header information cannot be interpreted until the variable-length code decoder VLD detects the block end signal EOB, and stopping the decoding before that becomes a complete overhead time. Therefore,
In real-time processing of a moving image or the like, the decoding time of the header portion containing the additional information cannot be taken, and the load on the hardware increases.

(Second Embodiment) Next, an information processing apparatus according to a second embodiment of the present invention which solves the problems of the information processing apparatus of the first embodiment will be described. The overall configuration of the information processing apparatus according to the present embodiment is shown in FIGS.
The configuration is the same as that of the first embodiment shown in FIGS. 6A and 6B and the first, second, and third modified examples of the first embodiment.

In this embodiment, in order to solve the problem of the run-length decoder RLD in the first embodiment, the run-length decoder RLD has a detailed configuration as shown in FIG. In the figure, a run-length decoder R of the present embodiment is shown.
The LD includes a bank memory (storage unit) 13 for holding the run length code Vdata for each block unit, a counter (reading unit) 14, a writing unit 10 including an adder 11 and a register 12, and a controller 15. Note that among the signal names used in FIG. 7, the same signal names as those in FIG. 4 use the same signal names, and a description thereof will be omitted.

The adder 11 calculates an address at which the level lvl is to be written, and detects an error. The calculation of the write address is based on the contents of the register 12 holding the previous write address, the length of the zero run zr, and "1".
Is executed by adding. “1” is a carry-in of the adder 11, and a single adder 11 can calculate a write address by adding the contents of the register 12 and the zero run zr.

Since the error detection is carried out by the adder 11, the calculation of the write address and the error detection can be performed with a very simple configuration. Register 12 is reset to zero just before the start of run-length decoding, so that it is zero when calculating the write address of the first run of the small block. The output of the adder 11 is used as a write address,
By writing the level lvl into the bank memory 0BM0 or the bank memory 1BM1 which has been initialized to zero in advance, the decoding process of the run-length code is performed.

The bank memory 13 has two memories (BM0 and BM1) each having a capacity of one block, one of which is used for writing a run-length code and the other is used for reading the result of decoding a run-length code. Used for
When only one block of memory is provided, reading cannot be performed until after writing is completed. However, by alternately using two memories of one block, writing and reading can be performed simultaneously, which is efficient.

In reading from the bank memory 13, a read address is generated by the counter 14. Further, according to the value of the counter 14, the content of the bank memory 0BM0 or the content of the bank memory 1BM1 is read, and at the same time, "0" is written.
The contents of 0 or BM1 are sequentially initialized. Since the zero portion of the run-length code has been decoded in advance by this read-modified-write operation, when the bank memory is switched and the bank memory that was performing the read operation becomes the bank that performs the write operation,
By writing the level lvl to a random address calculated by the above-described write address calculation means, a run-length code decoding process can be realized.

The controller 15 generates the bank switching signal bc when the counter 14 generates the read address at the beginning of the next small block after the read address is generated from the bank memory 13 last. In addition, a block end signal E indicating the end of the run length code in one small block.
During the period from when the OB is sent to when the counter 14 generates the next first read address, the next run-length decoding cannot be performed because there is no initialized bank memory. In order to stop the supply, the run-length code supply stop signal halt
To stop decoding.

FIG. 8 is a timing chart for explaining the operation of this embodiment. In the figure, VLD indicates a variable length code decoder, and RLD indicates a run length decoder.

In the run-length decoder RLD of this embodiment, the bank memory BM0 initialized before the start of the run-length code decoding operation, such as immediately after power-on, is started.
Alternatively, in order to prepare the BM1, an operation of performing idle reading of one bank of memory is required.

When the operation is started, the bank memory BM0 or B
Since the decoding is completed by one write operation to M1, the decoding process of the run-length code is completed only in the time corresponding to the number of the run and level pairs. Also, the variable length code decoder VLD that supplies the run length code can continuously decode the run length code portion in the bit stream.

Accordingly, the operation of stopping the variable-length code decoder VLD until the detection of the block end signal EOB is a period during which the header information cannot even be extracted by decoding the bit stream, but this operation does not occur. ,
Since the bit stream can be efficiently decoded and there is no operation to stop each time, the load on the hardware of the variable-length code decoder VLD is reduced.

Further, the period during which the supply of the run-length code is stopped from the block end signal EOB to the start of the next run-length decoding is a time including the overhead portion in the first embodiment, and is longer. Therefore, operations such as extracting header information and the like from the bit stream during that period can be flexibly processed.

[First Modification of Second Embodiment] FIG. 9 shows a detailed configuration diagram of a run-length decoder RLD in an information processing apparatus according to a first modification of the second embodiment.

The run-length decoder RLD of this modification is
Scan order converter Z for rearranging scan order
The configuration includes the function of IGZAG. Therefore,
The overall configuration of the information processing apparatus according to the present modified example is a configuration in which the scan order converter ZIGZAG is removed from the configuration shown in FIGS. 1 (1) and (2) and FIGS. 6 (1) and (2).

The run-length decoder R according to the second embodiment
Although the LD requires a bank memory initialized to zero in advance, the configuration of the present modification can be used very effectively to rearrange the scan order.

Read address generator 3 for bank memory 13
1 generates a read address by a counter 32 and an address converter 33 for converting the raster order before changing the scanning order in the run-length encoding. Here, when zigzag scanning is performed, the address converter 33 can be realized by a memory holding a conversion table shown in FIG.

As described above, the configuration of the information processing apparatus according to the present modification has a configuration in which the function of rearranging the scan order is added to the run-length decoder RLD, so that the hardware amount can be further reduced and the scan amount can be reduced. Since it is not necessary to separately perform the order conversion processing, the processing can be speeded up.

[Second Modification to Second Embodiment] FIG. 10 shows a detailed configuration diagram of a run-length decoder RLD in an information processing apparatus according to a second modification to the second embodiment.

The run-length decoder RLD of this modification is also
Scan order converter Z for rearranging scan order
The configuration includes the function of IGZAG. As in the first modification, the overall configuration of the information processing apparatus of this modification is
The configuration shown in FIGS. 1 (1) and (2) and FIGS. 6 (1) and (2) is obtained by removing the scan order converter ZIGZAG.

Run Length Decoder RLD of First Modification
In the above, the scan order conversion processing was realized by performing address conversion at the time of reading from the bank memory 13, but in this modification, at the time of writing to the bank memory 13, the scan order is converted by performing address conversion. Conversion processing is realized.

That is, the address converter 40 (memory) holding the conversion table shown in FIG. 11 is added to the output side of the adder 11, and the write address output from the adder 11 is converted. Is converted to the scan order at a stretch by the write operation of. In this case, the read address generating means can be constituted only by the simple counter 14.

As described above, in the run-length code using the zero-run zr, small blocks are usually scanned in raster order and arranged one-dimensionally in order to improve coding efficiency when performing variable-length coding. Instead, a method such as conversion into zigzag scan is used. In order to realize such rearrangement arbitrarily, it is necessary to once store the decoding result of the run-length code in the memory.

The configuration of the bank memory or 13 in the run-length decoder RLD of the first and second modifications can be used very effectively to realize this rearrangement, and the address converter 33 or 40 can be added. Thus, the scan order can be easily rearranged. In particular, in a system that does not require real-time performance, the bank memory 13 may not be configured as a two-bank configuration, and may be switched between writing and reading in small block units as one bank. In this case, the decoding takes twice as long as the second embodiment and the first and second modifications. However, the amount of the bank memory is reduced to half while maintaining the other effects. can do.

[0085]

As described above, according to the information processing apparatus of the first aspect of the present invention, the compressed data sequence subjected to the entropy coding and the run length coding is decoded by the variable length code decoder into a variable length code. Immediately after the execution, the compressed data string is decoded by the run-length decoding means to return to a data sequence of a set (z, d) of the preceding number z of zeros and a data value d other than zero, and thereafter the scan order conversion means In, for example, using a buffer memory, the scan order is converted from the zigzag order to the raster order, and the raster sequence data is subjected to inverse quantization and inverse orthogonal transform and decoded, so that the zigzag order is changed to the raster order. The capacity of the buffer memory used for the conversion into the data can be greatly reduced as compared with the conventional one, and the decoding process can be performed with a smaller hardware configuration. It is possible to provide a processing apparatus.

According to the information processing apparatus of the second, third, fourth, and fifth features of the present invention, the number z of leading zeros
Run-length decoding means for converting a compressed data sequence of a run-length code consisting of a set (z, d) of a non-zero data value d into a predetermined data sequence for each predetermined block unit; The data for one block that has already been written is read and a zero value is written. On the other hand, the writing means stores the ith set (zi, z i) of the compressed data string in the storage means initialized to the zero value.
di), the address obtained by adding the number zi of the i-th zero to the address at which the non-zero data value di-1 of the (i-1) -th set (zi-1, di-1) is written is added to the i-th zero Since the compressed data sequence for one block is written so that data values di other than the above are written, there is no time to write zero in decoding the run-length code, and the time corresponding to the number of symbols of the run-length code is reduced. Since decoding can be performed, the variable-length code decoder can decode the run-length code portion at a stroke, without wasting time,
It is possible to decode header information and the like during the run-length code supply suspension time, and as a result, it is possible to provide an information processing apparatus capable of performing high-speed decoding processing with a smaller hardware configuration.

In the reading means, when reading the data for one block, the address generating means generates the read address so that the scanning order in the block becomes a predetermined scanning order. Since the function of rearranging the order is added, it is possible to provide an information processing apparatus capable of performing a higher-speed decoding process with a smaller hardware configuration.

Alternatively, when writing data for one block in the writing means, the address conversion means may convert the write address so that the scan order in the block becomes a predetermined scan order. Has added the function of rearranging the scan order, reducing the amount of hardware and
Since it is not necessary to separately perform the scan order conversion processing, the processing can be speeded up.

Further, the storage means is constituted by a plurality of bank memories, and the reading means reads one block of data already written in one of the bank memories,
The writing means writes 1 to another of the bank memories.
Since the compressed data string for the block is written, the decoding process of the run-length code can be further speeded up.

[Brief description of the drawings]

FIG. 1A is a configuration diagram of an information processing apparatus according to a first embodiment of the present invention, and FIG. 1B is a configuration diagram of a first modification.

FIG. 2 is a detailed configuration diagram of a scan order converter in the information processing apparatus according to the first embodiment.

FIG. 3 is a diagram illustrating the contents of an address converter in the information processing apparatus according to the first embodiment.

FIG. 4 is a detailed circuit configuration diagram of a run-length decoder in the information processing apparatus according to the first embodiment.

FIG. 5 is a diagram illustrating an operation of a run-length decoder in the information processing apparatus according to the first embodiment.

FIG. 6A is a configuration diagram of a second modification of the information processing apparatus according to the first embodiment, and FIG. 6B is a configuration diagram of a third modification.

FIG. 7 is a detailed circuit configuration diagram of a run-length decoder of the information processing device according to the second embodiment of the present invention.

FIG. 8 is a diagram illustrating an operation of a run-length decoder in the information processing device according to the second embodiment.

FIG. 9 is a detailed circuit configuration diagram of a run-length decoder according to a first modification of the information processing apparatus according to the second embodiment;

FIG. 10 is a detailed circuit configuration diagram of a run-length decoder according to a second modification of the information processing apparatus according to the second embodiment;

FIG. 11 is a diagram illustrating the contents of an address converter of a run-length decoder according to a second modification of the information processing apparatus according to the second embodiment;

FIG. 12A is a diagram for explaining run-length encoding for a binary data sequence, and FIG. 12B is a diagram for explaining run-length encoding for a multi-level data sequence.

FIG. 13 is an example of run-length encoding for a small block (8 × 8 pixels), and FIG.
FIG. 13B shows a data string obtained by zigzag scanning.
(3) is a diagram for explaining each run-length code.

FIG. 14A is a configuration diagram of a conventional information processing apparatus, and FIG. 14B is a detailed configuration diagram of a conventional example.

FIG. 15A is a scan in a zigzag order, and FIG.
FIG. 5 (2) is a diagram for explaining scanning in raster order.

[Explanation of symbols]

Zdata compressed data sequence Ddata decoded data sequence BUF buffer VLD variable length code decoder RLD run-length decoder (run-length decoding means) ZIGZAG scan order converter (scan order converter) ZIGZAG 'scan order converter IQ inverse quantizer IOT Inverse orthogonal transformer Zad Zigzag address generation circuit Rad raster address generation circuit CMEM0, CMEM1 Buffer memory CN counter ADC Address converter S0, S1 Selector Vdata Variable-length decoded data sequence Rdata Run-length decoded data sequence Rdata 'Run-length obtained by converting scan order Decoded data sequence 101 Decrementer 102 Register 103 Counter 104 Controller 105, 108 Selector 106 Error detector 107 Comparator G1, G2 Gate circuit EOB Block end signal halt Run-length code supply stop signal error Error signal zr Zero run lvl Level 10 Writing means 11 Adder 12 Register 13 Bank memory (storage means) BM0 Bank memory 0 BM1 Bank memory 1 14 Counter (Reading means) 15 Controller bc Bank switching signal 31 Read address generator 32 Counter 33 Address converter (address generating means) 40 Address converter (address converting means)

Continuation of the front page (56) References JP-A-3-266564 (JP, A) JP-A-4-360469 (JP, A) JP-A-5-48903 (JP, A) JP-A-4-323962 (JP) (A) JP-A-5-83564 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 7/30 H03M 7/46 H04N 7/30

Claims (5)

(57) [Claims] (1) A continuous identical value is represented by the number of consecutive times.
To decode the encoded compressed data sequence by
An information processing device having at least two storage areas,
Storage means for simultaneously writing and reading data to and from the same storage area,
Initialization that initializes by writing values continuously
Means, and an address corresponding to the number of continuations of the initialized portion.
Writing means for writing the compressed data string, and writing in a second recording area of the storage area
An information processing apparatus , comprising: reading means for reading a data string . 2. The method according to claim 1, wherein the number of consecutive times z of the same value is the same.
Compressed data represented by a set (z, d) of data values d other than the value
An information processing apparatus for decoding a data sequence , wherein: a storage unit having at least two storage areas;
Initialization that initializes by writing values continuously
Means for storing the compressed data in the initialized storage area.
The data of the (i-1) -th set (zi-1, di-1) of the data sequence.
The i-th same value is added to the address where the data value di-1 is written.
The next address is obtained by adding the number of consecutive times zi
So that the i-th data value di is written to the dress
Writing means for writing the compressed data string and the first
At the same time as the writing process to the storage area, the second storage area
To read data already written to the area
The information processing apparatus characterized by comprising a stage. 3. Data output from said reading means.
Enter a sequence and enter the scan order for the data sequence
Scan order of a different data sequence from the data sequence
Having a scan order conversion means for converting to
The information processing apparatus according to claim 1 or 2, wherein 4. A data to be read to the reading means.
Address generating means for generating an address of the data, The address generation means is configured to scan the data sequence
Of the data sequence different from the input data sequence.
Generation of the addresses so as to be in a random order.
The information processing apparatus according to claim 1 or 2, wherein 5. A data to be written to the writing means.
Address conversion means for generating data addresses, The address conversion unit is configured to scan the data sequence
Of the data sequence different from the input data sequence.
Generation of the addresses so as to be in a random order.
The information processing apparatus according to claim 1 or 2, wherein